EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
efr32mg1p_ldma.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
44  __IM uint32_t STATUS;
45  __IOM uint32_t SYNC;
46  uint32_t RESERVED0[5];
47  __IOM uint32_t CHEN;
48  __IM uint32_t CHBUSY;
49  __IOM uint32_t CHDONE;
50  __IOM uint32_t DBGHALT;
51  __IOM uint32_t SWREQ;
52  __IOM uint32_t REQDIS;
53  __IM uint32_t REQPEND;
54  __IOM uint32_t LINKLOAD;
55  __IOM uint32_t REQCLEAR;
56  uint32_t RESERVED1[7];
57  __IM uint32_t IF;
58  __IOM uint32_t IFS;
59  __IOM uint32_t IFC;
60  __IOM uint32_t IEN;
62  uint32_t RESERVED2[4];
64 } LDMA_TypeDef;
66 /**************************************************************************/
71 /* Bit fields for LDMA CTRL */
72 #define _LDMA_CTRL_RESETVALUE 0x07000000UL
73 #define _LDMA_CTRL_MASK 0x0700FFFFUL
74 #define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0
75 #define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL
76 #define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL
77 #define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0)
78 #define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8
79 #define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL
80 #define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL
81 #define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8)
82 #define _LDMA_CTRL_NUMFIXED_SHIFT 24
83 #define _LDMA_CTRL_NUMFIXED_MASK 0x7000000UL
84 #define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000007UL
85 #define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24)
87 /* Bit fields for LDMA STATUS */
88 #define _LDMA_STATUS_RESETVALUE 0x08100000UL
89 #define _LDMA_STATUS_MASK 0x1F1F073BUL
90 #define LDMA_STATUS_ANYBUSY (0x1UL << 0)
91 #define _LDMA_STATUS_ANYBUSY_SHIFT 0
92 #define _LDMA_STATUS_ANYBUSY_MASK 0x1UL
93 #define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL
94 #define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0)
95 #define LDMA_STATUS_ANYREQ (0x1UL << 1)
96 #define _LDMA_STATUS_ANYREQ_SHIFT 1
97 #define _LDMA_STATUS_ANYREQ_MASK 0x2UL
98 #define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL
99 #define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1)
100 #define _LDMA_STATUS_CHGRANT_SHIFT 3
101 #define _LDMA_STATUS_CHGRANT_MASK 0x38UL
102 #define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL
103 #define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3)
104 #define _LDMA_STATUS_CHERROR_SHIFT 8
105 #define _LDMA_STATUS_CHERROR_MASK 0x700UL
106 #define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL
107 #define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8)
108 #define _LDMA_STATUS_FIFOLEVEL_SHIFT 16
109 #define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL
110 #define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL
111 #define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16)
112 #define _LDMA_STATUS_CHNUM_SHIFT 24
113 #define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL
114 #define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL
115 #define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24)
117 /* Bit fields for LDMA SYNC */
118 #define _LDMA_SYNC_RESETVALUE 0x00000000UL
119 #define _LDMA_SYNC_MASK 0x000000FFUL
120 #define _LDMA_SYNC_SYNCTRIG_SHIFT 0
121 #define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL
122 #define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL
123 #define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0)
125 /* Bit fields for LDMA CHEN */
126 #define _LDMA_CHEN_RESETVALUE 0x00000000UL
127 #define _LDMA_CHEN_MASK 0x000000FFUL
128 #define _LDMA_CHEN_CHEN_SHIFT 0
129 #define _LDMA_CHEN_CHEN_MASK 0xFFUL
130 #define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL
131 #define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0)
133 /* Bit fields for LDMA CHBUSY */
134 #define _LDMA_CHBUSY_RESETVALUE 0x00000000UL
135 #define _LDMA_CHBUSY_MASK 0x000000FFUL
136 #define _LDMA_CHBUSY_BUSY_SHIFT 0
137 #define _LDMA_CHBUSY_BUSY_MASK 0xFFUL
138 #define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL
139 #define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0)
141 /* Bit fields for LDMA CHDONE */
142 #define _LDMA_CHDONE_RESETVALUE 0x00000000UL
143 #define _LDMA_CHDONE_MASK 0x000000FFUL
144 #define _LDMA_CHDONE_CHDONE_SHIFT 0
145 #define _LDMA_CHDONE_CHDONE_MASK 0xFFUL
146 #define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL
147 #define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0)
149 /* Bit fields for LDMA DBGHALT */
150 #define _LDMA_DBGHALT_RESETVALUE 0x00000000UL
151 #define _LDMA_DBGHALT_MASK 0x000000FFUL
152 #define _LDMA_DBGHALT_DBGHALT_SHIFT 0
153 #define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL
154 #define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL
155 #define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0)
157 /* Bit fields for LDMA SWREQ */
158 #define _LDMA_SWREQ_RESETVALUE 0x00000000UL
159 #define _LDMA_SWREQ_MASK 0x000000FFUL
160 #define _LDMA_SWREQ_SWREQ_SHIFT 0
161 #define _LDMA_SWREQ_SWREQ_MASK 0xFFUL
162 #define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL
163 #define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0)
165 /* Bit fields for LDMA REQDIS */
166 #define _LDMA_REQDIS_RESETVALUE 0x00000000UL
167 #define _LDMA_REQDIS_MASK 0x000000FFUL
168 #define _LDMA_REQDIS_REQDIS_SHIFT 0
169 #define _LDMA_REQDIS_REQDIS_MASK 0xFFUL
170 #define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL
171 #define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0)
173 /* Bit fields for LDMA REQPEND */
174 #define _LDMA_REQPEND_RESETVALUE 0x00000000UL
175 #define _LDMA_REQPEND_MASK 0x000000FFUL
176 #define _LDMA_REQPEND_REQPEND_SHIFT 0
177 #define _LDMA_REQPEND_REQPEND_MASK 0xFFUL
178 #define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL
179 #define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0)
181 /* Bit fields for LDMA LINKLOAD */
182 #define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL
183 #define _LDMA_LINKLOAD_MASK 0x000000FFUL
184 #define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0
185 #define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL
186 #define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL
187 #define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0)
189 /* Bit fields for LDMA REQCLEAR */
190 #define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL
191 #define _LDMA_REQCLEAR_MASK 0x000000FFUL
192 #define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0
193 #define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL
194 #define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL
195 #define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0)
197 /* Bit fields for LDMA IF */
198 #define _LDMA_IF_RESETVALUE 0x00000000UL
199 #define _LDMA_IF_MASK 0x800000FFUL
200 #define _LDMA_IF_DONE_SHIFT 0
201 #define _LDMA_IF_DONE_MASK 0xFFUL
202 #define _LDMA_IF_DONE_DEFAULT 0x00000000UL
203 #define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0)
204 #define LDMA_IF_ERROR (0x1UL << 31)
205 #define _LDMA_IF_ERROR_SHIFT 31
206 #define _LDMA_IF_ERROR_MASK 0x80000000UL
207 #define _LDMA_IF_ERROR_DEFAULT 0x00000000UL
208 #define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31)
210 /* Bit fields for LDMA IFS */
211 #define _LDMA_IFS_RESETVALUE 0x00000000UL
212 #define _LDMA_IFS_MASK 0x800000FFUL
213 #define _LDMA_IFS_DONE_SHIFT 0
214 #define _LDMA_IFS_DONE_MASK 0xFFUL
215 #define _LDMA_IFS_DONE_DEFAULT 0x00000000UL
216 #define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0)
217 #define LDMA_IFS_ERROR (0x1UL << 31)
218 #define _LDMA_IFS_ERROR_SHIFT 31
219 #define _LDMA_IFS_ERROR_MASK 0x80000000UL
220 #define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL
221 #define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31)
223 /* Bit fields for LDMA IFC */
224 #define _LDMA_IFC_RESETVALUE 0x00000000UL
225 #define _LDMA_IFC_MASK 0x800000FFUL
226 #define _LDMA_IFC_DONE_SHIFT 0
227 #define _LDMA_IFC_DONE_MASK 0xFFUL
228 #define _LDMA_IFC_DONE_DEFAULT 0x00000000UL
229 #define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0)
230 #define LDMA_IFC_ERROR (0x1UL << 31)
231 #define _LDMA_IFC_ERROR_SHIFT 31
232 #define _LDMA_IFC_ERROR_MASK 0x80000000UL
233 #define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL
234 #define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31)
236 /* Bit fields for LDMA IEN */
237 #define _LDMA_IEN_RESETVALUE 0x00000000UL
238 #define _LDMA_IEN_MASK 0x800000FFUL
239 #define _LDMA_IEN_DONE_SHIFT 0
240 #define _LDMA_IEN_DONE_MASK 0xFFUL
241 #define _LDMA_IEN_DONE_DEFAULT 0x00000000UL
242 #define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0)
243 #define LDMA_IEN_ERROR (0x1UL << 31)
244 #define _LDMA_IEN_ERROR_SHIFT 31
245 #define _LDMA_IEN_ERROR_MASK 0x80000000UL
246 #define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL
247 #define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31)
249 /* Bit fields for LDMA CH_REQSEL */
250 #define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL
251 #define _LDMA_CH_REQSEL_MASK 0x003F000FUL
252 #define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0
253 #define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL
254 #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL
255 #define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL
256 #define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL
257 #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL
258 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL
259 #define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL
260 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL
261 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL
262 #define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL
263 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR 0x00000000UL
264 #define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL
265 #define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL
266 #define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL
267 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL
268 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL
269 #define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL
270 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL
271 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL
272 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR 0x00000001UL
273 #define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL
274 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL
275 #define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL
276 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL
277 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL
278 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD 0x00000002UL
279 #define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL
280 #define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL
281 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL
282 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR 0x00000003UL
283 #define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL
284 #define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL
285 #define _LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD 0x00000004UL
286 #define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0)
287 #define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0)
288 #define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0)
289 #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0)
290 #define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0)
291 #define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0)
292 #define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0)
293 #define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0)
294 #define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0)
295 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR << 0)
296 #define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0)
297 #define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0)
298 #define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0)
299 #define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0)
300 #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0)
301 #define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0)
302 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0)
303 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0)
304 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR << 0)
305 #define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0)
306 #define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0)
307 #define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0)
308 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0)
309 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0)
310 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD << 0)
311 #define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0)
312 #define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0)
313 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0)
314 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR << 0)
315 #define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0)
316 #define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0)
317 #define LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD << 0)
318 #define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16
319 #define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL
320 #define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL
321 #define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL
322 #define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL
323 #define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL
324 #define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL
325 #define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000010UL
326 #define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000014UL
327 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000018UL
328 #define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x00000019UL
329 #define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL
330 #define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO 0x00000031UL
331 #define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16)
332 #define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16)
333 #define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16)
334 #define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16)
335 #define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16)
336 #define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16)
337 #define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16)
338 #define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16)
339 #define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16)
340 #define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16)
341 #define LDMA_CH_REQSEL_SOURCESEL_CRYPTO (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO << 16)
343 /* Bit fields for LDMA CH_CFG */
344 #define _LDMA_CH_CFG_RESETVALUE 0x00000000UL
345 #define _LDMA_CH_CFG_MASK 0x00330000UL
346 #define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16
347 #define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL
348 #define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL
349 #define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL
350 #define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL
351 #define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL
352 #define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL
353 #define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16)
354 #define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16)
355 #define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16)
356 #define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16)
357 #define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16)
358 #define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20)
359 #define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20
360 #define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL
361 #define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL
362 #define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL
363 #define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL
364 #define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20)
365 #define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20)
366 #define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20)
367 #define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21)
368 #define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21
369 #define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL
370 #define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL
371 #define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL
372 #define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL
373 #define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21)
374 #define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21)
375 #define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21)
377 /* Bit fields for LDMA CH_LOOP */
378 #define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL
379 #define _LDMA_CH_LOOP_MASK 0x000000FFUL
380 #define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0
381 #define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL
382 #define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL
383 #define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0)
385 /* Bit fields for LDMA CH_CTRL */
386 #define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL
387 #define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL
388 #define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0
389 #define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL
390 #define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL
391 #define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL
392 #define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL
393 #define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL
394 #define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0)
395 #define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0)
396 #define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0)
397 #define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0)
398 #define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3)
399 #define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3
400 #define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL
401 #define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL
402 #define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3)
403 #define _LDMA_CH_CTRL_XFERCNT_SHIFT 4
404 #define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL
405 #define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL
406 #define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4)
407 #define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15)
408 #define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15
409 #define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL
410 #define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL
411 #define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15)
412 #define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16
413 #define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL
414 #define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL
415 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL
416 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL
417 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL
418 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL
419 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL
420 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL
421 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL
422 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL
423 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL
424 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL
425 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL
426 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL
427 #define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL
428 #define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL
429 #define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16)
430 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16)
431 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16)
432 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16)
433 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16)
434 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16)
435 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16)
436 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16)
437 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16)
438 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16)
439 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16)
440 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16)
441 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16)
442 #define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16)
443 #define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16)
444 #define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20)
445 #define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20
446 #define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL
447 #define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL
448 #define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20)
449 #define LDMA_CH_CTRL_REQMODE (0x1UL << 21)
450 #define _LDMA_CH_CTRL_REQMODE_SHIFT 21
451 #define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL
452 #define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL
453 #define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL
454 #define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL
455 #define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21)
456 #define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21)
457 #define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21)
458 #define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22)
459 #define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22
460 #define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL
461 #define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL
462 #define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22)
463 #define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23)
464 #define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23
465 #define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL
466 #define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL
467 #define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23)
468 #define _LDMA_CH_CTRL_SRCINC_SHIFT 24
469 #define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL
470 #define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL
471 #define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL
472 #define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL
473 #define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL
474 #define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL
475 #define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24)
476 #define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24)
477 #define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24)
478 #define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24)
479 #define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24)
480 #define _LDMA_CH_CTRL_SIZE_SHIFT 26
481 #define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL
482 #define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL
483 #define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL
484 #define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL
485 #define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL
486 #define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26)
487 #define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26)
488 #define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26)
489 #define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26)
490 #define _LDMA_CH_CTRL_DSTINC_SHIFT 28
491 #define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL
492 #define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL
493 #define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL
494 #define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL
495 #define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL
496 #define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL
497 #define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28)
498 #define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28)
499 #define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28)
500 #define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28)
501 #define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28)
502 #define LDMA_CH_CTRL_SRCMODE (0x1UL << 30)
503 #define _LDMA_CH_CTRL_SRCMODE_SHIFT 30
504 #define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL
505 #define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL
506 #define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL
507 #define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL
508 #define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30)
509 #define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30)
510 #define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30)
511 #define LDMA_CH_CTRL_DSTMODE (0x1UL << 31)
512 #define _LDMA_CH_CTRL_DSTMODE_SHIFT 31
513 #define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL
514 #define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL
515 #define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL
516 #define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL
517 #define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31)
518 #define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31)
519 #define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31)
521 /* Bit fields for LDMA CH_SRC */
522 #define _LDMA_CH_SRC_RESETVALUE 0x00000000UL
523 #define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL
524 #define _LDMA_CH_SRC_SRCADDR_SHIFT 0
525 #define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL
526 #define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL
527 #define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0)
529 /* Bit fields for LDMA CH_DST */
530 #define _LDMA_CH_DST_RESETVALUE 0x00000000UL
531 #define _LDMA_CH_DST_MASK 0xFFFFFFFFUL
532 #define _LDMA_CH_DST_DSTADDR_SHIFT 0
533 #define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL
534 #define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL
535 #define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0)
537 /* Bit fields for LDMA CH_LINK */
538 #define _LDMA_CH_LINK_RESETVALUE 0x00000000UL
539 #define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL
540 #define LDMA_CH_LINK_LINKMODE (0x1UL << 0)
541 #define _LDMA_CH_LINK_LINKMODE_SHIFT 0
542 #define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL
543 #define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL
544 #define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL
545 #define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL
546 #define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0)
547 #define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0)
548 #define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0)
549 #define LDMA_CH_LINK_LINK (0x1UL << 1)
550 #define _LDMA_CH_LINK_LINK_SHIFT 1
551 #define _LDMA_CH_LINK_LINK_MASK 0x2UL
552 #define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL
553 #define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1)
554 #define _LDMA_CH_LINK_LINKADDR_SHIFT 2
555 #define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL
556 #define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL
557 #define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2)
__IOM uint32_t SWREQ
__IOM uint32_t LINKLOAD
__IOM uint32_t DBGHALT
__IOM uint32_t CHDONE
__IOM uint32_t IEN
__IM uint32_t CHBUSY
__IM uint32_t REQPEND
LDMA_CH EFR32MG1P LDMA CH.
__IOM uint32_t SYNC
__IOM uint32_t REQCLEAR
__IM uint32_t IF
__IM uint32_t STATUS
__IOM uint32_t CHEN
__IOM uint32_t IFC
__IOM uint32_t REQDIS
__IOM uint32_t IFS
__IOM uint32_t CTRL