Detailed Description

CMSIS Cortex-M Peripheral Access Layer Header File for EFR32FG1P133F256GM48.

Version: 5.1.2

License

Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:

The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
This notice may not be removed or altered from any source distribution.

DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.

Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.

Definition in file efr32fg1p133f256gm48.h.

#include "core_cm4.h"
#include "system_efr32fg1p.h"
#include "efr32fg1p_msc.h"
#include "efr32fg1p_emu.h"
#include "efr32fg1p_rmu.h"
#include "efr32fg1p_cmu.h"
#include "efr32fg1p_crypto.h"
#include "efr32fg1p_gpio_p.h"
#include "efr32fg1p_gpio.h"
#include "efr32fg1p_prs_ch.h"
#include "efr32fg1p_prs.h"
#include "efr32fg1p_ldma_ch.h"
#include "efr32fg1p_ldma.h"
#include "efr32fg1p_fpueh.h"
#include "efr32fg1p_gpcrc.h"
#include "efr32fg1p_timer_cc.h"
#include "efr32fg1p_timer.h"
#include "efr32fg1p_usart.h"
#include "efr32fg1p_leuart.h"
#include "efr32fg1p_letimer.h"
#include "efr32fg1p_cryotimer.h"
#include "efr32fg1p_pcnt.h"
#include "efr32fg1p_i2c.h"
#include "efr32fg1p_adc.h"
#include "efr32fg1p_acmp.h"
#include "efr32fg1p_idac.h"
#include "efr32fg1p_rtcc_cc.h"
#include "efr32fg1p_rtcc_ret.h"
#include "efr32fg1p_rtcc.h"
#include "efr32fg1p_wdog_pch.h"
#include "efr32fg1p_wdog.h"
#include "efr32fg1p_dma_descriptor.h"
#include "efr32fg1p_devinfo.h"
#include "efr32fg1p_romtable.h"
#include "efr32fg1p_prs_signals.h"
#include "efr32fg1p_dmareq.h"
#include "efr32fg1p_af_ports.h"
#include "efr32fg1p_af_pins.h"

Go to the source code of this file.

Macros
#define	__CM4_REV 0x001

#define	__FPU_PRESENT 1

#define	__MPU_PRESENT 1

#define	__NVIC_PRIO_BITS 3

#define	__Vendor_SysTickConfig 0

#define	__VTOR_PRESENT 1

#define	_EFR32_FLEX_FAMILY 1

#define	_EFR_DEVICE

#define	_SILICON_LABS_32B_PLATFORM 2

#define	_SILICON_LABS_32B_PLATFORM_2

#define	_SILICON_LABS_32B_PLATFORM_2_GEN 1

#define	_SILICON_LABS_32B_PLATFORM_2_GEN_1

#define	_SILICON_LABS_32B_SERIES 1

#define	_SILICON_LABS_32B_SERIES_1

#define	_SILICON_LABS_32B_SERIES_1_CONFIG 1

#define	_SILICON_LABS_32B_SERIES_1_CONFIG_1

#define	_SILICON_LABS_EFR32_RADIO_2G4HZ 2

#define	_SILICON_LABS_EFR32_RADIO_DUALBAND 3

#define	_SILICON_LABS_EFR32_RADIO_SUBGHZ 1

#define	_SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_DUALBAND

#define	_SILICON_LABS_GECKO_INTERNAL_SDID 80 /** Silicon Labs internal use only, may change any time */

#define	_SILICON_LABS_GECKO_INTERNAL_SDID_80 /** Silicon Labs internal use only, may change any time */

#define	ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)

#define	ACMP0_BASE (0x40000000UL)

#define	ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)

#define	ACMP1_BASE (0x40000400UL)

#define	ACMP_COUNT 2

#define	ACMP_OFFSET 0x400

#define	ACMP_PRESENT

#define	ADC0 ((ADC_TypeDef *) ADC0_BASE)

#define	ADC0_BASE (0x40002000UL)

#define	ADC_COUNT 1

#define	ADC_OFFSET 0x400

#define	ADC_PRESENT

#define	AFACHAN_MAX 61

#define	AFCHAN_MAX 72

#define	AFCHANLOC_MAX 32

#define	BITBAND_PER_BASE ((uint32_t) 0x42000000UL)

#define	BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)

#define	BOOTLOADER_COUNT 1

#define	BOOTLOADER_PRESENT

#define	CMU ((CMU_TypeDef *) CMU_BASE)

#define	CMU_BASE (0x400E4000UL)

#define	CMU_COUNT 1

#define	CMU_PRESENT

#define	CMU_UNLOCK_CODE 0x580E

#define	CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE)

#define	CRYOTIMER_BASE (0x4001E000UL)

#define	CRYOTIMER_COUNT 1

#define	CRYOTIMER_PRESENT

#define	CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE)

#define	CRYPTO_BASE (0x400F0000UL)

#define	CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL)

#define	CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL)

#define	CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL)

#define	CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL)

#define	CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL)

#define	CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL)

#define	CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL)

#define	CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL)

#define	CRYPTO_COUNT 1

#define	CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL)

#define	CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL)

#define	CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL)

#define	CRYPTO_MEM_SIZE ((uint32_t) 0x400UL)

#define	CRYPTO_PRESENT

#define	DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)

#define	DEVINFO_BASE (0x0FE081B0UL)

#define	DMA_CHAN_COUNT 8

#define	EMU ((EMU_TypeDef *) EMU_BASE)

#define	EMU_BASE (0x400E3000UL)

#define	EMU_COUNT 1

#define	EMU_PRESENT

#define	EMU_UNLOCK_CODE 0xADE8

#define	EXT_IRQ_COUNT 34

#define	FLASH_BASE (0x00000000UL)

#define	FLASH_MEM_BASE ((uint32_t) 0x00000000UL)

#define	FLASH_MEM_BITS ((uint32_t) 0x0000001CUL)

#define	FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL)

#define	FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)

#define	FLASH_PAGE_SIZE 2048

#define	FLASH_SIZE (0x00040000UL)

#define	FPUEH ((FPUEH_TypeDef *) FPUEH_BASE)

#define	FPUEH_BASE (0x400E1000UL)

#define	FPUEH_COUNT 1

#define	FPUEH_PRESENT

#define	GPCRC ((GPCRC_TypeDef *) GPCRC_BASE)

#define	GPCRC_BASE (0x4001C000UL)

#define	GPCRC_COUNT 1

#define	GPCRC_PRESENT

#define	GPIO ((GPIO_TypeDef *) GPIO_BASE)

#define	GPIO_BASE (0x4000A000UL)

#define	GPIO_COUNT 1

#define	GPIO_PRESENT

#define	GPIO_UNLOCK_CODE 0xA534

#define	I2C0 ((I2C_TypeDef *) I2C0_BASE)

#define	I2C0_BASE (0x4000C000UL)

#define	I2C_COUNT 1

#define	I2C_OFFSET 0x400

#define	I2C_PRESENT

#define	IDAC0 ((IDAC_TypeDef *) IDAC0_BASE)

#define	IDAC0_BASE (0x40006000UL)

#define	IDAC_COUNT 1

#define	IDAC_OFFSET 0x400

#define	IDAC_PRESENT

#define	LDMA ((LDMA_TypeDef *) LDMA_BASE)

#define	LDMA_BASE (0x400E2000UL)

#define	LDMA_COUNT 1

#define	LDMA_PRESENT

#define	LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)

#define	LETIMER0_BASE (0x40046000UL)

#define	LETIMER_COUNT 1

#define	LETIMER_OFFSET 0x400

#define	LETIMER_PRESENT

#define	LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)

#define	LEUART0_BASE (0x4004A000UL)

#define	LEUART_COUNT 1

#define	LEUART_OFFSET 0x400

#define	LEUART_PRESENT

#define	LOCKBITS_BASE (0x0FE04000UL)

#define	MSC ((MSC_TypeDef *) MSC_BASE)

#define	MSC_BASE (0x400E0000UL)

#define	MSC_COUNT 1

#define	MSC_PRESENT

#define	MSC_UNLOCK_CODE 0x1B71

#define	PART_NUMBER "EFR32FG1P133F256GM48"

#define	PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)

#define	PCNT0_BASE (0x4004E000UL)

#define	PCNT_COUNT 1

#define	PCNT_OFFSET 0x400

#define	PCNT_PRESENT

#define	PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL)

#define	PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL)

#define	PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL)

#define	PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL)

#define	PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL)

#define	PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL)

#define	PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL)

#define	PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL)

#define	PER_MEM_BASE ((uint32_t) 0x40000000UL)

#define	PER_MEM_BITS ((uint32_t) 0x00000014UL)

#define	PER_MEM_END ((uint32_t) 0x400E7FFFUL)

#define	PER_MEM_SIZE ((uint32_t) 0xE8000UL)

#define	PRS ((PRS_TypeDef *) PRS_BASE)

#define	PRS_BASE (0x400E6000UL)

#define	PRS_CHAN_COUNT 12

#define	PRS_COUNT 1

#define	PRS_PRESENT

#define	RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)

#define	RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL)

#define	RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL)

#define	RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL)

#define	RAM_MEM_BASE ((uint32_t) 0x20000000UL)

#define	RAM_MEM_BITS ((uint32_t) 0x0000000FUL)

#define	RAM_MEM_END ((uint32_t) 0x20007BFFUL)

#define	RAM_MEM_SIZE ((uint32_t) 0x7C00UL)

#define	RMU ((RMU_TypeDef *) RMU_BASE)

#define	RMU_BASE (0x400E5000UL)

#define	RMU_COUNT 1

#define	RMU_PRESENT

#define	RMU_UNLOCK_CODE 0xE084

#define	ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)

#define	ROMTABLE_BASE (0xE00FFFD0UL)

#define	RTCC ((RTCC_TypeDef *) RTCC_BASE)

#define	RTCC_BASE (0x40042000UL)

#define	RTCC_COUNT 1

#define	RTCC_PRESENT

#define	RTCC_UNLOCK_CODE 0xAEE8

#define	SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) \| (((VALUE) << (OFFSET)) & (MASK));
	Set the value of a bit field within a register. More...

#define	SRAM_BASE (0x20000000UL)

#define	SRAM_SIZE (0x00007C00UL)

#define	TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)

#define	TIMER0_BASE (0x40018000UL)

#define	TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)

#define	TIMER1_BASE (0x40018400UL)

#define	TIMER_COUNT 2

#define	TIMER_OFFSET 0x400

#define	TIMER_PRESENT

#define	TIMER_UNLOCK_CODE 0xCE80

#define	USART0 ((USART_TypeDef *) USART0_BASE)

#define	USART0_BASE (0x40010000UL)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	USART1_BASE (0x40010400UL)

#define	USART_COUNT 2

#define	USART_OFFSET 0x400

#define	USART_PRESENT

#define	USERDATA_BASE (0x0FE00000UL)

#define	WDOG0 ((WDOG_TypeDef *) WDOG0_BASE)

#define	WDOG0_BASE (0x40052000UL)

#define	WDOG_COUNT 1

#define	WDOG_OFFSET 0x400

#define	WDOG_PRESENT

Typedefs
typedef enum IRQn	IRQn_Type

Enumerations
enum	IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, EMU_IRQn = 0, WDOG0_IRQn = 2, LDMA_IRQn = 8, GPIO_EVEN_IRQn = 9, TIMER0_IRQn = 10, USART0_RX_IRQn = 11, USART0_TX_IRQn = 12, ACMP0_IRQn = 13, ADC0_IRQn = 14, IDAC0_IRQn = 15, I2C0_IRQn = 16, GPIO_ODD_IRQn = 17, TIMER1_IRQn = 18, USART1_RX_IRQn = 19, USART1_TX_IRQn = 20, LEUART0_IRQn = 21, PCNT0_IRQn = 22, CMU_IRQn = 23, MSC_IRQn = 24, CRYPTO_IRQn = 25, LETIMER0_IRQn = 26, RTCC_IRQn = 29, CRYOTIMER_IRQn = 31, FPUEH_IRQn = 33 }

Detailed Description

License

Macros

Typedefs

Enumerations