EFR32 Flex Gecko 1 Software Documentation  efr32fg1-doc-5.1.2
efr32fg1p_devinfo.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IM uint32_t CAL;
44  uint32_t RESERVED0[7];
45  __IM uint32_t EXTINFO;
46  uint32_t RESERVED1[1];
47  __IM uint32_t EUI48L;
48  __IM uint32_t EUI48H;
49  __IM uint32_t CUSTOMINFO;
50  __IM uint32_t MEMINFO;
51  uint32_t RESERVED2[2];
52  __IM uint32_t UNIQUEL;
53  __IM uint32_t UNIQUEH;
54  __IM uint32_t MSIZE;
55  __IM uint32_t PART;
56  __IM uint32_t DEVINFOREV;
57  __IM uint32_t EMUTEMP;
58  uint32_t RESERVED3[2];
59  __IM uint32_t ADC0CAL0;
60  __IM uint32_t ADC0CAL1;
61  __IM uint32_t ADC0CAL2;
62  __IM uint32_t ADC0CAL3;
63  uint32_t RESERVED4[4];
64  __IM uint32_t HFRCOCAL0;
65  uint32_t RESERVED5[2];
66  __IM uint32_t HFRCOCAL3;
67  uint32_t RESERVED6[2];
68  __IM uint32_t HFRCOCAL6;
69  __IM uint32_t HFRCOCAL7;
70  __IM uint32_t HFRCOCAL8;
71  uint32_t RESERVED7[1];
72  __IM uint32_t HFRCOCAL10;
73  __IM uint32_t HFRCOCAL11;
74  __IM uint32_t HFRCOCAL12;
75  uint32_t RESERVED8[11];
76  __IM uint32_t AUXHFRCOCAL0;
77  uint32_t RESERVED9[2];
78  __IM uint32_t AUXHFRCOCAL3;
79  uint32_t RESERVED10[2];
80  __IM uint32_t AUXHFRCOCAL6;
81  __IM uint32_t AUXHFRCOCAL7;
82  __IM uint32_t AUXHFRCOCAL8;
83  uint32_t RESERVED11[1];
84  __IM uint32_t AUXHFRCOCAL10;
85  __IM uint32_t AUXHFRCOCAL11;
86  __IM uint32_t AUXHFRCOCAL12;
87  uint32_t RESERVED12[11];
88  __IM uint32_t VMONCAL0;
89  __IM uint32_t VMONCAL1;
90  __IM uint32_t VMONCAL2;
91  uint32_t RESERVED13[3];
92  __IM uint32_t IDAC0CAL0;
93  __IM uint32_t IDAC0CAL1;
94  uint32_t RESERVED14[2];
95  __IM uint32_t DCDCLNVCTRL0;
96  __IM uint32_t DCDCLPVCTRL0;
97  __IM uint32_t DCDCLPVCTRL1;
98  __IM uint32_t DCDCLPVCTRL2;
99  __IM uint32_t DCDCLPVCTRL3;
100  __IM uint32_t DCDCLPCMPHYSSEL0;
101  __IM uint32_t DCDCLPCMPHYSSEL1;
102 } DEVINFO_TypeDef;
104 /**************************************************************************/
109 /* Bit fields for DEVINFO CAL */
110 #define _DEVINFO_CAL_MASK 0x00FFFFFFUL
111 #define _DEVINFO_CAL_CRC_SHIFT 0
112 #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL
113 #define _DEVINFO_CAL_TEMP_SHIFT 16
114 #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL
116 /* Bit fields for DEVINFO EXTINFO */
117 #define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL
118 #define _DEVINFO_EXTINFO_TYPE_SHIFT 0
119 #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL
120 #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL
121 #define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL
122 #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL
123 #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0)
124 #define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0)
125 #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0)
126 #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8
127 #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL
128 #define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL
129 #define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL
130 #define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8)
131 #define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8)
132 #define _DEVINFO_EXTINFO_REV_SHIFT 16
133 #define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL
134 #define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL
135 #define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL
136 #define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16)
137 #define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16)
139 /* Bit fields for DEVINFO EUI48L */
140 #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL
141 #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0
142 #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL
143 #define _DEVINFO_EUI48L_OUI48L_SHIFT 24
144 #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL
146 /* Bit fields for DEVINFO EUI48H */
147 #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL
148 #define _DEVINFO_EUI48H_OUI48H_SHIFT 0
149 #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL
151 /* Bit fields for DEVINFO CUSTOMINFO */
152 #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL
153 #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16
154 #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL
156 /* Bit fields for DEVINFO MEMINFO */
157 #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL
158 #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0
159 #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL
160 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL
161 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL
162 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL
163 #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL
164 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0)
165 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0)
166 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0)
167 #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0)
168 #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8
169 #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL
170 #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL
171 #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL
172 #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL
173 #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8)
174 #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8)
175 #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8)
176 #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16
177 #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL
178 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24
179 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL
181 /* Bit fields for DEVINFO UNIQUEL */
182 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL
183 #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0
184 #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL
186 /* Bit fields for DEVINFO UNIQUEH */
187 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL
188 #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0
189 #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL
191 /* Bit fields for DEVINFO MSIZE */
192 #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL
193 #define _DEVINFO_MSIZE_FLASH_SHIFT 0
194 #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL
195 #define _DEVINFO_MSIZE_SRAM_SHIFT 16
196 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL
198 /* Bit fields for DEVINFO PART */
199 #define _DEVINFO_PART_MASK 0xFFFFFFFFUL
200 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0
201 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL
202 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16
203 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL
204 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL
205 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL
206 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL
207 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL
208 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL
209 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL
210 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL
211 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL
212 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL
213 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL
214 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL
215 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL
216 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL
217 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL
218 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL
219 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL
220 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL
221 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL
222 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL
223 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL
224 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL
225 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL
226 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL
227 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL
228 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL
229 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL
230 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL
231 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL
232 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL
233 #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL
234 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL
235 #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL
236 #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL
237 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL
238 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL
239 #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL
240 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL
241 #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL
242 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL
243 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL
244 #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL
245 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL
246 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL
247 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL
248 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL
249 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL
250 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL
251 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL
252 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL
253 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL
254 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL
255 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16)
256 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16)
257 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16)
258 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16)
259 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16)
260 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16)
261 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16)
262 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16)
263 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16)
264 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16)
265 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16)
266 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16)
267 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16)
268 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16)
269 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16)
270 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16)
271 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16)
272 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16)
273 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16)
274 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16)
275 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16)
276 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16)
277 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16)
278 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16)
279 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16)
280 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16)
281 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16)
282 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16)
283 #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16)
284 #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16)
285 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16)
286 #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16)
287 #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16)
288 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16)
289 #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16)
290 #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16)
291 #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16)
292 #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16)
293 #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16)
294 #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16)
295 #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16)
296 #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16)
297 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16)
298 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16)
299 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16)
300 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16)
301 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16)
302 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16)
303 #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16)
304 #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16)
305 #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16)
306 #define _DEVINFO_PART_PROD_REV_SHIFT 24
307 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL
309 /* Bit fields for DEVINFO DEVINFOREV */
310 #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL
311 #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0
312 #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL
314 /* Bit fields for DEVINFO EMUTEMP */
315 #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL
316 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0
317 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL
319 /* Bit fields for DEVINFO ADC0CAL0 */
320 #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL
321 #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0
322 #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL
323 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4
324 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL
325 #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8
326 #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL
327 #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16
328 #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL
329 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20
330 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL
331 #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24
332 #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL
334 /* Bit fields for DEVINFO ADC0CAL1 */
335 #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL
336 #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0
337 #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL
338 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4
339 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL
340 #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8
341 #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL
342 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16
343 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL
344 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20
345 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL
346 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24
347 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL
349 /* Bit fields for DEVINFO ADC0CAL2 */
350 #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL
351 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0
352 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL
353 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4
354 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL
356 /* Bit fields for DEVINFO ADC0CAL3 */
357 #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL
358 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4
359 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL
361 /* Bit fields for DEVINFO HFRCOCAL0 */
362 #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL
363 #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0
364 #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL
365 #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8
366 #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL
367 #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16
368 #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL
369 #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21
370 #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL
371 #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24
372 #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL
373 #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25
374 #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL
375 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27
376 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL
377 #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28
378 #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL
380 /* Bit fields for DEVINFO HFRCOCAL3 */
381 #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL
382 #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0
383 #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL
384 #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8
385 #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL
386 #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16
387 #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL
388 #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21
389 #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL
390 #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24
391 #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL
392 #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25
393 #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL
394 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27
395 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL
396 #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28
397 #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL
399 /* Bit fields for DEVINFO HFRCOCAL6 */
400 #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL
401 #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0
402 #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL
403 #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8
404 #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL
405 #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16
406 #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL
407 #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21
408 #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL
409 #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24
410 #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL
411 #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25
412 #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL
413 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27
414 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL
415 #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28
416 #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL
418 /* Bit fields for DEVINFO HFRCOCAL7 */
419 #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL
420 #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0
421 #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL
422 #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8
423 #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL
424 #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16
425 #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL
426 #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21
427 #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL
428 #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24
429 #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL
430 #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25
431 #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL
432 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27
433 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL
434 #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28
435 #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL
437 /* Bit fields for DEVINFO HFRCOCAL8 */
438 #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL
439 #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0
440 #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL
441 #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8
442 #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL
443 #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16
444 #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL
445 #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21
446 #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL
447 #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24
448 #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL
449 #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25
450 #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL
451 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27
452 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL
453 #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28
454 #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL
456 /* Bit fields for DEVINFO HFRCOCAL10 */
457 #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL
458 #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0
459 #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL
460 #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8
461 #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL
462 #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16
463 #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL
464 #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21
465 #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL
466 #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24
467 #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL
468 #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25
469 #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL
470 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27
471 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL
472 #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28
473 #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL
475 /* Bit fields for DEVINFO HFRCOCAL11 */
476 #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL
477 #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0
478 #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL
479 #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8
480 #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL
481 #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16
482 #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL
483 #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21
484 #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL
485 #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24
486 #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL
487 #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25
488 #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL
489 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27
490 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL
491 #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28
492 #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL
494 /* Bit fields for DEVINFO HFRCOCAL12 */
495 #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL
496 #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0
497 #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL
498 #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8
499 #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL
500 #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16
501 #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL
502 #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21
503 #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL
504 #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24
505 #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL
506 #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25
507 #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL
508 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27
509 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL
510 #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28
511 #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL
513 /* Bit fields for DEVINFO AUXHFRCOCAL0 */
514 #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL
515 #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0
516 #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL
517 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8
518 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL
519 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16
520 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL
521 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21
522 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL
523 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24
524 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL
525 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25
526 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL
527 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27
528 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL
529 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28
530 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL
532 /* Bit fields for DEVINFO AUXHFRCOCAL3 */
533 #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL
534 #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0
535 #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL
536 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8
537 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL
538 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16
539 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL
540 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21
541 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL
542 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24
543 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL
544 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25
545 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL
546 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27
547 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL
548 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28
549 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL
551 /* Bit fields for DEVINFO AUXHFRCOCAL6 */
552 #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL
553 #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0
554 #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL
555 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8
556 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL
557 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16
558 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL
559 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21
560 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL
561 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24
562 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL
563 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25
564 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL
565 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27
566 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL
567 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28
568 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL
570 /* Bit fields for DEVINFO AUXHFRCOCAL7 */
571 #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL
572 #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0
573 #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL
574 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8
575 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL
576 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16
577 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL
578 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21
579 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL
580 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24
581 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL
582 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25
583 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL
584 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27
585 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL
586 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28
587 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL
589 /* Bit fields for DEVINFO AUXHFRCOCAL8 */
590 #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL
591 #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0
592 #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL
593 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8
594 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL
595 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16
596 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL
597 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21
598 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL
599 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24
600 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL
601 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25
602 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL
603 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27
604 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL
605 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28
606 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL
608 /* Bit fields for DEVINFO AUXHFRCOCAL10 */
609 #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL
610 #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0
611 #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL
612 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8
613 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL
614 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16
615 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL
616 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21
617 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL
618 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24
619 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL
620 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25
621 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL
622 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27
623 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL
624 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28
625 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL
627 /* Bit fields for DEVINFO AUXHFRCOCAL11 */
628 #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL
629 #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0
630 #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL
631 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8
632 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL
633 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16
634 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL
635 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21
636 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL
637 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24
638 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL
639 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25
640 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL
641 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27
642 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL
643 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28
644 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL
646 /* Bit fields for DEVINFO AUXHFRCOCAL12 */
647 #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL
648 #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0
649 #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL
650 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8
651 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL
652 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16
653 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL
654 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21
655 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL
656 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24
657 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL
658 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25
659 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL
660 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27
661 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL
662 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28
663 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL
665 /* Bit fields for DEVINFO VMONCAL0 */
666 #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL
667 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0
668 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL
669 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4
670 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL
671 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8
672 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL
673 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12
674 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL
675 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16
676 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL
677 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20
678 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL
679 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24
680 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL
681 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28
682 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL
684 /* Bit fields for DEVINFO VMONCAL1 */
685 #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL
686 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0
687 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL
688 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4
689 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL
690 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8
691 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL
692 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12
693 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL
694 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16
695 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL
696 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20
697 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL
698 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24
699 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL
700 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28
701 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL
703 /* Bit fields for DEVINFO VMONCAL2 */
704 #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL
705 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0
706 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL
707 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4
708 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL
709 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8
710 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL
711 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12
712 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL
713 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16
714 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL
715 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20
716 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL
717 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24
718 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL
719 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28
720 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL
722 /* Bit fields for DEVINFO IDAC0CAL0 */
723 #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL
724 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0
725 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL
726 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8
727 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL
728 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16
729 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL
730 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24
731 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL
733 /* Bit fields for DEVINFO IDAC0CAL1 */
734 #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL
735 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0
736 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL
737 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8
738 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL
739 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16
740 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL
741 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24
742 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL
744 /* Bit fields for DEVINFO DCDCLNVCTRL0 */
745 #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL
746 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0
747 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL
748 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8
749 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL
750 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16
751 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL
752 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24
753 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL
755 /* Bit fields for DEVINFO DCDCLPVCTRL0 */
756 #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL
757 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0
758 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL
759 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8
760 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL
761 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16
762 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL
763 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24
764 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL
766 /* Bit fields for DEVINFO DCDCLPVCTRL1 */
767 #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL
768 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0
769 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL
770 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8
771 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL
772 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16
773 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL
774 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24
775 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL
777 /* Bit fields for DEVINFO DCDCLPVCTRL2 */
778 #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL
779 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0
780 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL
781 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8
782 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL
783 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16
784 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL
785 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24
786 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL
788 /* Bit fields for DEVINFO DCDCLPVCTRL3 */
789 #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL
790 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0
791 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL
792 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8
793 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL
794 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16
795 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL
796 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24
797 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL
799 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
800 #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL
801 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0
802 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL
803 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8
804 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL
806 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
807 #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL
808 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0
809 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL
810 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8
811 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL
812 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16
813 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL
814 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24
815 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL
__IM uint32_t UNIQUEH
__IM uint32_t HFRCOCAL12
__IM uint32_t DCDCLPVCTRL1
__IM uint32_t EUI48L
__IM uint32_t AUXHFRCOCAL11
__IM uint32_t AUXHFRCOCAL8
__IM uint32_t EUI48H
__IM uint32_t VMONCAL1
__IM uint32_t HFRCOCAL10
__IM uint32_t AUXHFRCOCAL6
__IM uint32_t DCDCLPVCTRL2
__IM uint32_t DCDCLPCMPHYSSEL0
__IM uint32_t DCDCLPCMPHYSSEL1
__IM uint32_t IDAC0CAL1
__IM uint32_t EMUTEMP
__IM uint32_t HFRCOCAL3
__IM uint32_t AUXHFRCOCAL0
__IM uint32_t DCDCLPVCTRL3
__IM uint32_t AUXHFRCOCAL7
__IM uint32_t AUXHFRCOCAL10
__IM uint32_t ADC0CAL3
__IM uint32_t CUSTOMINFO
__IM uint32_t HFRCOCAL7
__IM uint32_t AUXHFRCOCAL3
__IM uint32_t VMONCAL0
__IM uint32_t MSIZE
__IM uint32_t DCDCLNVCTRL0
__IM uint32_t ADC0CAL0
__IM uint32_t HFRCOCAL6
__IM uint32_t MEMINFO
__IM uint32_t IDAC0CAL0
__IM uint32_t HFRCOCAL11
__IM uint32_t EXTINFO
__IM uint32_t ADC0CAL1
__IM uint32_t DEVINFOREV
__IM uint32_t VMONCAL2
__IM uint32_t PART
__IM uint32_t HFRCOCAL8
__IM uint32_t AUXHFRCOCAL12
__IM uint32_t UNIQUEL
__IM uint32_t CAL
__IM uint32_t ADC0CAL2
__IM uint32_t HFRCOCAL0
__IM uint32_t DCDCLPVCTRL0