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EFR32 Blue Gecko 1 Software Documentation
efr32bg1-doc-5.1.2
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EFR32 Blue Gecko 1 Software Documentation
efr32bg1-doc-5.1.2
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| #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) |
ACMP0 base pointer
Definition at line 353 of file efr32bg1p333f256gm48.h.
Referenced by CAPLESENSE_setupACMP().
| #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) |
ACMP1 base pointer
Definition at line 354 of file efr32bg1p333f256gm48.h.
Referenced by CAPLESENSE_setupACMP().
| #define ADC0 ((ADC_TypeDef *) ADC0_BASE) |
ADC0 base pointer
Definition at line 352 of file efr32bg1p333f256gm48.h.
Referenced by ADC0_IRQHandler(), ADC_Init(), adcInit(), getAdcSample(), MIC_init(), MIC_start(), TOUCH_GetPos(), and TOUCH_Init().
| #define CMU ((CMU_TypeDef *) CMU_BASE) |
CMU base pointer
Definition at line 336 of file efr32bg1p333f256gm48.h.
Referenced by adcDeInit(), BSP_TraceSwoSetup(), CAPSENSE_Init(), CHIP_Init(), CMU_AUXHFRCOBandSet(), CMU_Calibrate(), CMU_CalibrateConfig(), CMU_CalibrateCont(), CMU_CalibrateCountGet(), CMU_CalibrateStart(), CMU_CalibrateStop(), CMU_ClockDivGet(), CMU_ClockDivSet(), CMU_ClockEnable(), CMU_ClockFreqGet(), CMU_ClockPrescGet(), CMU_ClockPrescSet(), CMU_ClockSelectGet(), CMU_ClockSelectSet(), CMU_FreezeEnable(), CMU_HFRCOBandSet(), CMU_HFXOAutostartEnable(), CMU_HFXOInit(), CMU_IntClear(), CMU_IntDisable(), CMU_IntEnable(), CMU_IntGet(), CMU_IntGetEnabled(), CMU_IntSet(), CMU_LCDClkFDIVGet(), CMU_LCDClkFDIVSet(), CMU_LFXOInit(), CMU_Lock(), CMU_OscillatorEnable(), CMU_OscillatorTuningGet(), CMU_OscillatorTuningOptimize(), CMU_OscillatorTuningSet(), CMU_OscillatorTuningWait(), CMU_PCNTClockExternalGet(), CMU_PCNTClockExternalSet(), CMU_Unlock(), EMU_EnterEM3(), MIC_init(), RTCC_Lock(), RTCC_Unlock(), SegmentLCD_Disable(), SegmentLCD_Init(), SystemCoreClockGet(), SystemHFClockGet(), SystemHFXOClockSet(), SystemLFXOClockSet(), UARTDRV_InitLeuart(), and UDELAY_Calibrate().
| #define CRYOTIMER ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) |
CRYOTIMER base pointer
Definition at line 349 of file efr32bg1p333f256gm48.h.
Referenced by CRYOTIMER_CounterGet(), CRYOTIMER_EM4WakeupEnable(), CRYOTIMER_Enable(), CRYOTIMER_Init(), CRYOTIMER_IntClear(), CRYOTIMER_IntDisable(), CRYOTIMER_IntEnable(), CRYOTIMER_IntGet(), CRYOTIMER_IntGetEnabled(), CRYOTIMER_IntSet(), CRYOTIMER_PeriodGet(), and CRYOTIMER_PeriodSet().
| #define CRYPTO ((CRYPTO_TypeDef *) CRYPTO_BASE) |
CRYPTO base pointer
Definition at line 337 of file efr32bg1p333f256gm48.h.
Referenced by AES_CBC128(), AES_CBC256(), AES_CFB128(), AES_CFB256(), AES_CTR128(), AES_CTR256(), AES_DecryptKey128(), AES_DecryptKey256(), AES_ECB128(), AES_ECB256(), AES_OFB128(), and AES_OFB256().
| #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) |
DEVINFO base pointer
Definition at line 358 of file efr32bg1p333f256gm48.h.
Referenced by CMU_AUXHFRCODevinfoGet(), CMU_HFRCODevinfoGet(), EMU_DCDCOutputVoltageSet(), IDAC_RangeSet(), SYSTEM_GetCalibrationTemperature(), SYSTEM_GetDevinfoRev(), SYSTEM_GetFamily(), SYSTEM_GetFlashPageSize(), SYSTEM_GetFlashSize(), SYSTEM_GetPartNumber(), SYSTEM_GetProdRev(), SYSTEM_GetSRAMSize(), SYSTEM_GetUnique(), and TEMPDRV_Init().
| #define EMU ((EMU_TypeDef *) EMU_BASE) |
EMU base pointer
Definition at line 334 of file efr32bg1p333f256gm48.h.
Referenced by CMU_HFXOInit(), CMU_LFXOInit(), EMU_DCDCConductionModeSet(), EMU_DCDCInit(), EMU_DCDCLnRcoBandSet(), EMU_DCDCModeSet(), EMU_DCDCOptimizeSlice(), EMU_DCDCOutputVoltageSet(), EMU_DCDCPowerOff(), EMU_EM23Init(), EMU_EM2Block(), EMU_EM2UnBlock(), EMU_EM4Init(), EMU_EnterEM4(), EMU_EnterEM4H(), EMU_EnterEM4S(), EMU_IntClear(), EMU_IntDisable(), EMU_IntEnable(), EMU_IntGet(), EMU_IntGetEnabled(), EMU_IntSet(), EMU_Lock(), EMU_MemPwrDown(), EMU_PowerLock(), EMU_PowerUnlock(), EMU_RamPowerDown(), EMU_UnlatchPinRetention(), EMU_Unlock(), EMU_VmonChannelStatusGet(), EMU_VmonEnable(), EMU_VmonHystInit(), EMU_VmonInit(), EMU_VmonStatusGet(), errataStateUpdate(), GPIO_EM4SetPinRetention(), MSC_ErasePage(), MSC_Init(), RMU_ResetCauseClear(), TEMPDRV_GetTemp(), and updateInterrupts().
| #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) |
FPUEH base pointer
Definition at line 341 of file efr32bg1p333f256gm48.h.
| #define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) |
GPCRC base pointer
Definition at line 342 of file efr32bg1p333f256gm48.h.
| #define GPIO ((GPIO_TypeDef *) GPIO_BASE) |
GPIO base pointer
Definition at line 338 of file efr32bg1p333f256gm48.h.
Referenced by BSP_TraceSwoSetup(), CHIP_Init(), GPIO_DbgLocationSet(), GPIO_DbgSWDClkEnable(), GPIO_DbgSWDIOEnable(), GPIO_DbgSWOEnable(), GPIO_DriveStrengthSet(), GPIO_EM4DisablePinWakeup(), GPIO_EM4EnablePinWakeup(), GPIO_EM4GetPinWakeupCause(), GPIO_EM4SetPinRetention(), GPIO_ExtIntConfig(), GPIO_InputSenseSet(), GPIO_IntClear(), GPIO_IntDisable(), GPIO_IntEnable(), GPIO_IntGet(), GPIO_IntGetEnabled(), GPIO_IntSet(), GPIO_Lock(), GPIO_PinInGet(), GPIO_PinModeGet(), GPIO_PinModeSet(), GPIO_PinOutClear(), GPIO_PinOutGet(), GPIO_PinOutSet(), GPIO_PinOutToggle(), GPIO_PortInGet(), GPIO_PortOutClear(), GPIO_PortOutGet(), GPIO_PortOutSet(), GPIO_PortOutSetVal(), GPIO_PortOutToggle(), GPIO_SlewrateSet(), GPIO_Unlock(), MICROSD_Deselect(), and MICROSD_Select().
| #define I2C0 ((I2C_TypeDef *) I2C0_BASE) |
I2C0 base pointer
Definition at line 351 of file efr32bg1p333f256gm48.h.
Referenced by I2C_Transfer(), I2C_TransferInit(), I2CSPM_Init(), performI2CTransfer(), and setupI2C().
| #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) |
IDAC0 base pointer
Definition at line 355 of file efr32bg1p333f256gm48.h.
Referenced by IDAC_RangeSet().
| #define LDMA ((LDMA_TypeDef *) LDMA_BASE) |
LDMA base pointer
Definition at line 340 of file efr32bg1p333f256gm48.h.
Referenced by DMADRV_TransferActive(), DMADRV_TransferCompletePending(), LDMA_DeInit(), LDMA_EnableChannelRequest(), LDMA_Init(), LDMA_IntClear(), LDMA_IntDisable(), LDMA_IntEnable(), LDMA_IntGet(), LDMA_IntGetEnabled(), LDMA_IntSet(), LDMA_StartTransfer(), LDMA_StopTransfer(), LDMA_TransferDone(), and LDMA_TransferRemainingCount().
| #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) |
LETIMER0 base pointer
Definition at line 348 of file efr32bg1p333f256gm48.h.
| #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) |
LEUART0 base pointer
Definition at line 347 of file efr32bg1p333f256gm48.h.
Referenced by LEUART_BaudrateGet(), LEUART_BaudrateSet(), and UARTDRV_InitLeuart().
| #define MSC ((MSC_TypeDef *) MSC_BASE) |
MSC base pointer
Definition at line 333 of file efr32bg1p333f256gm48.h.
Referenced by CHIP_Init(), MSC_Deinit(), MSC_EnableAutoCacheFlush(), MSC_EnableCache(), MSC_EnableCacheIRQs(), MSC_ErasePage(), MSC_ExecConfigSet(), MSC_FlushCache(), MSC_GetCacheMeasurement(), MSC_Init(), MSC_IntClear(), MSC_IntDisable(), MSC_IntEnable(), MSC_IntGet(), MSC_IntGetEnabled(), MSC_IntSet(), MSC_MassErase(), and MSC_StartCacheMeasurement().
| #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) |
PCNT0 base pointer
Definition at line 350 of file efr32bg1p333f256gm48.h.
Referenced by PCNT_CounterTopSet(), PCNT_Init(), and PCNT_TopSet().
| #define PRS ((PRS_TypeDef *) PRS_BASE) |
PRS base pointer
Definition at line 339 of file efr32bg1p333f256gm48.h.
Referenced by BOARD_init(), CAPSENSE_Init(), ezradio_hal_GpioInit(), PRS_LevelSet(), PRS_PulseTrigger(), PRS_SourceAsyncSignalSet(), and PRS_SourceSignalSet().
| #define RMU ((RMU_TypeDef *) RMU_BASE) |
RMU base pointer
Definition at line 335 of file efr32bg1p333f256gm48.h.
Referenced by RMU_ResetCauseClear(), RMU_ResetCauseGet(), RMU_ResetControl(), RMU_UserResetStateGet(), and RMU_UserResetStateSet().
| #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) |
ROMTABLE base pointer
Definition at line 359 of file efr32bg1p333f256gm48.h.
Referenced by SYSTEM_ChipRevisionGet().
| #define RTCC ((RTCC_TypeDef *) RTCC_BASE) |
RTCC base pointer
Definition at line 356 of file efr32bg1p333f256gm48.h.
Referenced by RTCC_ChannelCCVGet(), RTCC_ChannelCCVSet(), RTCC_ChannelDateGet(), RTCC_ChannelDateSet(), RTCC_ChannelInit(), RTCC_ChannelTimeGet(), RTCC_ChannelTimeSet(), RTCC_CombinedCounterGet(), RTCC_CounterGet(), RTCC_CounterSet(), RTCC_DateGet(), RTCC_DateSet(), RTCC_EM4WakeupEnable(), RTCC_Enable(), RTCC_Init(), RTCC_IntClear(), RTCC_IntDisable(), RTCC_IntEnable(), RTCC_IntGet(), RTCC_IntGetEnabled(), RTCC_IntSet(), RTCC_Lock(), RTCC_PreCounterGet(), RTCC_PreCounterSet(), RTCC_Reset(), RTCC_RetentionRamPowerDown(), RTCC_StatusClear(), RTCC_StatusGet(), RTCC_TimeGet(), RTCC_TimeSet(), RTCC_Unlock(), and UDELAY_Calibrate().
| #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) |
TIMER0 base pointer
Definition at line 343 of file efr32bg1p333f256gm48.h.
Referenced by CAPSENSE_Init(), CAPSENSE_Measure(), TIMER0_IRQHandler(), TIMER_ClearDTIFault(), TIMER_EnableDTI(), TIMER_GetDTIFault(), TIMER_InitDTI(), TIMER_Lock(), TIMER_Unlock(), and TIMER_Valid().
| #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) |
TIMER1 base pointer
Definition at line 344 of file efr32bg1p333f256gm48.h.
Referenced by CAPSENSE_Init(), CAPSENSE_Measure(), TIMER0_IRQHandler(), and TIMER_Valid().
| #define USART0 ((USART_TypeDef *) USART0_BASE) |
USART0 base pointer
Definition at line 345 of file efr32bg1p333f256gm48.h.
Referenced by SPIDRV_Init(), UARTDRV_InitUart(), and USART_InitIrDA().
| #define USART1 ((USART_TypeDef *) USART1_BASE) |
USART1 base pointer
Definition at line 346 of file efr32bg1p333f256gm48.h.
Referenced by SPI_TFT_Init(), SPI_TFT_WriteRegister(), SPIDRV_Init(), UARTDRV_InitUart(), and USART_InitIrDA().
| #define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) |
WDOG0 base pointer
Definition at line 357 of file efr32bg1p333f256gm48.h.
1.8.10 
