EFR32 Blue Gecko 1 Software Documentation  efr32bg1-doc-5.1.2
efr32bg1p_rtcc.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
44  __IOM uint32_t PRECNT;
45  __IOM uint32_t CNT;
46  __IM uint32_t COMBCNT;
47  __IOM uint32_t TIME;
48  __IOM uint32_t DATE;
49  __IM uint32_t IF;
50  __IOM uint32_t IFS;
51  __IOM uint32_t IFC;
52  __IOM uint32_t IEN;
53  __IM uint32_t STATUS;
54  __IOM uint32_t CMD;
55  __IM uint32_t SYNCBUSY;
56  __IOM uint32_t POWERDOWN;
57  __IOM uint32_t LOCK;
58  __IOM uint32_t EM4WUEN;
62  uint32_t RESERVED0[37];
63  RTCC_RET_TypeDef RET[32];
64 } RTCC_TypeDef;
66 /**************************************************************************/
71 /* Bit fields for RTCC CTRL */
72 #define _RTCC_CTRL_RESETVALUE 0x00000000UL
73 #define _RTCC_CTRL_MASK 0x00039F35UL
74 #define RTCC_CTRL_ENABLE (0x1UL << 0)
75 #define _RTCC_CTRL_ENABLE_SHIFT 0
76 #define _RTCC_CTRL_ENABLE_MASK 0x1UL
77 #define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL
78 #define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0)
79 #define RTCC_CTRL_DEBUGRUN (0x1UL << 2)
80 #define _RTCC_CTRL_DEBUGRUN_SHIFT 2
81 #define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL
82 #define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL
83 #define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2)
84 #define RTCC_CTRL_PRECCV0TOP (0x1UL << 4)
85 #define _RTCC_CTRL_PRECCV0TOP_SHIFT 4
86 #define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL
87 #define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL
88 #define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4)
89 #define RTCC_CTRL_CCV1TOP (0x1UL << 5)
90 #define _RTCC_CTRL_CCV1TOP_SHIFT 5
91 #define _RTCC_CTRL_CCV1TOP_MASK 0x20UL
92 #define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL
93 #define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5)
94 #define _RTCC_CTRL_CNTPRESC_SHIFT 8
95 #define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL
96 #define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL
97 #define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL
98 #define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL
99 #define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL
100 #define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL
101 #define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL
102 #define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL
103 #define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL
104 #define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL
105 #define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL
106 #define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL
107 #define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL
108 #define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL
109 #define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL
110 #define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL
111 #define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL
112 #define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL
113 #define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8)
114 #define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8)
115 #define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8)
116 #define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8)
117 #define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8)
118 #define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8)
119 #define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8)
120 #define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8)
121 #define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8)
122 #define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8)
123 #define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8)
124 #define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8)
125 #define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8)
126 #define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8)
127 #define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8)
128 #define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8)
129 #define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8)
130 #define RTCC_CTRL_CNTTICK (0x1UL << 12)
131 #define _RTCC_CTRL_CNTTICK_SHIFT 12
132 #define _RTCC_CTRL_CNTTICK_MASK 0x1000UL
133 #define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL
134 #define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL
135 #define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL
136 #define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12)
137 #define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12)
138 #define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12)
139 #define RTCC_CTRL_OSCFDETEN (0x1UL << 15)
140 #define _RTCC_CTRL_OSCFDETEN_SHIFT 15
141 #define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL
142 #define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL
143 #define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15)
144 #define RTCC_CTRL_CNTMODE (0x1UL << 16)
145 #define _RTCC_CTRL_CNTMODE_SHIFT 16
146 #define _RTCC_CTRL_CNTMODE_MASK 0x10000UL
147 #define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL
148 #define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL
149 #define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL
150 #define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16)
151 #define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16)
152 #define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16)
153 #define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17)
154 #define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17
155 #define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL
156 #define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL
157 #define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17)
159 /* Bit fields for RTCC PRECNT */
160 #define _RTCC_PRECNT_RESETVALUE 0x00000000UL
161 #define _RTCC_PRECNT_MASK 0x00007FFFUL
162 #define _RTCC_PRECNT_PRECNT_SHIFT 0
163 #define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL
164 #define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL
165 #define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0)
167 /* Bit fields for RTCC CNT */
168 #define _RTCC_CNT_RESETVALUE 0x00000000UL
169 #define _RTCC_CNT_MASK 0xFFFFFFFFUL
170 #define _RTCC_CNT_CNT_SHIFT 0
171 #define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL
172 #define _RTCC_CNT_CNT_DEFAULT 0x00000000UL
173 #define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0)
175 /* Bit fields for RTCC COMBCNT */
176 #define _RTCC_COMBCNT_RESETVALUE 0x00000000UL
177 #define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL
178 #define _RTCC_COMBCNT_PRECNT_SHIFT 0
179 #define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL
180 #define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL
181 #define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0)
182 #define _RTCC_COMBCNT_CNTLSB_SHIFT 15
183 #define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL
184 #define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL
185 #define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15)
187 /* Bit fields for RTCC TIME */
188 #define _RTCC_TIME_RESETVALUE 0x00000000UL
189 #define _RTCC_TIME_MASK 0x003F7F7FUL
190 #define _RTCC_TIME_SECU_SHIFT 0
191 #define _RTCC_TIME_SECU_MASK 0xFUL
192 #define _RTCC_TIME_SECU_DEFAULT 0x00000000UL
193 #define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0)
194 #define _RTCC_TIME_SECT_SHIFT 4
195 #define _RTCC_TIME_SECT_MASK 0x70UL
196 #define _RTCC_TIME_SECT_DEFAULT 0x00000000UL
197 #define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4)
198 #define _RTCC_TIME_MINU_SHIFT 8
199 #define _RTCC_TIME_MINU_MASK 0xF00UL
200 #define _RTCC_TIME_MINU_DEFAULT 0x00000000UL
201 #define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8)
202 #define _RTCC_TIME_MINT_SHIFT 12
203 #define _RTCC_TIME_MINT_MASK 0x7000UL
204 #define _RTCC_TIME_MINT_DEFAULT 0x00000000UL
205 #define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12)
206 #define _RTCC_TIME_HOURU_SHIFT 16
207 #define _RTCC_TIME_HOURU_MASK 0xF0000UL
208 #define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL
209 #define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16)
210 #define _RTCC_TIME_HOURT_SHIFT 20
211 #define _RTCC_TIME_HOURT_MASK 0x300000UL
212 #define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL
213 #define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20)
215 /* Bit fields for RTCC DATE */
216 #define _RTCC_DATE_RESETVALUE 0x00000000UL
217 #define _RTCC_DATE_MASK 0x07FF1F3FUL
218 #define _RTCC_DATE_DAYOMU_SHIFT 0
219 #define _RTCC_DATE_DAYOMU_MASK 0xFUL
220 #define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL
221 #define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0)
222 #define _RTCC_DATE_DAYOMT_SHIFT 4
223 #define _RTCC_DATE_DAYOMT_MASK 0x30UL
224 #define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL
225 #define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4)
226 #define _RTCC_DATE_MONTHU_SHIFT 8
227 #define _RTCC_DATE_MONTHU_MASK 0xF00UL
228 #define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL
229 #define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8)
230 #define RTCC_DATE_MONTHT (0x1UL << 12)
231 #define _RTCC_DATE_MONTHT_SHIFT 12
232 #define _RTCC_DATE_MONTHT_MASK 0x1000UL
233 #define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL
234 #define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12)
235 #define _RTCC_DATE_YEARU_SHIFT 16
236 #define _RTCC_DATE_YEARU_MASK 0xF0000UL
237 #define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL
238 #define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16)
239 #define _RTCC_DATE_YEART_SHIFT 20
240 #define _RTCC_DATE_YEART_MASK 0xF00000UL
241 #define _RTCC_DATE_YEART_DEFAULT 0x00000000UL
242 #define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20)
243 #define _RTCC_DATE_DAYOW_SHIFT 24
244 #define _RTCC_DATE_DAYOW_MASK 0x7000000UL
245 #define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL
246 #define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24)
248 /* Bit fields for RTCC IF */
249 #define _RTCC_IF_RESETVALUE 0x00000000UL
250 #define _RTCC_IF_MASK 0x000007FFUL
251 #define RTCC_IF_OF (0x1UL << 0)
252 #define _RTCC_IF_OF_SHIFT 0
253 #define _RTCC_IF_OF_MASK 0x1UL
254 #define _RTCC_IF_OF_DEFAULT 0x00000000UL
255 #define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0)
256 #define RTCC_IF_CC0 (0x1UL << 1)
257 #define _RTCC_IF_CC0_SHIFT 1
258 #define _RTCC_IF_CC0_MASK 0x2UL
259 #define _RTCC_IF_CC0_DEFAULT 0x00000000UL
260 #define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1)
261 #define RTCC_IF_CC1 (0x1UL << 2)
262 #define _RTCC_IF_CC1_SHIFT 2
263 #define _RTCC_IF_CC1_MASK 0x4UL
264 #define _RTCC_IF_CC1_DEFAULT 0x00000000UL
265 #define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2)
266 #define RTCC_IF_CC2 (0x1UL << 3)
267 #define _RTCC_IF_CC2_SHIFT 3
268 #define _RTCC_IF_CC2_MASK 0x8UL
269 #define _RTCC_IF_CC2_DEFAULT 0x00000000UL
270 #define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3)
271 #define RTCC_IF_OSCFAIL (0x1UL << 4)
272 #define _RTCC_IF_OSCFAIL_SHIFT 4
273 #define _RTCC_IF_OSCFAIL_MASK 0x10UL
274 #define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL
275 #define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4)
276 #define RTCC_IF_CNTTICK (0x1UL << 5)
277 #define _RTCC_IF_CNTTICK_SHIFT 5
278 #define _RTCC_IF_CNTTICK_MASK 0x20UL
279 #define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL
280 #define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5)
281 #define RTCC_IF_MINTICK (0x1UL << 6)
282 #define _RTCC_IF_MINTICK_SHIFT 6
283 #define _RTCC_IF_MINTICK_MASK 0x40UL
284 #define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL
285 #define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6)
286 #define RTCC_IF_HOURTICK (0x1UL << 7)
287 #define _RTCC_IF_HOURTICK_SHIFT 7
288 #define _RTCC_IF_HOURTICK_MASK 0x80UL
289 #define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL
290 #define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7)
291 #define RTCC_IF_DAYTICK (0x1UL << 8)
292 #define _RTCC_IF_DAYTICK_SHIFT 8
293 #define _RTCC_IF_DAYTICK_MASK 0x100UL
294 #define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL
295 #define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8)
296 #define RTCC_IF_DAYOWOF (0x1UL << 9)
297 #define _RTCC_IF_DAYOWOF_SHIFT 9
298 #define _RTCC_IF_DAYOWOF_MASK 0x200UL
299 #define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL
300 #define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9)
301 #define RTCC_IF_MONTHTICK (0x1UL << 10)
302 #define _RTCC_IF_MONTHTICK_SHIFT 10
303 #define _RTCC_IF_MONTHTICK_MASK 0x400UL
304 #define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL
305 #define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10)
307 /* Bit fields for RTCC IFS */
308 #define _RTCC_IFS_RESETVALUE 0x00000000UL
309 #define _RTCC_IFS_MASK 0x000007FFUL
310 #define RTCC_IFS_OF (0x1UL << 0)
311 #define _RTCC_IFS_OF_SHIFT 0
312 #define _RTCC_IFS_OF_MASK 0x1UL
313 #define _RTCC_IFS_OF_DEFAULT 0x00000000UL
314 #define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0)
315 #define RTCC_IFS_CC0 (0x1UL << 1)
316 #define _RTCC_IFS_CC0_SHIFT 1
317 #define _RTCC_IFS_CC0_MASK 0x2UL
318 #define _RTCC_IFS_CC0_DEFAULT 0x00000000UL
319 #define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1)
320 #define RTCC_IFS_CC1 (0x1UL << 2)
321 #define _RTCC_IFS_CC1_SHIFT 2
322 #define _RTCC_IFS_CC1_MASK 0x4UL
323 #define _RTCC_IFS_CC1_DEFAULT 0x00000000UL
324 #define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2)
325 #define RTCC_IFS_CC2 (0x1UL << 3)
326 #define _RTCC_IFS_CC2_SHIFT 3
327 #define _RTCC_IFS_CC2_MASK 0x8UL
328 #define _RTCC_IFS_CC2_DEFAULT 0x00000000UL
329 #define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3)
330 #define RTCC_IFS_OSCFAIL (0x1UL << 4)
331 #define _RTCC_IFS_OSCFAIL_SHIFT 4
332 #define _RTCC_IFS_OSCFAIL_MASK 0x10UL
333 #define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL
334 #define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4)
335 #define RTCC_IFS_CNTTICK (0x1UL << 5)
336 #define _RTCC_IFS_CNTTICK_SHIFT 5
337 #define _RTCC_IFS_CNTTICK_MASK 0x20UL
338 #define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL
339 #define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5)
340 #define RTCC_IFS_MINTICK (0x1UL << 6)
341 #define _RTCC_IFS_MINTICK_SHIFT 6
342 #define _RTCC_IFS_MINTICK_MASK 0x40UL
343 #define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL
344 #define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6)
345 #define RTCC_IFS_HOURTICK (0x1UL << 7)
346 #define _RTCC_IFS_HOURTICK_SHIFT 7
347 #define _RTCC_IFS_HOURTICK_MASK 0x80UL
348 #define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL
349 #define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7)
350 #define RTCC_IFS_DAYTICK (0x1UL << 8)
351 #define _RTCC_IFS_DAYTICK_SHIFT 8
352 #define _RTCC_IFS_DAYTICK_MASK 0x100UL
353 #define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL
354 #define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8)
355 #define RTCC_IFS_DAYOWOF (0x1UL << 9)
356 #define _RTCC_IFS_DAYOWOF_SHIFT 9
357 #define _RTCC_IFS_DAYOWOF_MASK 0x200UL
358 #define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL
359 #define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9)
360 #define RTCC_IFS_MONTHTICK (0x1UL << 10)
361 #define _RTCC_IFS_MONTHTICK_SHIFT 10
362 #define _RTCC_IFS_MONTHTICK_MASK 0x400UL
363 #define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL
364 #define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10)
366 /* Bit fields for RTCC IFC */
367 #define _RTCC_IFC_RESETVALUE 0x00000000UL
368 #define _RTCC_IFC_MASK 0x000007FFUL
369 #define RTCC_IFC_OF (0x1UL << 0)
370 #define _RTCC_IFC_OF_SHIFT 0
371 #define _RTCC_IFC_OF_MASK 0x1UL
372 #define _RTCC_IFC_OF_DEFAULT 0x00000000UL
373 #define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0)
374 #define RTCC_IFC_CC0 (0x1UL << 1)
375 #define _RTCC_IFC_CC0_SHIFT 1
376 #define _RTCC_IFC_CC0_MASK 0x2UL
377 #define _RTCC_IFC_CC0_DEFAULT 0x00000000UL
378 #define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1)
379 #define RTCC_IFC_CC1 (0x1UL << 2)
380 #define _RTCC_IFC_CC1_SHIFT 2
381 #define _RTCC_IFC_CC1_MASK 0x4UL
382 #define _RTCC_IFC_CC1_DEFAULT 0x00000000UL
383 #define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2)
384 #define RTCC_IFC_CC2 (0x1UL << 3)
385 #define _RTCC_IFC_CC2_SHIFT 3
386 #define _RTCC_IFC_CC2_MASK 0x8UL
387 #define _RTCC_IFC_CC2_DEFAULT 0x00000000UL
388 #define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3)
389 #define RTCC_IFC_OSCFAIL (0x1UL << 4)
390 #define _RTCC_IFC_OSCFAIL_SHIFT 4
391 #define _RTCC_IFC_OSCFAIL_MASK 0x10UL
392 #define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL
393 #define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4)
394 #define RTCC_IFC_CNTTICK (0x1UL << 5)
395 #define _RTCC_IFC_CNTTICK_SHIFT 5
396 #define _RTCC_IFC_CNTTICK_MASK 0x20UL
397 #define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL
398 #define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5)
399 #define RTCC_IFC_MINTICK (0x1UL << 6)
400 #define _RTCC_IFC_MINTICK_SHIFT 6
401 #define _RTCC_IFC_MINTICK_MASK 0x40UL
402 #define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL
403 #define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6)
404 #define RTCC_IFC_HOURTICK (0x1UL << 7)
405 #define _RTCC_IFC_HOURTICK_SHIFT 7
406 #define _RTCC_IFC_HOURTICK_MASK 0x80UL
407 #define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL
408 #define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7)
409 #define RTCC_IFC_DAYTICK (0x1UL << 8)
410 #define _RTCC_IFC_DAYTICK_SHIFT 8
411 #define _RTCC_IFC_DAYTICK_MASK 0x100UL
412 #define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL
413 #define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8)
414 #define RTCC_IFC_DAYOWOF (0x1UL << 9)
415 #define _RTCC_IFC_DAYOWOF_SHIFT 9
416 #define _RTCC_IFC_DAYOWOF_MASK 0x200UL
417 #define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL
418 #define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9)
419 #define RTCC_IFC_MONTHTICK (0x1UL << 10)
420 #define _RTCC_IFC_MONTHTICK_SHIFT 10
421 #define _RTCC_IFC_MONTHTICK_MASK 0x400UL
422 #define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL
423 #define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10)
425 /* Bit fields for RTCC IEN */
426 #define _RTCC_IEN_RESETVALUE 0x00000000UL
427 #define _RTCC_IEN_MASK 0x000007FFUL
428 #define RTCC_IEN_OF (0x1UL << 0)
429 #define _RTCC_IEN_OF_SHIFT 0
430 #define _RTCC_IEN_OF_MASK 0x1UL
431 #define _RTCC_IEN_OF_DEFAULT 0x00000000UL
432 #define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0)
433 #define RTCC_IEN_CC0 (0x1UL << 1)
434 #define _RTCC_IEN_CC0_SHIFT 1
435 #define _RTCC_IEN_CC0_MASK 0x2UL
436 #define _RTCC_IEN_CC0_DEFAULT 0x00000000UL
437 #define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1)
438 #define RTCC_IEN_CC1 (0x1UL << 2)
439 #define _RTCC_IEN_CC1_SHIFT 2
440 #define _RTCC_IEN_CC1_MASK 0x4UL
441 #define _RTCC_IEN_CC1_DEFAULT 0x00000000UL
442 #define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2)
443 #define RTCC_IEN_CC2 (0x1UL << 3)
444 #define _RTCC_IEN_CC2_SHIFT 3
445 #define _RTCC_IEN_CC2_MASK 0x8UL
446 #define _RTCC_IEN_CC2_DEFAULT 0x00000000UL
447 #define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3)
448 #define RTCC_IEN_OSCFAIL (0x1UL << 4)
449 #define _RTCC_IEN_OSCFAIL_SHIFT 4
450 #define _RTCC_IEN_OSCFAIL_MASK 0x10UL
451 #define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL
452 #define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4)
453 #define RTCC_IEN_CNTTICK (0x1UL << 5)
454 #define _RTCC_IEN_CNTTICK_SHIFT 5
455 #define _RTCC_IEN_CNTTICK_MASK 0x20UL
456 #define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL
457 #define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5)
458 #define RTCC_IEN_MINTICK (0x1UL << 6)
459 #define _RTCC_IEN_MINTICK_SHIFT 6
460 #define _RTCC_IEN_MINTICK_MASK 0x40UL
461 #define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL
462 #define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6)
463 #define RTCC_IEN_HOURTICK (0x1UL << 7)
464 #define _RTCC_IEN_HOURTICK_SHIFT 7
465 #define _RTCC_IEN_HOURTICK_MASK 0x80UL
466 #define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL
467 #define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7)
468 #define RTCC_IEN_DAYTICK (0x1UL << 8)
469 #define _RTCC_IEN_DAYTICK_SHIFT 8
470 #define _RTCC_IEN_DAYTICK_MASK 0x100UL
471 #define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL
472 #define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8)
473 #define RTCC_IEN_DAYOWOF (0x1UL << 9)
474 #define _RTCC_IEN_DAYOWOF_SHIFT 9
475 #define _RTCC_IEN_DAYOWOF_MASK 0x200UL
476 #define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL
477 #define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9)
478 #define RTCC_IEN_MONTHTICK (0x1UL << 10)
479 #define _RTCC_IEN_MONTHTICK_SHIFT 10
480 #define _RTCC_IEN_MONTHTICK_MASK 0x400UL
481 #define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL
482 #define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10)
484 /* Bit fields for RTCC STATUS */
485 #define _RTCC_STATUS_RESETVALUE 0x00000000UL
486 #define _RTCC_STATUS_MASK 0x00000000UL
488 /* Bit fields for RTCC CMD */
489 #define _RTCC_CMD_RESETVALUE 0x00000000UL
490 #define _RTCC_CMD_MASK 0x00000001UL
491 #define RTCC_CMD_CLRSTATUS (0x1UL << 0)
492 #define _RTCC_CMD_CLRSTATUS_SHIFT 0
493 #define _RTCC_CMD_CLRSTATUS_MASK 0x1UL
494 #define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL
495 #define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0)
497 /* Bit fields for RTCC SYNCBUSY */
498 #define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL
499 #define _RTCC_SYNCBUSY_MASK 0x00000020UL
500 #define RTCC_SYNCBUSY_CMD (0x1UL << 5)
501 #define _RTCC_SYNCBUSY_CMD_SHIFT 5
502 #define _RTCC_SYNCBUSY_CMD_MASK 0x20UL
503 #define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL
504 #define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5)
506 /* Bit fields for RTCC POWERDOWN */
507 #define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL
508 #define _RTCC_POWERDOWN_MASK 0x00000001UL
509 #define RTCC_POWERDOWN_RAM (0x1UL << 0)
510 #define _RTCC_POWERDOWN_RAM_SHIFT 0
511 #define _RTCC_POWERDOWN_RAM_MASK 0x1UL
512 #define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL
513 #define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0)
515 /* Bit fields for RTCC LOCK */
516 #define _RTCC_LOCK_RESETVALUE 0x00000000UL
517 #define _RTCC_LOCK_MASK 0x0000FFFFUL
518 #define _RTCC_LOCK_LOCKKEY_SHIFT 0
519 #define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL
520 #define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
521 #define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL
522 #define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
523 #define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL
524 #define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL
525 #define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0)
526 #define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0)
527 #define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0)
528 #define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0)
529 #define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0)
531 /* Bit fields for RTCC EM4WUEN */
532 #define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL
533 #define _RTCC_EM4WUEN_MASK 0x00000001UL
534 #define RTCC_EM4WUEN_EM4WU (0x1UL << 0)
535 #define _RTCC_EM4WUEN_EM4WU_SHIFT 0
536 #define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL
537 #define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL
538 #define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0)
540 /* Bit fields for RTCC CC_CTRL */
541 #define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL
542 #define _RTCC_CC_CTRL_MASK 0x0003FBFFUL
543 #define _RTCC_CC_CTRL_MODE_SHIFT 0
544 #define _RTCC_CC_CTRL_MODE_MASK 0x3UL
545 #define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL
546 #define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL
547 #define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL
548 #define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL
549 #define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0)
550 #define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0)
551 #define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0)
552 #define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0)
553 #define _RTCC_CC_CTRL_CMOA_SHIFT 2
554 #define _RTCC_CC_CTRL_CMOA_MASK 0xCUL
555 #define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL
556 #define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL
557 #define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL
558 #define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL
559 #define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL
560 #define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2)
561 #define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2)
562 #define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2)
563 #define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2)
564 #define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2)
565 #define _RTCC_CC_CTRL_ICEDGE_SHIFT 4
566 #define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL
567 #define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL
568 #define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL
569 #define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL
570 #define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL
571 #define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL
572 #define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4)
573 #define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4)
574 #define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4)
575 #define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4)
576 #define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4)
577 #define _RTCC_CC_CTRL_PRSSEL_SHIFT 6
578 #define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL
579 #define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL
580 #define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL
581 #define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL
582 #define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL
583 #define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL
584 #define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL
585 #define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL
586 #define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL
587 #define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL
588 #define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL
589 #define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL
590 #define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL
591 #define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL
592 #define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6)
593 #define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6)
594 #define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6)
595 #define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6)
596 #define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6)
597 #define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6)
598 #define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6)
599 #define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6)
600 #define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6)
601 #define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6)
602 #define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6)
603 #define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6)
604 #define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6)
605 #define RTCC_CC_CTRL_COMPBASE (0x1UL << 11)
606 #define _RTCC_CC_CTRL_COMPBASE_SHIFT 11
607 #define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL
608 #define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL
609 #define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL
610 #define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL
611 #define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11)
612 #define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11)
613 #define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11)
614 #define _RTCC_CC_CTRL_COMPMASK_SHIFT 12
615 #define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL
616 #define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL
617 #define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12)
618 #define RTCC_CC_CTRL_DAYCC (0x1UL << 17)
619 #define _RTCC_CC_CTRL_DAYCC_SHIFT 17
620 #define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL
621 #define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL
622 #define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL
623 #define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL
624 #define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17)
625 #define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17)
626 #define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17)
628 /* Bit fields for RTCC CC_CCV */
629 #define _RTCC_CC_CCV_RESETVALUE 0x00000000UL
630 #define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL
631 #define _RTCC_CC_CCV_CCV_SHIFT 0
632 #define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL
633 #define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL
634 #define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0)
636 /* Bit fields for RTCC CC_TIME */
637 #define _RTCC_CC_TIME_RESETVALUE 0x00000000UL
638 #define _RTCC_CC_TIME_MASK 0x003F7F7FUL
639 #define _RTCC_CC_TIME_SECU_SHIFT 0
640 #define _RTCC_CC_TIME_SECU_MASK 0xFUL
641 #define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL
642 #define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0)
643 #define _RTCC_CC_TIME_SECT_SHIFT 4
644 #define _RTCC_CC_TIME_SECT_MASK 0x70UL
645 #define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL
646 #define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4)
647 #define _RTCC_CC_TIME_MINU_SHIFT 8
648 #define _RTCC_CC_TIME_MINU_MASK 0xF00UL
649 #define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL
650 #define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8)
651 #define _RTCC_CC_TIME_MINT_SHIFT 12
652 #define _RTCC_CC_TIME_MINT_MASK 0x7000UL
653 #define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL
654 #define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12)
655 #define _RTCC_CC_TIME_HOURU_SHIFT 16
656 #define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL
657 #define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL
658 #define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16)
659 #define _RTCC_CC_TIME_HOURT_SHIFT 20
660 #define _RTCC_CC_TIME_HOURT_MASK 0x300000UL
661 #define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL
662 #define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20)
664 /* Bit fields for RTCC CC_DATE */
665 #define _RTCC_CC_DATE_RESETVALUE 0x00000000UL
666 #define _RTCC_CC_DATE_MASK 0x00001F3FUL
667 #define _RTCC_CC_DATE_DAYU_SHIFT 0
668 #define _RTCC_CC_DATE_DAYU_MASK 0xFUL
669 #define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL
670 #define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0)
671 #define _RTCC_CC_DATE_DAYT_SHIFT 4
672 #define _RTCC_CC_DATE_DAYT_MASK 0x30UL
673 #define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL
674 #define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4)
675 #define _RTCC_CC_DATE_MONTHU_SHIFT 8
676 #define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL
677 #define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL
678 #define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8)
679 #define RTCC_CC_DATE_MONTHT (0x1UL << 12)
680 #define _RTCC_CC_DATE_MONTHT_SHIFT 12
681 #define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL
682 #define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL
683 #define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12)
685 /* Bit fields for RTCC RET_REG */
686 #define _RTCC_RET_REG_RESETVALUE 0x00000000UL
687 #define _RTCC_RET_REG_MASK 0xFFFFFFFFUL
688 #define _RTCC_RET_REG_REG_SHIFT 0
689 #define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL
690 #define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL
691 #define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0)
__IOM uint32_t POWERDOWN
__IOM uint32_t IFS
__IOM uint32_t CNT
__IOM uint32_t CMD
__IOM uint32_t IEN
__IOM uint32_t DATE
__IOM uint32_t TIME
__IOM uint32_t IFC
__IOM uint32_t EM4WUEN
__IM uint32_t SYNCBUSY
__IM uint32_t STATUS
__IOM uint32_t PRECNT
RTCC_CC EFR32BG1P RTCC CC.
RTCC_RET EFR32BG1P RTCC RET.
__IM uint32_t COMBCNT
__IOM uint32_t LOCK
__IOM uint32_t CTRL
__IM uint32_t IF