Detailed Description

EFM32ZG_DMA register and bit field definitions.

Version: 5.1.2

License

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Definition in file efm32zg_dma.h.

Go to the source code of this file.

Data Structures
struct	DMA_TypeDef

Macros
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000040UL

#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0

#define	_DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_ALTCTRLBASE_RESETVALUE 0x00000040UL

#define	_DMA_CH_CTRL_MASK 0x003F000FUL

#define	_DMA_CH_CTRL_RESETVALUE 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_MASK 0xFUL

#define	_DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_SHIFT 0

#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL

#define	_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL

#define	_DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL

#define	_DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL

#define	_DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL

#define	_DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL

#define	_DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL

#define	_DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL

#define	_DMA_CH_CTRL_SOURCESEL_SHIFT 16

#define	_DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL

#define	_DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL

#define	_DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL

#define	_DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH0ALTC_MASK 0x1UL

#define	_DMA_CHALTC_CH0ALTC_SHIFT 0

#define	_DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH1ALTC_MASK 0x2UL

#define	_DMA_CHALTC_CH1ALTC_SHIFT 1

#define	_DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH2ALTC_MASK 0x4UL

#define	_DMA_CHALTC_CH2ALTC_SHIFT 2

#define	_DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH3ALTC_MASK 0x8UL

#define	_DMA_CHALTC_CH3ALTC_SHIFT 3

#define	_DMA_CHALTC_MASK 0x0000000FUL

#define	_DMA_CHALTC_RESETVALUE 0x00000000UL

#define	_DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH0ALTS_MASK 0x1UL

#define	_DMA_CHALTS_CH0ALTS_SHIFT 0

#define	_DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH1ALTS_MASK 0x2UL

#define	_DMA_CHALTS_CH1ALTS_SHIFT 1

#define	_DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH2ALTS_MASK 0x4UL

#define	_DMA_CHALTS_CH2ALTS_SHIFT 2

#define	_DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH3ALTS_MASK 0x8UL

#define	_DMA_CHALTS_CH3ALTS_SHIFT 3

#define	_DMA_CHALTS_MASK 0x0000000FUL

#define	_DMA_CHALTS_RESETVALUE 0x00000000UL

#define	_DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH0ENC_MASK 0x1UL

#define	_DMA_CHENC_CH0ENC_SHIFT 0

#define	_DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH1ENC_MASK 0x2UL

#define	_DMA_CHENC_CH1ENC_SHIFT 1

#define	_DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH2ENC_MASK 0x4UL

#define	_DMA_CHENC_CH2ENC_SHIFT 2

#define	_DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH3ENC_MASK 0x8UL

#define	_DMA_CHENC_CH3ENC_SHIFT 3

#define	_DMA_CHENC_MASK 0x0000000FUL

#define	_DMA_CHENC_RESETVALUE 0x00000000UL

#define	_DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH0ENS_MASK 0x1UL

#define	_DMA_CHENS_CH0ENS_SHIFT 0

#define	_DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH1ENS_MASK 0x2UL

#define	_DMA_CHENS_CH1ENS_SHIFT 1

#define	_DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH2ENS_MASK 0x4UL

#define	_DMA_CHENS_CH2ENS_SHIFT 2

#define	_DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH3ENS_MASK 0x8UL

#define	_DMA_CHENS_CH3ENS_SHIFT 3

#define	_DMA_CHENS_MASK 0x0000000FUL

#define	_DMA_CHENS_RESETVALUE 0x00000000UL

#define	_DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH0PRIC_MASK 0x1UL

#define	_DMA_CHPRIC_CH0PRIC_SHIFT 0

#define	_DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH1PRIC_MASK 0x2UL

#define	_DMA_CHPRIC_CH1PRIC_SHIFT 1

#define	_DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH2PRIC_MASK 0x4UL

#define	_DMA_CHPRIC_CH2PRIC_SHIFT 2

#define	_DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH3PRIC_MASK 0x8UL

#define	_DMA_CHPRIC_CH3PRIC_SHIFT 3

#define	_DMA_CHPRIC_MASK 0x0000000FUL

#define	_DMA_CHPRIC_RESETVALUE 0x00000000UL

#define	_DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH0PRIS_MASK 0x1UL

#define	_DMA_CHPRIS_CH0PRIS_SHIFT 0

#define	_DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH1PRIS_MASK 0x2UL

#define	_DMA_CHPRIS_CH1PRIS_SHIFT 1

#define	_DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH2PRIS_MASK 0x4UL

#define	_DMA_CHPRIS_CH2PRIS_SHIFT 2

#define	_DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH3PRIS_MASK 0x8UL

#define	_DMA_CHPRIS_CH3PRIS_SHIFT 3

#define	_DMA_CHPRIS_MASK 0x0000000FUL

#define	_DMA_CHPRIS_RESETVALUE 0x00000000UL

#define	_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL

#define	_DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0

#define	_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL

#define	_DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1

#define	_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL

#define	_DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2

#define	_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL

#define	_DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3

#define	_DMA_CHREQMASKC_MASK 0x0000000FUL

#define	_DMA_CHREQMASKC_RESETVALUE 0x00000000UL

#define	_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL

#define	_DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0

#define	_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL

#define	_DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1

#define	_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL

#define	_DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2

#define	_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL

#define	_DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3

#define	_DMA_CHREQMASKS_MASK 0x0000000FUL

#define	_DMA_CHREQMASKS_RESETVALUE 0x00000000UL

#define	_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL

#define	_DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0

#define	_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL

#define	_DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1

#define	_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL

#define	_DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2

#define	_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL

#define	_DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3

#define	_DMA_CHREQSTATUS_MASK 0x0000000FUL

#define	_DMA_CHREQSTATUS_RESETVALUE 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL

#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0

#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL

#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1

#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL

#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2

#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL

#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3

#define	_DMA_CHSREQSTATUS_MASK 0x0000000FUL

#define	_DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL

#define	_DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL

#define	_DMA_CHSWREQ_CH0SWREQ_SHIFT 0

#define	_DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL

#define	_DMA_CHSWREQ_CH1SWREQ_SHIFT 1

#define	_DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL

#define	_DMA_CHSWREQ_CH2SWREQ_SHIFT 2

#define	_DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL

#define	_DMA_CHSWREQ_CH3SWREQ_SHIFT 3

#define	_DMA_CHSWREQ_MASK 0x0000000FUL

#define	_DMA_CHSWREQ_RESETVALUE 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL

#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0

#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL

#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1

#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL

#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2

#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL

#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3

#define	_DMA_CHUSEBURSTC_MASK 0x0000000FUL

#define	_DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL

#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1

#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL

#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2

#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL

#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3

#define	_DMA_CHUSEBURSTS_MASK 0x0000000FUL

#define	_DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL

#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL

#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0

#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL

#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1

#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL

#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2

#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL

#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3

#define	_DMA_CHWAITSTATUS_MASK 0x0000000FUL

#define	_DMA_CHWAITSTATUS_RESETVALUE 0x0000000FUL

#define	_DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL

#define	_DMA_CONFIG_CHPROT_MASK 0x20UL

#define	_DMA_CONFIG_CHPROT_SHIFT 5

#define	_DMA_CONFIG_EN_DEFAULT 0x00000000UL

#define	_DMA_CONFIG_EN_MASK 0x1UL

#define	_DMA_CONFIG_EN_SHIFT 0

#define	_DMA_CONFIG_MASK 0x00000021UL

#define	_DMA_CONFIG_RESETVALUE 0x00000000UL

#define	_DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL

#define	_DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_CTRLBASE_CTRLBASE_SHIFT 0

#define	_DMA_CTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_CTRLBASE_RESETVALUE 0x00000000UL

#define	_DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL

#define	_DMA_ERRORC_ERRORC_MASK 0x1UL

#define	_DMA_ERRORC_ERRORC_SHIFT 0

#define	_DMA_ERRORC_MASK 0x00000001UL

#define	_DMA_ERRORC_RESETVALUE 0x00000000UL

#define	_DMA_IEN_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH0DONE_MASK 0x1UL

#define	_DMA_IEN_CH0DONE_SHIFT 0

#define	_DMA_IEN_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH1DONE_MASK 0x2UL

#define	_DMA_IEN_CH1DONE_SHIFT 1

#define	_DMA_IEN_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH2DONE_MASK 0x4UL

#define	_DMA_IEN_CH2DONE_SHIFT 2

#define	_DMA_IEN_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH3DONE_MASK 0x8UL

#define	_DMA_IEN_CH3DONE_SHIFT 3

#define	_DMA_IEN_ERR_DEFAULT 0x00000000UL

#define	_DMA_IEN_ERR_MASK 0x80000000UL

#define	_DMA_IEN_ERR_SHIFT 31

#define	_DMA_IEN_MASK 0x8000000FUL

#define	_DMA_IEN_RESETVALUE 0x00000000UL

#define	_DMA_IF_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH0DONE_MASK 0x1UL

#define	_DMA_IF_CH0DONE_SHIFT 0

#define	_DMA_IF_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH1DONE_MASK 0x2UL

#define	_DMA_IF_CH1DONE_SHIFT 1

#define	_DMA_IF_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH2DONE_MASK 0x4UL

#define	_DMA_IF_CH2DONE_SHIFT 2

#define	_DMA_IF_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH3DONE_MASK 0x8UL

#define	_DMA_IF_CH3DONE_SHIFT 3

#define	_DMA_IF_ERR_DEFAULT 0x00000000UL

#define	_DMA_IF_ERR_MASK 0x80000000UL

#define	_DMA_IF_ERR_SHIFT 31

#define	_DMA_IF_MASK 0x8000000FUL

#define	_DMA_IF_RESETVALUE 0x00000000UL

#define	_DMA_IFC_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH0DONE_MASK 0x1UL

#define	_DMA_IFC_CH0DONE_SHIFT 0

#define	_DMA_IFC_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH1DONE_MASK 0x2UL

#define	_DMA_IFC_CH1DONE_SHIFT 1

#define	_DMA_IFC_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH2DONE_MASK 0x4UL

#define	_DMA_IFC_CH2DONE_SHIFT 2

#define	_DMA_IFC_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH3DONE_MASK 0x8UL

#define	_DMA_IFC_CH3DONE_SHIFT 3

#define	_DMA_IFC_ERR_DEFAULT 0x00000000UL

#define	_DMA_IFC_ERR_MASK 0x80000000UL

#define	_DMA_IFC_ERR_SHIFT 31

#define	_DMA_IFC_MASK 0x8000000FUL

#define	_DMA_IFC_RESETVALUE 0x00000000UL

#define	_DMA_IFS_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH0DONE_MASK 0x1UL

#define	_DMA_IFS_CH0DONE_SHIFT 0

#define	_DMA_IFS_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH1DONE_MASK 0x2UL

#define	_DMA_IFS_CH1DONE_SHIFT 1

#define	_DMA_IFS_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH2DONE_MASK 0x4UL

#define	_DMA_IFS_CH2DONE_SHIFT 2

#define	_DMA_IFS_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH3DONE_MASK 0x8UL

#define	_DMA_IFS_CH3DONE_SHIFT 3

#define	_DMA_IFS_ERR_DEFAULT 0x00000000UL

#define	_DMA_IFS_ERR_MASK 0x80000000UL

#define	_DMA_IFS_ERR_SHIFT 31

#define	_DMA_IFS_MASK 0x8000000FUL

#define	_DMA_IFS_RESETVALUE 0x00000000UL

#define	_DMA_STATUS_CHNUM_DEFAULT 0x00000003UL

#define	_DMA_STATUS_CHNUM_MASK 0x1F0000UL

#define	_DMA_STATUS_CHNUM_SHIFT 16

#define	_DMA_STATUS_EN_DEFAULT 0x00000000UL

#define	_DMA_STATUS_EN_MASK 0x1UL

#define	_DMA_STATUS_EN_SHIFT 0

#define	_DMA_STATUS_MASK 0x001F00F1UL

#define	_DMA_STATUS_RESETVALUE 0x10030000UL

#define	_DMA_STATUS_STATE_DEFAULT 0x00000000UL

#define	_DMA_STATUS_STATE_DONE 0x00000009UL

#define	_DMA_STATUS_STATE_IDLE 0x00000000UL

#define	_DMA_STATUS_STATE_MASK 0xF0UL

#define	_DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL

#define	_DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL

#define	_DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL

#define	_DMA_STATUS_STATE_RDSRCDATA 0x00000004UL

#define	_DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL

#define	_DMA_STATUS_STATE_SHIFT 4

#define	_DMA_STATUS_STATE_STALLED 0x00000008UL

#define	_DMA_STATUS_STATE_WAITREQCLR 0x00000006UL

#define	_DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL

#define	_DMA_STATUS_STATE_WRDSTDATA 0x00000005UL

#define	DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)

#define	DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)

#define	DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)

#define	DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)

#define	DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)

#define	DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)

#define	DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)

#define	DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)

#define	DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)

#define	DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0)

#define	DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)

#define	DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)

#define	DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16)

#define	DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)

#define	DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)

#define	DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)

#define	DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)

#define	DMA_CHALTC_CH0ALTC (0x1UL << 0)

#define	DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)

#define	DMA_CHALTC_CH1ALTC (0x1UL << 1)

#define	DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)

#define	DMA_CHALTC_CH2ALTC (0x1UL << 2)

#define	DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)

#define	DMA_CHALTC_CH3ALTC (0x1UL << 3)

#define	DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)

#define	DMA_CHALTS_CH0ALTS (0x1UL << 0)

#define	DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)

#define	DMA_CHALTS_CH1ALTS (0x1UL << 1)

#define	DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)

#define	DMA_CHALTS_CH2ALTS (0x1UL << 2)

#define	DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)

#define	DMA_CHALTS_CH3ALTS (0x1UL << 3)

#define	DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)

#define	DMA_CHENC_CH0ENC (0x1UL << 0)

#define	DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)

#define	DMA_CHENC_CH1ENC (0x1UL << 1)

#define	DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)

#define	DMA_CHENC_CH2ENC (0x1UL << 2)

#define	DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)

#define	DMA_CHENC_CH3ENC (0x1UL << 3)

#define	DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)

#define	DMA_CHENS_CH0ENS (0x1UL << 0)

#define	DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)

#define	DMA_CHENS_CH1ENS (0x1UL << 1)

#define	DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)

#define	DMA_CHENS_CH2ENS (0x1UL << 2)

#define	DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)

#define	DMA_CHENS_CH3ENS (0x1UL << 3)

#define	DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)

#define	DMA_CHPRIC_CH0PRIC (0x1UL << 0)

#define	DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)

#define	DMA_CHPRIC_CH1PRIC (0x1UL << 1)

#define	DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)

#define	DMA_CHPRIC_CH2PRIC (0x1UL << 2)

#define	DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)

#define	DMA_CHPRIC_CH3PRIC (0x1UL << 3)

#define	DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)

#define	DMA_CHPRIS_CH0PRIS (0x1UL << 0)

#define	DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)

#define	DMA_CHPRIS_CH1PRIS (0x1UL << 1)

#define	DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)

#define	DMA_CHPRIS_CH2PRIS (0x1UL << 2)

#define	DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)

#define	DMA_CHPRIS_CH3PRIS (0x1UL << 3)

#define	DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)

#define	DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)

#define	DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)

#define	DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)

#define	DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)

#define	DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)

#define	DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)

#define	DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)

#define	DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)

#define	DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)

#define	DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)

#define	DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)

#define	DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)

#define	DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)

#define	DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)

#define	DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)

#define	DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)

#define	DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)

#define	DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)

#define	DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)

#define	DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)

#define	DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)

#define	DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)

#define	DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)

#define	DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)

#define	DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)

#define	DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)

#define	DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)

#define	DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)

#define	DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)

#define	DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)

#define	DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)

#define	DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)

#define	DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)

#define	DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)

#define	DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)

#define	DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)

#define	DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)

#define	DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)

#define	DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)

#define	DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)

#define	DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)

#define	DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)

#define	DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)

#define	DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)

#define	DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)

#define	DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)

#define	DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)

#define	DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)

#define	DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)

#define	DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)

#define	DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)

#define	DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)

#define	DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)

#define	DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)

#define	DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)

#define	DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)

#define	DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)

#define	DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)

#define	DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)

#define	DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)

#define	DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)

#define	DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)

#define	DMA_CONFIG_CHPROT (0x1UL << 5)

#define	DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)

#define	DMA_CONFIG_EN (0x1UL << 0)

#define	DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)

#define	DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)

#define	DMA_ERRORC_ERRORC (0x1UL << 0)

#define	DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)

#define	DMA_IEN_CH0DONE (0x1UL << 0)

#define	DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)

#define	DMA_IEN_CH1DONE (0x1UL << 1)

#define	DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)

#define	DMA_IEN_CH2DONE (0x1UL << 2)

#define	DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)

#define	DMA_IEN_CH3DONE (0x1UL << 3)

#define	DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)

#define	DMA_IEN_ERR (0x1UL << 31)

#define	DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)

#define	DMA_IF_CH0DONE (0x1UL << 0)

#define	DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)

#define	DMA_IF_CH1DONE (0x1UL << 1)

#define	DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)

#define	DMA_IF_CH2DONE (0x1UL << 2)

#define	DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)

#define	DMA_IF_CH3DONE (0x1UL << 3)

#define	DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)

#define	DMA_IF_ERR (0x1UL << 31)

#define	DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)

#define	DMA_IFC_CH0DONE (0x1UL << 0)

#define	DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)

#define	DMA_IFC_CH1DONE (0x1UL << 1)

#define	DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)

#define	DMA_IFC_CH2DONE (0x1UL << 2)

#define	DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)

#define	DMA_IFC_CH3DONE (0x1UL << 3)

#define	DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)

#define	DMA_IFC_ERR (0x1UL << 31)

#define	DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)

#define	DMA_IFS_CH0DONE (0x1UL << 0)

#define	DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)

#define	DMA_IFS_CH1DONE (0x1UL << 1)

#define	DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1)

#define	DMA_IFS_CH2DONE (0x1UL << 2)

#define	DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2)

#define	DMA_IFS_CH3DONE (0x1UL << 3)

#define	DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3)

#define	DMA_IFS_ERR (0x1UL << 31)

#define	DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31)

#define	DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16)

#define	DMA_STATUS_EN (0x1UL << 0)

#define	DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0)

#define	DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4)

#define	DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4)

#define	DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4)

#define	DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4)

#define	DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)

#define	DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4)

#define	DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4)

#define	DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4)

#define	DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4)

#define	DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4)

#define	DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)

#define	DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4)

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