EFM32 Zero Gecko Software Documentation  efm32zg-doc-5.1.2
Macros
EFM32ZG_DMA_BitFields
Devices

Detailed Description

Macros

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   0x00000040UL
 
#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK   0xFFFFFFFFUL
 
#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT   0
 
#define _DMA_ALTCTRLBASE_MASK   0xFFFFFFFFUL
 
#define _DMA_ALTCTRLBASE_RESETVALUE   0x00000040UL
 
#define _DMA_CH_CTRL_MASK   0x003F000FUL
 
#define _DMA_CH_CTRL_RESETVALUE   0x00000000UL
 
#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN   0x00000001UL
 
#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE   0x00000000UL
 
#define _DMA_CH_CTRL_SIGSEL_AESDATARD   0x00000002UL
 
#define _DMA_CH_CTRL_SIGSEL_AESDATAWR   0x00000000UL
 
#define _DMA_CH_CTRL_SIGSEL_AESKEYWR   0x00000003UL
 
#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR   0x00000001UL
 
#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   0x00000000UL
 
#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL   0x00000001UL
 
#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   0x00000000UL
 
#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL   0x00000001UL
 
#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   0x00000002UL
 
#define _DMA_CH_CTRL_SIGSEL_MASK   0xFUL
 
#define _DMA_CH_CTRL_SIGSEL_MSCWDATA   0x00000000UL
 
#define _DMA_CH_CTRL_SIGSEL_SHIFT   0
 
#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0   0x00000001UL
 
#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1   0x00000002UL
 
#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2   0x00000003UL
 
#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF   0x00000000UL
 
#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0   0x00000001UL
 
#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1   0x00000002UL
 
#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2   0x00000003UL
 
#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF   0x00000000UL
 
#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV   0x00000000UL
 
#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT   0x00000003UL
 
#define _DMA_CH_CTRL_SIGSEL_USART1TXBL   0x00000001UL
 
#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT   0x00000004UL
 
#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   0x00000002UL
 
#define _DMA_CH_CTRL_SOURCESEL_ADC0   0x00000008UL
 
#define _DMA_CH_CTRL_SOURCESEL_AES   0x00000031UL
 
#define _DMA_CH_CTRL_SOURCESEL_I2C0   0x00000014UL
 
#define _DMA_CH_CTRL_SOURCESEL_LEUART0   0x00000010UL
 
#define _DMA_CH_CTRL_SOURCESEL_MASK   0x3F0000UL
 
#define _DMA_CH_CTRL_SOURCESEL_MSC   0x00000030UL
 
#define _DMA_CH_CTRL_SOURCESEL_NONE   0x00000000UL
 
#define _DMA_CH_CTRL_SOURCESEL_SHIFT   16
 
#define _DMA_CH_CTRL_SOURCESEL_TIMER0   0x00000018UL
 
#define _DMA_CH_CTRL_SOURCESEL_TIMER1   0x00000019UL
 
#define _DMA_CH_CTRL_SOURCESEL_USART1   0x0000000DUL
 
#define _DMA_CHALTC_CH0ALTC_DEFAULT   0x00000000UL
 
#define _DMA_CHALTC_CH0ALTC_MASK   0x1UL
 
#define _DMA_CHALTC_CH0ALTC_SHIFT   0
 
#define _DMA_CHALTC_CH1ALTC_DEFAULT   0x00000000UL
 
#define _DMA_CHALTC_CH1ALTC_MASK   0x2UL
 
#define _DMA_CHALTC_CH1ALTC_SHIFT   1
 
#define _DMA_CHALTC_CH2ALTC_DEFAULT   0x00000000UL
 
#define _DMA_CHALTC_CH2ALTC_MASK   0x4UL
 
#define _DMA_CHALTC_CH2ALTC_SHIFT   2
 
#define _DMA_CHALTC_CH3ALTC_DEFAULT   0x00000000UL
 
#define _DMA_CHALTC_CH3ALTC_MASK   0x8UL
 
#define _DMA_CHALTC_CH3ALTC_SHIFT   3
 
#define _DMA_CHALTC_MASK   0x0000000FUL
 
#define _DMA_CHALTC_RESETVALUE   0x00000000UL
 
#define _DMA_CHALTS_CH0ALTS_DEFAULT   0x00000000UL
 
#define _DMA_CHALTS_CH0ALTS_MASK   0x1UL
 
#define _DMA_CHALTS_CH0ALTS_SHIFT   0
 
#define _DMA_CHALTS_CH1ALTS_DEFAULT   0x00000000UL
 
#define _DMA_CHALTS_CH1ALTS_MASK   0x2UL
 
#define _DMA_CHALTS_CH1ALTS_SHIFT   1
 
#define _DMA_CHALTS_CH2ALTS_DEFAULT   0x00000000UL
 
#define _DMA_CHALTS_CH2ALTS_MASK   0x4UL
 
#define _DMA_CHALTS_CH2ALTS_SHIFT   2
 
#define _DMA_CHALTS_CH3ALTS_DEFAULT   0x00000000UL
 
#define _DMA_CHALTS_CH3ALTS_MASK   0x8UL
 
#define _DMA_CHALTS_CH3ALTS_SHIFT   3
 
#define _DMA_CHALTS_MASK   0x0000000FUL
 
#define _DMA_CHALTS_RESETVALUE   0x00000000UL
 
#define _DMA_CHENC_CH0ENC_DEFAULT   0x00000000UL
 
#define _DMA_CHENC_CH0ENC_MASK   0x1UL
 
#define _DMA_CHENC_CH0ENC_SHIFT   0
 
#define _DMA_CHENC_CH1ENC_DEFAULT   0x00000000UL
 
#define _DMA_CHENC_CH1ENC_MASK   0x2UL
 
#define _DMA_CHENC_CH1ENC_SHIFT   1
 
#define _DMA_CHENC_CH2ENC_DEFAULT   0x00000000UL
 
#define _DMA_CHENC_CH2ENC_MASK   0x4UL
 
#define _DMA_CHENC_CH2ENC_SHIFT   2
 
#define _DMA_CHENC_CH3ENC_DEFAULT   0x00000000UL
 
#define _DMA_CHENC_CH3ENC_MASK   0x8UL
 
#define _DMA_CHENC_CH3ENC_SHIFT   3
 
#define _DMA_CHENC_MASK   0x0000000FUL
 
#define _DMA_CHENC_RESETVALUE   0x00000000UL
 
#define _DMA_CHENS_CH0ENS_DEFAULT   0x00000000UL
 
#define _DMA_CHENS_CH0ENS_MASK   0x1UL
 
#define _DMA_CHENS_CH0ENS_SHIFT   0
 
#define _DMA_CHENS_CH1ENS_DEFAULT   0x00000000UL
 
#define _DMA_CHENS_CH1ENS_MASK   0x2UL
 
#define _DMA_CHENS_CH1ENS_SHIFT   1
 
#define _DMA_CHENS_CH2ENS_DEFAULT   0x00000000UL
 
#define _DMA_CHENS_CH2ENS_MASK   0x4UL
 
#define _DMA_CHENS_CH2ENS_SHIFT   2
 
#define _DMA_CHENS_CH3ENS_DEFAULT   0x00000000UL
 
#define _DMA_CHENS_CH3ENS_MASK   0x8UL
 
#define _DMA_CHENS_CH3ENS_SHIFT   3
 
#define _DMA_CHENS_MASK   0x0000000FUL
 
#define _DMA_CHENS_RESETVALUE   0x00000000UL
 
#define _DMA_CHPRIC_CH0PRIC_DEFAULT   0x00000000UL
 
#define _DMA_CHPRIC_CH0PRIC_MASK   0x1UL
 
#define _DMA_CHPRIC_CH0PRIC_SHIFT   0
 
#define _DMA_CHPRIC_CH1PRIC_DEFAULT   0x00000000UL
 
#define _DMA_CHPRIC_CH1PRIC_MASK   0x2UL
 
#define _DMA_CHPRIC_CH1PRIC_SHIFT   1
 
#define _DMA_CHPRIC_CH2PRIC_DEFAULT   0x00000000UL
 
#define _DMA_CHPRIC_CH2PRIC_MASK   0x4UL
 
#define _DMA_CHPRIC_CH2PRIC_SHIFT   2
 
#define _DMA_CHPRIC_CH3PRIC_DEFAULT   0x00000000UL
 
#define _DMA_CHPRIC_CH3PRIC_MASK   0x8UL
 
#define _DMA_CHPRIC_CH3PRIC_SHIFT   3
 
#define _DMA_CHPRIC_MASK   0x0000000FUL
 
#define _DMA_CHPRIC_RESETVALUE   0x00000000UL
 
#define _DMA_CHPRIS_CH0PRIS_DEFAULT   0x00000000UL
 
#define _DMA_CHPRIS_CH0PRIS_MASK   0x1UL
 
#define _DMA_CHPRIS_CH0PRIS_SHIFT   0
 
#define _DMA_CHPRIS_CH1PRIS_DEFAULT   0x00000000UL
 
#define _DMA_CHPRIS_CH1PRIS_MASK   0x2UL
 
#define _DMA_CHPRIS_CH1PRIS_SHIFT   1
 
#define _DMA_CHPRIS_CH2PRIS_DEFAULT   0x00000000UL
 
#define _DMA_CHPRIS_CH2PRIS_MASK   0x4UL
 
#define _DMA_CHPRIS_CH2PRIS_SHIFT   2
 
#define _DMA_CHPRIS_CH3PRIS_DEFAULT   0x00000000UL
 
#define _DMA_CHPRIS_CH3PRIS_MASK   0x8UL
 
#define _DMA_CHPRIS_CH3PRIS_SHIFT   3
 
#define _DMA_CHPRIS_MASK   0x0000000FUL
 
#define _DMA_CHPRIS_RESETVALUE   0x00000000UL
 
#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   0x00000000UL
 
#define _DMA_CHREQMASKC_CH0REQMASKC_MASK   0x1UL
 
#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT   0
 
#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   0x00000000UL
 
#define _DMA_CHREQMASKC_CH1REQMASKC_MASK   0x2UL
 
#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT   1
 
#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   0x00000000UL
 
#define _DMA_CHREQMASKC_CH2REQMASKC_MASK   0x4UL
 
#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT   2
 
#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   0x00000000UL
 
#define _DMA_CHREQMASKC_CH3REQMASKC_MASK   0x8UL
 
#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT   3
 
#define _DMA_CHREQMASKC_MASK   0x0000000FUL
 
#define _DMA_CHREQMASKC_RESETVALUE   0x00000000UL
 
#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   0x00000000UL
 
#define _DMA_CHREQMASKS_CH0REQMASKS_MASK   0x1UL
 
#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT   0
 
#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   0x00000000UL
 
#define _DMA_CHREQMASKS_CH1REQMASKS_MASK   0x2UL
 
#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT   1
 
#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   0x00000000UL
 
#define _DMA_CHREQMASKS_CH2REQMASKS_MASK   0x4UL
 
#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT   2
 
#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   0x00000000UL
 
#define _DMA_CHREQMASKS_CH3REQMASKS_MASK   0x8UL
 
#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT   3
 
#define _DMA_CHREQMASKS_MASK   0x0000000FUL
 
#define _DMA_CHREQMASKS_RESETVALUE   0x00000000UL
 
#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   0x00000000UL
 
#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK   0x1UL
 
#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT   0
 
#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   0x00000000UL
 
#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK   0x2UL
 
#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT   1
 
#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   0x00000000UL
 
#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK   0x4UL
 
#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT   2
 
#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   0x00000000UL
 
#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK   0x8UL
 
#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT   3
 
#define _DMA_CHREQSTATUS_MASK   0x0000000FUL
 
#define _DMA_CHREQSTATUS_RESETVALUE   0x00000000UL
 
#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   0x00000000UL
 
#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK   0x1UL
 
#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT   0
 
#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   0x00000000UL
 
#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK   0x2UL
 
#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT   1
 
#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   0x00000000UL
 
#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK   0x4UL
 
#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT   2
 
#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   0x00000000UL
 
#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK   0x8UL
 
#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT   3
 
#define _DMA_CHSREQSTATUS_MASK   0x0000000FUL
 
#define _DMA_CHSREQSTATUS_RESETVALUE   0x00000000UL
 
#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT   0x00000000UL
 
#define _DMA_CHSWREQ_CH0SWREQ_MASK   0x1UL
 
#define _DMA_CHSWREQ_CH0SWREQ_SHIFT   0
 
#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT   0x00000000UL
 
#define _DMA_CHSWREQ_CH1SWREQ_MASK   0x2UL
 
#define _DMA_CHSWREQ_CH1SWREQ_SHIFT   1
 
#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT   0x00000000UL
 
#define _DMA_CHSWREQ_CH2SWREQ_MASK   0x4UL
 
#define _DMA_CHSWREQ_CH2SWREQ_SHIFT   2
 
#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT   0x00000000UL
 
#define _DMA_CHSWREQ_CH3SWREQ_MASK   0x8UL
 
#define _DMA_CHSWREQ_CH3SWREQ_SHIFT   3
 
#define _DMA_CHSWREQ_MASK   0x0000000FUL
 
#define _DMA_CHSWREQ_RESETVALUE   0x00000000UL
 
#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   0x00000000UL
 
#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK   0x1UL
 
#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT   0
 
#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   0x00000000UL
 
#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK   0x2UL
 
#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT   1
 
#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   0x00000000UL
 
#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK   0x4UL
 
#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT   2
 
#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   0x00000000UL
 
#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK   0x8UL
 
#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT   3
 
#define _DMA_CHUSEBURSTC_MASK   0x0000000FUL
 
#define _DMA_CHUSEBURSTC_RESETVALUE   0x00000000UL
 
#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   0x00000001UL
 
#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   0x00000000UL
 
#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK   0x1UL
 
#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT   0
 
#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   0x00000000UL
 
#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   0x00000000UL
 
#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK   0x2UL
 
#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT   1
 
#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   0x00000000UL
 
#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK   0x4UL
 
#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT   2
 
#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   0x00000000UL
 
#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK   0x8UL
 
#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT   3
 
#define _DMA_CHUSEBURSTS_MASK   0x0000000FUL
 
#define _DMA_CHUSEBURSTS_RESETVALUE   0x00000000UL
 
#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   0x00000001UL
 
#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK   0x1UL
 
#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT   0
 
#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   0x00000001UL
 
#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK   0x2UL
 
#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT   1
 
#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   0x00000001UL
 
#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK   0x4UL
 
#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT   2
 
#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   0x00000001UL
 
#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK   0x8UL
 
#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT   3
 
#define _DMA_CHWAITSTATUS_MASK   0x0000000FUL
 
#define _DMA_CHWAITSTATUS_RESETVALUE   0x0000000FUL
 
#define _DMA_CONFIG_CHPROT_DEFAULT   0x00000000UL
 
#define _DMA_CONFIG_CHPROT_MASK   0x20UL
 
#define _DMA_CONFIG_CHPROT_SHIFT   5
 
#define _DMA_CONFIG_EN_DEFAULT   0x00000000UL
 
#define _DMA_CONFIG_EN_MASK   0x1UL
 
#define _DMA_CONFIG_EN_SHIFT   0
 
#define _DMA_CONFIG_MASK   0x00000021UL
 
#define _DMA_CONFIG_RESETVALUE   0x00000000UL
 
#define _DMA_CTRLBASE_CTRLBASE_DEFAULT   0x00000000UL
 
#define _DMA_CTRLBASE_CTRLBASE_MASK   0xFFFFFFFFUL
 
#define _DMA_CTRLBASE_CTRLBASE_SHIFT   0
 
#define _DMA_CTRLBASE_MASK   0xFFFFFFFFUL
 
#define _DMA_CTRLBASE_RESETVALUE   0x00000000UL
 
#define _DMA_ERRORC_ERRORC_DEFAULT   0x00000000UL
 
#define _DMA_ERRORC_ERRORC_MASK   0x1UL
 
#define _DMA_ERRORC_ERRORC_SHIFT   0
 
#define _DMA_ERRORC_MASK   0x00000001UL
 
#define _DMA_ERRORC_RESETVALUE   0x00000000UL
 
#define _DMA_IEN_CH0DONE_DEFAULT   0x00000000UL
 
#define _DMA_IEN_CH0DONE_MASK   0x1UL
 
#define _DMA_IEN_CH0DONE_SHIFT   0
 
#define _DMA_IEN_CH1DONE_DEFAULT   0x00000000UL
 
#define _DMA_IEN_CH1DONE_MASK   0x2UL
 
#define _DMA_IEN_CH1DONE_SHIFT   1
 
#define _DMA_IEN_CH2DONE_DEFAULT   0x00000000UL
 
#define _DMA_IEN_CH2DONE_MASK   0x4UL
 
#define _DMA_IEN_CH2DONE_SHIFT   2
 
#define _DMA_IEN_CH3DONE_DEFAULT   0x00000000UL
 
#define _DMA_IEN_CH3DONE_MASK   0x8UL
 
#define _DMA_IEN_CH3DONE_SHIFT   3
 
#define _DMA_IEN_ERR_DEFAULT   0x00000000UL
 
#define _DMA_IEN_ERR_MASK   0x80000000UL
 
#define _DMA_IEN_ERR_SHIFT   31
 
#define _DMA_IEN_MASK   0x8000000FUL
 
#define _DMA_IEN_RESETVALUE   0x00000000UL
 
#define _DMA_IF_CH0DONE_DEFAULT   0x00000000UL
 
#define _DMA_IF_CH0DONE_MASK   0x1UL
 
#define _DMA_IF_CH0DONE_SHIFT   0
 
#define _DMA_IF_CH1DONE_DEFAULT   0x00000000UL
 
#define _DMA_IF_CH1DONE_MASK   0x2UL
 
#define _DMA_IF_CH1DONE_SHIFT   1
 
#define _DMA_IF_CH2DONE_DEFAULT   0x00000000UL
 
#define _DMA_IF_CH2DONE_MASK   0x4UL
 
#define _DMA_IF_CH2DONE_SHIFT   2
 
#define _DMA_IF_CH3DONE_DEFAULT   0x00000000UL
 
#define _DMA_IF_CH3DONE_MASK   0x8UL
 
#define _DMA_IF_CH3DONE_SHIFT   3
 
#define _DMA_IF_ERR_DEFAULT   0x00000000UL
 
#define _DMA_IF_ERR_MASK   0x80000000UL
 
#define _DMA_IF_ERR_SHIFT   31
 
#define _DMA_IF_MASK   0x8000000FUL
 
#define _DMA_IF_RESETVALUE   0x00000000UL
 
#define _DMA_IFC_CH0DONE_DEFAULT   0x00000000UL
 
#define _DMA_IFC_CH0DONE_MASK   0x1UL
 
#define _DMA_IFC_CH0DONE_SHIFT   0
 
#define _DMA_IFC_CH1DONE_DEFAULT   0x00000000UL
 
#define _DMA_IFC_CH1DONE_MASK   0x2UL
 
#define _DMA_IFC_CH1DONE_SHIFT   1
 
#define _DMA_IFC_CH2DONE_DEFAULT   0x00000000UL
 
#define _DMA_IFC_CH2DONE_MASK   0x4UL
 
#define _DMA_IFC_CH2DONE_SHIFT   2
 
#define _DMA_IFC_CH3DONE_DEFAULT   0x00000000UL
 
#define _DMA_IFC_CH3DONE_MASK   0x8UL
 
#define _DMA_IFC_CH3DONE_SHIFT   3
 
#define _DMA_IFC_ERR_DEFAULT   0x00000000UL
 
#define _DMA_IFC_ERR_MASK   0x80000000UL
 
#define _DMA_IFC_ERR_SHIFT   31
 
#define _DMA_IFC_MASK   0x8000000FUL
 
#define _DMA_IFC_RESETVALUE   0x00000000UL
 
#define _DMA_IFS_CH0DONE_DEFAULT   0x00000000UL
 
#define _DMA_IFS_CH0DONE_MASK   0x1UL
 
#define _DMA_IFS_CH0DONE_SHIFT   0
 
#define _DMA_IFS_CH1DONE_DEFAULT   0x00000000UL
 
#define _DMA_IFS_CH1DONE_MASK   0x2UL
 
#define _DMA_IFS_CH1DONE_SHIFT   1
 
#define _DMA_IFS_CH2DONE_DEFAULT   0x00000000UL
 
#define _DMA_IFS_CH2DONE_MASK   0x4UL
 
#define _DMA_IFS_CH2DONE_SHIFT   2
 
#define _DMA_IFS_CH3DONE_DEFAULT   0x00000000UL
 
#define _DMA_IFS_CH3DONE_MASK   0x8UL
 
#define _DMA_IFS_CH3DONE_SHIFT   3
 
#define _DMA_IFS_ERR_DEFAULT   0x00000000UL
 
#define _DMA_IFS_ERR_MASK   0x80000000UL
 
#define _DMA_IFS_ERR_SHIFT   31
 
#define _DMA_IFS_MASK   0x8000000FUL
 
#define _DMA_IFS_RESETVALUE   0x00000000UL
 
#define _DMA_STATUS_CHNUM_DEFAULT   0x00000003UL
 
#define _DMA_STATUS_CHNUM_MASK   0x1F0000UL
 
#define _DMA_STATUS_CHNUM_SHIFT   16
 
#define _DMA_STATUS_EN_DEFAULT   0x00000000UL
 
#define _DMA_STATUS_EN_MASK   0x1UL
 
#define _DMA_STATUS_EN_SHIFT   0
 
#define _DMA_STATUS_MASK   0x001F00F1UL
 
#define _DMA_STATUS_RESETVALUE   0x10030000UL
 
#define _DMA_STATUS_STATE_DEFAULT   0x00000000UL
 
#define _DMA_STATUS_STATE_DONE   0x00000009UL
 
#define _DMA_STATUS_STATE_IDLE   0x00000000UL
 
#define _DMA_STATUS_STATE_MASK   0xF0UL
 
#define _DMA_STATUS_STATE_PERSCATTRANS   0x0000000AUL
 
#define _DMA_STATUS_STATE_RDCHCTRLDATA   0x00000001UL
 
#define _DMA_STATUS_STATE_RDDSTENDPTR   0x00000003UL
 
#define _DMA_STATUS_STATE_RDSRCDATA   0x00000004UL
 
#define _DMA_STATUS_STATE_RDSRCENDPTR   0x00000002UL
 
#define _DMA_STATUS_STATE_SHIFT   4
 
#define _DMA_STATUS_STATE_STALLED   0x00000008UL
 
#define _DMA_STATUS_STATE_WAITREQCLR   0x00000006UL
 
#define _DMA_STATUS_STATE_WRCHCTRLDATA   0x00000007UL
 
#define _DMA_STATUS_STATE_WRDSTDATA   0x00000005UL
 
#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
 
#define DMA_CH_CTRL_SIGSEL_ADC0SCAN   (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)
 
#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
 
#define DMA_CH_CTRL_SIGSEL_AESDATARD   (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)
 
#define DMA_CH_CTRL_SIGSEL_AESDATAWR   (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)
 
#define DMA_CH_CTRL_SIGSEL_AESKEYWR   (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)
 
#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR   (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)
 
#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
 
#define DMA_CH_CTRL_SIGSEL_I2C0TXBL   (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
 
#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
 
#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
 
#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
 
#define DMA_CH_CTRL_SIGSEL_MSCWDATA   (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
 
#define DMA_CH_CTRL_SIGSEL_TIMER0CC0   (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
 
#define DMA_CH_CTRL_SIGSEL_TIMER0CC1   (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
 
#define DMA_CH_CTRL_SIGSEL_TIMER0CC2   (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
 
#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
 
#define DMA_CH_CTRL_SIGSEL_TIMER1CC0   (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
 
#define DMA_CH_CTRL_SIGSEL_TIMER1CC1   (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
 
#define DMA_CH_CTRL_SIGSEL_TIMER1CC2   (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
 
#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
 
#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
 
#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0)
 
#define DMA_CH_CTRL_SIGSEL_USART1TXBL   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
 
#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT   (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)
 
#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
 
#define DMA_CH_CTRL_SOURCESEL_ADC0   (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)
 
#define DMA_CH_CTRL_SOURCESEL_AES   (_DMA_CH_CTRL_SOURCESEL_AES << 16)
 
#define DMA_CH_CTRL_SOURCESEL_I2C0   (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
 
#define DMA_CH_CTRL_SOURCESEL_LEUART0   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
 
#define DMA_CH_CTRL_SOURCESEL_MSC   (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
 
#define DMA_CH_CTRL_SOURCESEL_NONE   (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
 
#define DMA_CH_CTRL_SOURCESEL_TIMER0   (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
 
#define DMA_CH_CTRL_SOURCESEL_TIMER1   (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
 
#define DMA_CH_CTRL_SOURCESEL_USART1   (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
 
#define DMA_CHALTC_CH0ALTC   (0x1UL << 0)
 
#define DMA_CHALTC_CH0ALTC_DEFAULT   (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
 
#define DMA_CHALTC_CH1ALTC   (0x1UL << 1)
 
#define DMA_CHALTC_CH1ALTC_DEFAULT   (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
 
#define DMA_CHALTC_CH2ALTC   (0x1UL << 2)
 
#define DMA_CHALTC_CH2ALTC_DEFAULT   (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
 
#define DMA_CHALTC_CH3ALTC   (0x1UL << 3)
 
#define DMA_CHALTC_CH3ALTC_DEFAULT   (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
 
#define DMA_CHALTS_CH0ALTS   (0x1UL << 0)
 
#define DMA_CHALTS_CH0ALTS_DEFAULT   (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
 
#define DMA_CHALTS_CH1ALTS   (0x1UL << 1)
 
#define DMA_CHALTS_CH1ALTS_DEFAULT   (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
 
#define DMA_CHALTS_CH2ALTS   (0x1UL << 2)
 
#define DMA_CHALTS_CH2ALTS_DEFAULT   (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
 
#define DMA_CHALTS_CH3ALTS   (0x1UL << 3)
 
#define DMA_CHALTS_CH3ALTS_DEFAULT   (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
 
#define DMA_CHENC_CH0ENC   (0x1UL << 0)
 
#define DMA_CHENC_CH0ENC_DEFAULT   (_DMA_CHENC_CH0ENC_DEFAULT << 0)
 
#define DMA_CHENC_CH1ENC   (0x1UL << 1)
 
#define DMA_CHENC_CH1ENC_DEFAULT   (_DMA_CHENC_CH1ENC_DEFAULT << 1)
 
#define DMA_CHENC_CH2ENC   (0x1UL << 2)
 
#define DMA_CHENC_CH2ENC_DEFAULT   (_DMA_CHENC_CH2ENC_DEFAULT << 2)
 
#define DMA_CHENC_CH3ENC   (0x1UL << 3)
 
#define DMA_CHENC_CH3ENC_DEFAULT   (_DMA_CHENC_CH3ENC_DEFAULT << 3)
 
#define DMA_CHENS_CH0ENS   (0x1UL << 0)
 
#define DMA_CHENS_CH0ENS_DEFAULT   (_DMA_CHENS_CH0ENS_DEFAULT << 0)
 
#define DMA_CHENS_CH1ENS   (0x1UL << 1)
 
#define DMA_CHENS_CH1ENS_DEFAULT   (_DMA_CHENS_CH1ENS_DEFAULT << 1)
 
#define DMA_CHENS_CH2ENS   (0x1UL << 2)
 
#define DMA_CHENS_CH2ENS_DEFAULT   (_DMA_CHENS_CH2ENS_DEFAULT << 2)
 
#define DMA_CHENS_CH3ENS   (0x1UL << 3)
 
#define DMA_CHENS_CH3ENS_DEFAULT   (_DMA_CHENS_CH3ENS_DEFAULT << 3)
 
#define DMA_CHPRIC_CH0PRIC   (0x1UL << 0)
 
#define DMA_CHPRIC_CH0PRIC_DEFAULT   (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
 
#define DMA_CHPRIC_CH1PRIC   (0x1UL << 1)
 
#define DMA_CHPRIC_CH1PRIC_DEFAULT   (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
 
#define DMA_CHPRIC_CH2PRIC   (0x1UL << 2)
 
#define DMA_CHPRIC_CH2PRIC_DEFAULT   (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
 
#define DMA_CHPRIC_CH3PRIC   (0x1UL << 3)
 
#define DMA_CHPRIC_CH3PRIC_DEFAULT   (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
 
#define DMA_CHPRIS_CH0PRIS   (0x1UL << 0)
 
#define DMA_CHPRIS_CH0PRIS_DEFAULT   (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
 
#define DMA_CHPRIS_CH1PRIS   (0x1UL << 1)
 
#define DMA_CHPRIS_CH1PRIS_DEFAULT   (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
 
#define DMA_CHPRIS_CH2PRIS   (0x1UL << 2)
 
#define DMA_CHPRIS_CH2PRIS_DEFAULT   (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
 
#define DMA_CHPRIS_CH3PRIS   (0x1UL << 3)
 
#define DMA_CHPRIS_CH3PRIS_DEFAULT   (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
 
#define DMA_CHREQMASKC_CH0REQMASKC   (0x1UL << 0)
 
#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
 
#define DMA_CHREQMASKC_CH1REQMASKC   (0x1UL << 1)
 
#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
 
#define DMA_CHREQMASKC_CH2REQMASKC   (0x1UL << 2)
 
#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
 
#define DMA_CHREQMASKC_CH3REQMASKC   (0x1UL << 3)
 
#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
 
#define DMA_CHREQMASKS_CH0REQMASKS   (0x1UL << 0)
 
#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
 
#define DMA_CHREQMASKS_CH1REQMASKS   (0x1UL << 1)
 
#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
 
#define DMA_CHREQMASKS_CH2REQMASKS   (0x1UL << 2)
 
#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
 
#define DMA_CHREQMASKS_CH3REQMASKS   (0x1UL << 3)
 
#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
 
#define DMA_CHREQSTATUS_CH0REQSTATUS   (0x1UL << 0)
 
#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
 
#define DMA_CHREQSTATUS_CH1REQSTATUS   (0x1UL << 1)
 
#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
 
#define DMA_CHREQSTATUS_CH2REQSTATUS   (0x1UL << 2)
 
#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
 
#define DMA_CHREQSTATUS_CH3REQSTATUS   (0x1UL << 3)
 
#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
 
#define DMA_CHSREQSTATUS_CH0SREQSTATUS   (0x1UL << 0)
 
#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
 
#define DMA_CHSREQSTATUS_CH1SREQSTATUS   (0x1UL << 1)
 
#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
 
#define DMA_CHSREQSTATUS_CH2SREQSTATUS   (0x1UL << 2)
 
#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
 
#define DMA_CHSREQSTATUS_CH3SREQSTATUS   (0x1UL << 3)
 
#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
 
#define DMA_CHSWREQ_CH0SWREQ   (0x1UL << 0)
 
#define DMA_CHSWREQ_CH0SWREQ_DEFAULT   (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
 
#define DMA_CHSWREQ_CH1SWREQ   (0x1UL << 1)
 
#define DMA_CHSWREQ_CH1SWREQ_DEFAULT   (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
 
#define DMA_CHSWREQ_CH2SWREQ   (0x1UL << 2)
 
#define DMA_CHSWREQ_CH2SWREQ_DEFAULT   (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
 
#define DMA_CHSWREQ_CH3SWREQ   (0x1UL << 3)
 
#define DMA_CHSWREQ_CH3SWREQ_DEFAULT   (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
 
#define DMA_CHUSEBURSTC_CH0USEBURSTC   (0x1UL << 0)
 
#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
 
#define DMA_CHUSEBURSTC_CH1USEBURSTC   (0x1UL << 1)
 
#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
 
#define DMA_CHUSEBURSTC_CH2USEBURSTC   (0x1UL << 2)
 
#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
 
#define DMA_CHUSEBURSTC_CH3USEBURSTC   (0x1UL << 3)
 
#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
 
#define DMA_CHUSEBURSTS_CH0USEBURSTS   (0x1UL << 0)
 
#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
 
#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
 
#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
 
#define DMA_CHUSEBURSTS_CH1USEBURSTS   (0x1UL << 1)
 
#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
 
#define DMA_CHUSEBURSTS_CH2USEBURSTS   (0x1UL << 2)
 
#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
 
#define DMA_CHUSEBURSTS_CH3USEBURSTS   (0x1UL << 3)
 
#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
 
#define DMA_CHWAITSTATUS_CH0WAITSTATUS   (0x1UL << 0)
 
#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
 
#define DMA_CHWAITSTATUS_CH1WAITSTATUS   (0x1UL << 1)
 
#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
 
#define DMA_CHWAITSTATUS_CH2WAITSTATUS   (0x1UL << 2)
 
#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
 
#define DMA_CHWAITSTATUS_CH3WAITSTATUS   (0x1UL << 3)
 
#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
 
#define DMA_CONFIG_CHPROT   (0x1UL << 5)
 
#define DMA_CONFIG_CHPROT_DEFAULT   (_DMA_CONFIG_CHPROT_DEFAULT << 5)
 
#define DMA_CONFIG_EN   (0x1UL << 0)
 
#define DMA_CONFIG_EN_DEFAULT   (_DMA_CONFIG_EN_DEFAULT << 0)
 
#define DMA_CTRLBASE_CTRLBASE_DEFAULT   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
 
#define DMA_ERRORC_ERRORC   (0x1UL << 0)
 
#define DMA_ERRORC_ERRORC_DEFAULT   (_DMA_ERRORC_ERRORC_DEFAULT << 0)
 
#define DMA_IEN_CH0DONE   (0x1UL << 0)
 
#define DMA_IEN_CH0DONE_DEFAULT   (_DMA_IEN_CH0DONE_DEFAULT << 0)
 
#define DMA_IEN_CH1DONE   (0x1UL << 1)
 
#define DMA_IEN_CH1DONE_DEFAULT   (_DMA_IEN_CH1DONE_DEFAULT << 1)
 
#define DMA_IEN_CH2DONE   (0x1UL << 2)
 
#define DMA_IEN_CH2DONE_DEFAULT   (_DMA_IEN_CH2DONE_DEFAULT << 2)
 
#define DMA_IEN_CH3DONE   (0x1UL << 3)
 
#define DMA_IEN_CH3DONE_DEFAULT   (_DMA_IEN_CH3DONE_DEFAULT << 3)
 
#define DMA_IEN_ERR   (0x1UL << 31)
 
#define DMA_IEN_ERR_DEFAULT   (_DMA_IEN_ERR_DEFAULT << 31)
 
#define DMA_IF_CH0DONE   (0x1UL << 0)
 
#define DMA_IF_CH0DONE_DEFAULT   (_DMA_IF_CH0DONE_DEFAULT << 0)
 
#define DMA_IF_CH1DONE   (0x1UL << 1)
 
#define DMA_IF_CH1DONE_DEFAULT   (_DMA_IF_CH1DONE_DEFAULT << 1)
 
#define DMA_IF_CH2DONE   (0x1UL << 2)
 
#define DMA_IF_CH2DONE_DEFAULT   (_DMA_IF_CH2DONE_DEFAULT << 2)
 
#define DMA_IF_CH3DONE   (0x1UL << 3)
 
#define DMA_IF_CH3DONE_DEFAULT   (_DMA_IF_CH3DONE_DEFAULT << 3)
 
#define DMA_IF_ERR   (0x1UL << 31)
 
#define DMA_IF_ERR_DEFAULT   (_DMA_IF_ERR_DEFAULT << 31)
 
#define DMA_IFC_CH0DONE   (0x1UL << 0)
 
#define DMA_IFC_CH0DONE_DEFAULT   (_DMA_IFC_CH0DONE_DEFAULT << 0)
 
#define DMA_IFC_CH1DONE   (0x1UL << 1)
 
#define DMA_IFC_CH1DONE_DEFAULT   (_DMA_IFC_CH1DONE_DEFAULT << 1)
 
#define DMA_IFC_CH2DONE   (0x1UL << 2)
 
#define DMA_IFC_CH2DONE_DEFAULT   (_DMA_IFC_CH2DONE_DEFAULT << 2)
 
#define DMA_IFC_CH3DONE   (0x1UL << 3)
 
#define DMA_IFC_CH3DONE_DEFAULT   (_DMA_IFC_CH3DONE_DEFAULT << 3)
 
#define DMA_IFC_ERR   (0x1UL << 31)
 
#define DMA_IFC_ERR_DEFAULT   (_DMA_IFC_ERR_DEFAULT << 31)
 
#define DMA_IFS_CH0DONE   (0x1UL << 0)
 
#define DMA_IFS_CH0DONE_DEFAULT   (_DMA_IFS_CH0DONE_DEFAULT << 0)
 
#define DMA_IFS_CH1DONE   (0x1UL << 1)
 
#define DMA_IFS_CH1DONE_DEFAULT   (_DMA_IFS_CH1DONE_DEFAULT << 1)
 
#define DMA_IFS_CH2DONE   (0x1UL << 2)
 
#define DMA_IFS_CH2DONE_DEFAULT   (_DMA_IFS_CH2DONE_DEFAULT << 2)
 
#define DMA_IFS_CH3DONE   (0x1UL << 3)
 
#define DMA_IFS_CH3DONE_DEFAULT   (_DMA_IFS_CH3DONE_DEFAULT << 3)
 
#define DMA_IFS_ERR   (0x1UL << 31)
 
#define DMA_IFS_ERR_DEFAULT   (_DMA_IFS_ERR_DEFAULT << 31)
 
#define DMA_STATUS_CHNUM_DEFAULT   (_DMA_STATUS_CHNUM_DEFAULT << 16)
 
#define DMA_STATUS_EN   (0x1UL << 0)
 
#define DMA_STATUS_EN_DEFAULT   (_DMA_STATUS_EN_DEFAULT << 0)
 
#define DMA_STATUS_STATE_DEFAULT   (_DMA_STATUS_STATE_DEFAULT << 4)
 
#define DMA_STATUS_STATE_DONE   (_DMA_STATUS_STATE_DONE << 4)
 
#define DMA_STATUS_STATE_IDLE   (_DMA_STATUS_STATE_IDLE << 4)
 
#define DMA_STATUS_STATE_PERSCATTRANS   (_DMA_STATUS_STATE_PERSCATTRANS << 4)
 
#define DMA_STATUS_STATE_RDCHCTRLDATA   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
 
#define DMA_STATUS_STATE_RDDSTENDPTR   (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
 
#define DMA_STATUS_STATE_RDSRCDATA   (_DMA_STATUS_STATE_RDSRCDATA << 4)
 
#define DMA_STATUS_STATE_RDSRCENDPTR   (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
 
#define DMA_STATUS_STATE_STALLED   (_DMA_STATUS_STATE_STALLED << 4)
 
#define DMA_STATUS_STATE_WAITREQCLR   (_DMA_STATUS_STATE_WAITREQCLR << 4)
 
#define DMA_STATUS_STATE_WRCHCTRLDATA   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
 
#define DMA_STATUS_STATE_WRDSTDATA   (_DMA_STATUS_STATE_WRDSTDATA << 4)
 

Macro Definition Documentation

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   0x00000040UL

Mode DEFAULT for DMA_ALTCTRLBASE

Definition at line 148 of file efm32zg_dma.h.

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK   0xFFFFFFFFUL

Bit mask for DMA_ALTCTRLBASE

Definition at line 147 of file efm32zg_dma.h.

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT   0

Shift value for DMA_ALTCTRLBASE

Definition at line 146 of file efm32zg_dma.h.

#define _DMA_ALTCTRLBASE_MASK   0xFFFFFFFFUL

Mask for DMA_ALTCTRLBASE

Definition at line 145 of file efm32zg_dma.h.

#define _DMA_ALTCTRLBASE_RESETVALUE   0x00000040UL

Default value for DMA_ALTCTRLBASE

Definition at line 144 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_MASK   0x003F000FUL

Mask for DMA_CH_CTRL

Definition at line 618 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_RESETVALUE   0x00000000UL

Default value for DMA_CH_CTRL

Definition at line 617 of file efm32zg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN   0x00000001UL

Mode ADC0SCAN for DMA_CH_CTRL

Definition at line 629 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE   0x00000000UL

Mode ADC0SINGLE for DMA_CH_CTRL

Definition at line 621 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESDATARD   0x00000002UL

Mode AESDATARD for DMA_CH_CTRL

Definition at line 640 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESDATAWR   0x00000000UL

Mode AESDATAWR for DMA_CH_CTRL

Definition at line 628 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESKEYWR   0x00000003UL

Mode AESKEYWR for DMA_CH_CTRL

Definition at line 644 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR   0x00000001UL

Mode AESXORDATAWR for DMA_CH_CTRL

Definition at line 635 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   0x00000000UL

Mode I2C0RXDATAV for DMA_CH_CTRL

Definition at line 624 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL   0x00000001UL

Mode I2C0TXBL for DMA_CH_CTRL

Definition at line 632 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   0x00000000UL

Mode LEUART0RXDATAV for DMA_CH_CTRL

Definition at line 623 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL   0x00000001UL

Mode LEUART0TXBL for DMA_CH_CTRL

Definition at line 631 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   0x00000002UL

Mode LEUART0TXEMPTY for DMA_CH_CTRL

Definition at line 637 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_MASK   0xFUL

Bit mask for DMA_SIGSEL

Definition at line 620 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_MSCWDATA   0x00000000UL

Mode MSCWDATA for DMA_CH_CTRL

Definition at line 627 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_SHIFT   0

Shift value for DMA_SIGSEL

Definition at line 619 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0   0x00000001UL

Mode TIMER0CC0 for DMA_CH_CTRL

Definition at line 633 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1   0x00000002UL

Mode TIMER0CC1 for DMA_CH_CTRL

Definition at line 638 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2   0x00000003UL

Mode TIMER0CC2 for DMA_CH_CTRL

Definition at line 642 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF   0x00000000UL

Mode TIMER0UFOF for DMA_CH_CTRL

Definition at line 625 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0   0x00000001UL

Mode TIMER1CC0 for DMA_CH_CTRL

Definition at line 634 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1   0x00000002UL

Mode TIMER1CC1 for DMA_CH_CTRL

Definition at line 639 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2   0x00000003UL

Mode TIMER1CC2 for DMA_CH_CTRL

Definition at line 643 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF   0x00000000UL

Mode TIMER1UFOF for DMA_CH_CTRL

Definition at line 626 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV   0x00000000UL

Mode USART1RXDATAV for DMA_CH_CTRL

Definition at line 622 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT   0x00000003UL

Mode USART1RXDATAVRIGHT for DMA_CH_CTRL

Definition at line 641 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1TXBL   0x00000001UL

Mode USART1TXBL for DMA_CH_CTRL

Definition at line 630 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT   0x00000004UL

Mode USART1TXBLRIGHT for DMA_CH_CTRL

Definition at line 645 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   0x00000002UL

Mode USART1TXEMPTY for DMA_CH_CTRL

Definition at line 636 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_ADC0   0x00000008UL

Mode ADC0 for DMA_CH_CTRL

Definition at line 674 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_AES   0x00000031UL

Mode AES for DMA_CH_CTRL

Definition at line 681 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_I2C0   0x00000014UL

Mode I2C0 for DMA_CH_CTRL

Definition at line 677 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_LEUART0   0x00000010UL

Mode LEUART0 for DMA_CH_CTRL

Definition at line 676 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_MASK   0x3F0000UL

Bit mask for DMA_SOURCESEL

Definition at line 672 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_MSC   0x00000030UL

Mode MSC for DMA_CH_CTRL

Definition at line 680 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_NONE   0x00000000UL

Mode NONE for DMA_CH_CTRL

Definition at line 673 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_SHIFT   16

Shift value for DMA_SOURCESEL

Definition at line 671 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER0   0x00000018UL

Mode TIMER0 for DMA_CH_CTRL

Definition at line 678 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER1   0x00000019UL

Mode TIMER1 for DMA_CH_CTRL

Definition at line 679 of file efm32zg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_USART1   0x0000000DUL

Mode USART1 for DMA_CH_CTRL

Definition at line 675 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH0ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 377 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH0ALTC_MASK   0x1UL

Bit mask for DMA_CH0ALTC

Definition at line 376 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH0ALTC_SHIFT   0

Shift value for DMA_CH0ALTC

Definition at line 375 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH1ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 382 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH1ALTC_MASK   0x2UL

Bit mask for DMA_CH1ALTC

Definition at line 381 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH1ALTC_SHIFT   1

Shift value for DMA_CH1ALTC

Definition at line 380 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH2ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 387 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH2ALTC_MASK   0x4UL

Bit mask for DMA_CH2ALTC

Definition at line 386 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH2ALTC_SHIFT   2

Shift value for DMA_CH2ALTC

Definition at line 385 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH3ALTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 392 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH3ALTC_MASK   0x8UL

Bit mask for DMA_CH3ALTC

Definition at line 391 of file efm32zg_dma.h.

#define _DMA_CHALTC_CH3ALTC_SHIFT   3

Shift value for DMA_CH3ALTC

Definition at line 390 of file efm32zg_dma.h.

#define _DMA_CHALTC_MASK   0x0000000FUL

Mask for DMA_CHALTC

Definition at line 373 of file efm32zg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHALTC_RESETVALUE   0x00000000UL

Default value for DMA_CHALTC

Definition at line 372 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH0ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 353 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH0ALTS_MASK   0x1UL

Bit mask for DMA_CH0ALTS

Definition at line 352 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH0ALTS_SHIFT   0

Shift value for DMA_CH0ALTS

Definition at line 351 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH1ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 358 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH1ALTS_MASK   0x2UL

Bit mask for DMA_CH1ALTS

Definition at line 357 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH1ALTS_SHIFT   1

Shift value for DMA_CH1ALTS

Definition at line 356 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH2ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 363 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH2ALTS_MASK   0x4UL

Bit mask for DMA_CH2ALTS

Definition at line 362 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH2ALTS_SHIFT   2

Shift value for DMA_CH2ALTS

Definition at line 361 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH3ALTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 368 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH3ALTS_MASK   0x8UL

Bit mask for DMA_CH3ALTS

Definition at line 367 of file efm32zg_dma.h.

#define _DMA_CHALTS_CH3ALTS_SHIFT   3

Shift value for DMA_CH3ALTS

Definition at line 366 of file efm32zg_dma.h.

#define _DMA_CHALTS_MASK   0x0000000FUL

Mask for DMA_CHALTS

Definition at line 349 of file efm32zg_dma.h.

#define _DMA_CHALTS_RESETVALUE   0x00000000UL

Default value for DMA_CHALTS

Definition at line 348 of file efm32zg_dma.h.

#define _DMA_CHENC_CH0ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 329 of file efm32zg_dma.h.

#define _DMA_CHENC_CH0ENC_MASK   0x1UL

Bit mask for DMA_CH0ENC

Definition at line 328 of file efm32zg_dma.h.

#define _DMA_CHENC_CH0ENC_SHIFT   0

Shift value for DMA_CH0ENC

Definition at line 327 of file efm32zg_dma.h.

#define _DMA_CHENC_CH1ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 334 of file efm32zg_dma.h.

#define _DMA_CHENC_CH1ENC_MASK   0x2UL

Bit mask for DMA_CH1ENC

Definition at line 333 of file efm32zg_dma.h.

#define _DMA_CHENC_CH1ENC_SHIFT   1

Shift value for DMA_CH1ENC

Definition at line 332 of file efm32zg_dma.h.

#define _DMA_CHENC_CH2ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 339 of file efm32zg_dma.h.

#define _DMA_CHENC_CH2ENC_MASK   0x4UL

Bit mask for DMA_CH2ENC

Definition at line 338 of file efm32zg_dma.h.

#define _DMA_CHENC_CH2ENC_SHIFT   2

Shift value for DMA_CH2ENC

Definition at line 337 of file efm32zg_dma.h.

#define _DMA_CHENC_CH3ENC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 344 of file efm32zg_dma.h.

#define _DMA_CHENC_CH3ENC_MASK   0x8UL

Bit mask for DMA_CH3ENC

Definition at line 343 of file efm32zg_dma.h.

#define _DMA_CHENC_CH3ENC_SHIFT   3

Shift value for DMA_CH3ENC

Definition at line 342 of file efm32zg_dma.h.

#define _DMA_CHENC_MASK   0x0000000FUL

Mask for DMA_CHENC

Definition at line 325 of file efm32zg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHENC_RESETVALUE   0x00000000UL

Default value for DMA_CHENC

Definition at line 324 of file efm32zg_dma.h.

#define _DMA_CHENS_CH0ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 305 of file efm32zg_dma.h.

#define _DMA_CHENS_CH0ENS_MASK   0x1UL

Bit mask for DMA_CH0ENS

Definition at line 304 of file efm32zg_dma.h.

#define _DMA_CHENS_CH0ENS_SHIFT   0

Shift value for DMA_CH0ENS

Definition at line 303 of file efm32zg_dma.h.

#define _DMA_CHENS_CH1ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 310 of file efm32zg_dma.h.

#define _DMA_CHENS_CH1ENS_MASK   0x2UL

Bit mask for DMA_CH1ENS

Definition at line 309 of file efm32zg_dma.h.

#define _DMA_CHENS_CH1ENS_SHIFT   1

Shift value for DMA_CH1ENS

Definition at line 308 of file efm32zg_dma.h.

#define _DMA_CHENS_CH2ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 315 of file efm32zg_dma.h.

#define _DMA_CHENS_CH2ENS_MASK   0x4UL

Bit mask for DMA_CH2ENS

Definition at line 314 of file efm32zg_dma.h.

#define _DMA_CHENS_CH2ENS_SHIFT   2

Shift value for DMA_CH2ENS

Definition at line 313 of file efm32zg_dma.h.

#define _DMA_CHENS_CH3ENS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 320 of file efm32zg_dma.h.

#define _DMA_CHENS_CH3ENS_MASK   0x8UL

Bit mask for DMA_CH3ENS

Definition at line 319 of file efm32zg_dma.h.

#define _DMA_CHENS_CH3ENS_SHIFT   3

Shift value for DMA_CH3ENS

Definition at line 318 of file efm32zg_dma.h.

#define _DMA_CHENS_MASK   0x0000000FUL

Mask for DMA_CHENS

Definition at line 301 of file efm32zg_dma.h.

#define _DMA_CHENS_RESETVALUE   0x00000000UL

Default value for DMA_CHENS

Definition at line 300 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH0PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 425 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH0PRIC_MASK   0x1UL

Bit mask for DMA_CH0PRIC

Definition at line 424 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH0PRIC_SHIFT   0

Shift value for DMA_CH0PRIC

Definition at line 423 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH1PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 430 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH1PRIC_MASK   0x2UL

Bit mask for DMA_CH1PRIC

Definition at line 429 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH1PRIC_SHIFT   1

Shift value for DMA_CH1PRIC

Definition at line 428 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH2PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 435 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH2PRIC_MASK   0x4UL

Bit mask for DMA_CH2PRIC

Definition at line 434 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH2PRIC_SHIFT   2

Shift value for DMA_CH2PRIC

Definition at line 433 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH3PRIC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 440 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH3PRIC_MASK   0x8UL

Bit mask for DMA_CH3PRIC

Definition at line 439 of file efm32zg_dma.h.

#define _DMA_CHPRIC_CH3PRIC_SHIFT   3

Shift value for DMA_CH3PRIC

Definition at line 438 of file efm32zg_dma.h.

#define _DMA_CHPRIC_MASK   0x0000000FUL

Mask for DMA_CHPRIC

Definition at line 421 of file efm32zg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHPRIC_RESETVALUE   0x00000000UL

Default value for DMA_CHPRIC

Definition at line 420 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH0PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 401 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH0PRIS_MASK   0x1UL

Bit mask for DMA_CH0PRIS

Definition at line 400 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH0PRIS_SHIFT   0

Shift value for DMA_CH0PRIS

Definition at line 399 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH1PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 406 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH1PRIS_MASK   0x2UL

Bit mask for DMA_CH1PRIS

Definition at line 405 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH1PRIS_SHIFT   1

Shift value for DMA_CH1PRIS

Definition at line 404 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH2PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 411 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH2PRIS_MASK   0x4UL

Bit mask for DMA_CH2PRIS

Definition at line 410 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH2PRIS_SHIFT   2

Shift value for DMA_CH2PRIS

Definition at line 409 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH3PRIS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 416 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH3PRIS_MASK   0x8UL

Bit mask for DMA_CH3PRIS

Definition at line 415 of file efm32zg_dma.h.

#define _DMA_CHPRIS_CH3PRIS_SHIFT   3

Shift value for DMA_CH3PRIS

Definition at line 414 of file efm32zg_dma.h.

#define _DMA_CHPRIS_MASK   0x0000000FUL

Mask for DMA_CHPRIS

Definition at line 397 of file efm32zg_dma.h.

#define _DMA_CHPRIS_RESETVALUE   0x00000000UL

Default value for DMA_CHPRIS

Definition at line 396 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 281 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_MASK   0x1UL

Bit mask for DMA_CH0REQMASKC

Definition at line 280 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT   0

Shift value for DMA_CH0REQMASKC

Definition at line 279 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 286 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_MASK   0x2UL

Bit mask for DMA_CH1REQMASKC

Definition at line 285 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT   1

Shift value for DMA_CH1REQMASKC

Definition at line 284 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 291 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_MASK   0x4UL

Bit mask for DMA_CH2REQMASKC

Definition at line 290 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT   2

Shift value for DMA_CH2REQMASKC

Definition at line 289 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 296 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_MASK   0x8UL

Bit mask for DMA_CH3REQMASKC

Definition at line 295 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT   3

Shift value for DMA_CH3REQMASKC

Definition at line 294 of file efm32zg_dma.h.

#define _DMA_CHREQMASKC_MASK   0x0000000FUL

Mask for DMA_CHREQMASKC

Definition at line 277 of file efm32zg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHREQMASKC_RESETVALUE   0x00000000UL

Default value for DMA_CHREQMASKC

Definition at line 276 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 257 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_MASK   0x1UL

Bit mask for DMA_CH0REQMASKS

Definition at line 256 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT   0

Shift value for DMA_CH0REQMASKS

Definition at line 255 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 262 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_MASK   0x2UL

Bit mask for DMA_CH1REQMASKS

Definition at line 261 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT   1

Shift value for DMA_CH1REQMASKS

Definition at line 260 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 267 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_MASK   0x4UL

Bit mask for DMA_CH2REQMASKS

Definition at line 266 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT   2

Shift value for DMA_CH2REQMASKS

Definition at line 265 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 272 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_MASK   0x8UL

Bit mask for DMA_CH3REQMASKS

Definition at line 271 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT   3

Shift value for DMA_CH3REQMASKS

Definition at line 270 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_MASK   0x0000000FUL

Mask for DMA_CHREQMASKS

Definition at line 253 of file efm32zg_dma.h.

#define _DMA_CHREQMASKS_RESETVALUE   0x00000000UL

Default value for DMA_CHREQMASKS

Definition at line 252 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 458 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK   0x1UL

Bit mask for DMA_CH0REQSTATUS

Definition at line 457 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT   0

Shift value for DMA_CH0REQSTATUS

Definition at line 456 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 463 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK   0x2UL

Bit mask for DMA_CH1REQSTATUS

Definition at line 462 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT   1

Shift value for DMA_CH1REQSTATUS

Definition at line 461 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 468 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK   0x4UL

Bit mask for DMA_CH2REQSTATUS

Definition at line 467 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT   2

Shift value for DMA_CH2REQSTATUS

Definition at line 466 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 473 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK   0x8UL

Bit mask for DMA_CH3REQSTATUS

Definition at line 472 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT   3

Shift value for DMA_CH3REQSTATUS

Definition at line 471 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_MASK   0x0000000FUL

Mask for DMA_CHREQSTATUS

Definition at line 454 of file efm32zg_dma.h.

#define _DMA_CHREQSTATUS_RESETVALUE   0x00000000UL

Default value for DMA_CHREQSTATUS

Definition at line 453 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 482 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK   0x1UL

Bit mask for DMA_CH0SREQSTATUS

Definition at line 481 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT   0

Shift value for DMA_CH0SREQSTATUS

Definition at line 480 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 487 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK   0x2UL

Bit mask for DMA_CH1SREQSTATUS

Definition at line 486 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT   1

Shift value for DMA_CH1SREQSTATUS

Definition at line 485 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 492 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK   0x4UL

Bit mask for DMA_CH2SREQSTATUS

Definition at line 491 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT   2

Shift value for DMA_CH2SREQSTATUS

Definition at line 490 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 497 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK   0x8UL

Bit mask for DMA_CH3SREQSTATUS

Definition at line 496 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT   3

Shift value for DMA_CH3SREQSTATUS

Definition at line 495 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_MASK   0x0000000FUL

Mask for DMA_CHSREQSTATUS

Definition at line 478 of file efm32zg_dma.h.

#define _DMA_CHSREQSTATUS_RESETVALUE   0x00000000UL

Default value for DMA_CHSREQSTATUS

Definition at line 477 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 181 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH0SWREQ_MASK   0x1UL

Bit mask for DMA_CH0SWREQ

Definition at line 180 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH0SWREQ_SHIFT   0

Shift value for DMA_CH0SWREQ

Definition at line 179 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 186 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH1SWREQ_MASK   0x2UL

Bit mask for DMA_CH1SWREQ

Definition at line 185 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH1SWREQ_SHIFT   1

Shift value for DMA_CH1SWREQ

Definition at line 184 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 191 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH2SWREQ_MASK   0x4UL

Bit mask for DMA_CH2SWREQ

Definition at line 190 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH2SWREQ_SHIFT   2

Shift value for DMA_CH2SWREQ

Definition at line 189 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 196 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH3SWREQ_MASK   0x8UL

Bit mask for DMA_CH3SWREQ

Definition at line 195 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_CH3SWREQ_SHIFT   3

Shift value for DMA_CH3SWREQ

Definition at line 194 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_MASK   0x0000000FUL

Mask for DMA_CHSWREQ

Definition at line 177 of file efm32zg_dma.h.

#define _DMA_CHSWREQ_RESETVALUE   0x00000000UL

Default value for DMA_CHSWREQ

Definition at line 176 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 233 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK   0x1UL

Bit mask for DMA_CH0USEBURSTC

Definition at line 232 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT   0

Shift value for DMA_CH0USEBURSTC

Definition at line 231 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 238 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK   0x2UL

Bit mask for DMA_CH1USEBURSTC

Definition at line 237 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT   1

Shift value for DMA_CH1USEBURSTC

Definition at line 236 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 243 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK   0x4UL

Bit mask for DMA_CH2USEBURSTC

Definition at line 242 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT   2

Shift value for DMA_CH2USEBURSTC

Definition at line 241 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 248 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK   0x8UL

Bit mask for DMA_CH3USEBURSTC

Definition at line 247 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT   3

Shift value for DMA_CH3USEBURSTC

Definition at line 246 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTC_MASK   0x0000000FUL

Mask for DMA_CHUSEBURSTC

Definition at line 229 of file efm32zg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHUSEBURSTC_RESETVALUE   0x00000000UL

Default value for DMA_CHUSEBURSTC

Definition at line 228 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   0x00000001UL

Mode BURSTONLY for DMA_CHUSEBURSTS

Definition at line 207 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 205 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK   0x1UL

Bit mask for DMA_CH0USEBURSTS

Definition at line 204 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT   0

Shift value for DMA_CH0USEBURSTS

Definition at line 203 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   0x00000000UL

Mode SINGLEANDBURST for DMA_CHUSEBURSTS

Definition at line 206 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 214 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK   0x2UL

Bit mask for DMA_CH1USEBURSTS

Definition at line 213 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT   1

Shift value for DMA_CH1USEBURSTS

Definition at line 212 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 219 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK   0x4UL

Bit mask for DMA_CH2USEBURSTS

Definition at line 218 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT   2

Shift value for DMA_CH2USEBURSTS

Definition at line 217 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 224 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK   0x8UL

Bit mask for DMA_CH3USEBURSTS

Definition at line 223 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT   3

Shift value for DMA_CH3USEBURSTS

Definition at line 222 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_MASK   0x0000000FUL

Mask for DMA_CHUSEBURSTS

Definition at line 201 of file efm32zg_dma.h.

#define _DMA_CHUSEBURSTS_RESETVALUE   0x00000000UL

Default value for DMA_CHUSEBURSTS

Definition at line 200 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 157 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK   0x1UL

Bit mask for DMA_CH0WAITSTATUS

Definition at line 156 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT   0

Shift value for DMA_CH0WAITSTATUS

Definition at line 155 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 162 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK   0x2UL

Bit mask for DMA_CH1WAITSTATUS

Definition at line 161 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT   1

Shift value for DMA_CH1WAITSTATUS

Definition at line 160 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 167 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK   0x4UL

Bit mask for DMA_CH2WAITSTATUS

Definition at line 166 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT   2

Shift value for DMA_CH2WAITSTATUS

Definition at line 165 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 172 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK   0x8UL

Bit mask for DMA_CH3WAITSTATUS

Definition at line 171 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT   3

Shift value for DMA_CH3WAITSTATUS

Definition at line 170 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_MASK   0x0000000FUL

Mask for DMA_CHWAITSTATUS

Definition at line 153 of file efm32zg_dma.h.

#define _DMA_CHWAITSTATUS_RESETVALUE   0x0000000FUL

Default value for DMA_CHWAITSTATUS

Definition at line 152 of file efm32zg_dma.h.

#define _DMA_CONFIG_CHPROT_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CONFIG

Definition at line 132 of file efm32zg_dma.h.

#define _DMA_CONFIG_CHPROT_MASK   0x20UL

Bit mask for DMA_CHPROT

Definition at line 131 of file efm32zg_dma.h.

#define _DMA_CONFIG_CHPROT_SHIFT   5

Shift value for DMA_CHPROT

Definition at line 130 of file efm32zg_dma.h.

Referenced by DMA_Init().

#define _DMA_CONFIG_EN_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CONFIG

Definition at line 127 of file efm32zg_dma.h.

#define _DMA_CONFIG_EN_MASK   0x1UL

Bit mask for DMA_EN

Definition at line 126 of file efm32zg_dma.h.

#define _DMA_CONFIG_EN_SHIFT   0

Shift value for DMA_EN

Definition at line 125 of file efm32zg_dma.h.

#define _DMA_CONFIG_MASK   0x00000021UL

Mask for DMA_CONFIG

Definition at line 123 of file efm32zg_dma.h.

#define _DMA_CONFIG_RESETVALUE   0x00000000UL

Default value for DMA_CONFIG

Definition at line 122 of file efm32zg_dma.h.

Referenced by DMA_Reset(), and DMADRV_DeInit().

#define _DMA_CTRLBASE_CTRLBASE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_CTRLBASE

Definition at line 140 of file efm32zg_dma.h.

#define _DMA_CTRLBASE_CTRLBASE_MASK   0xFFFFFFFFUL

Bit mask for DMA_CTRLBASE

Definition at line 139 of file efm32zg_dma.h.

#define _DMA_CTRLBASE_CTRLBASE_SHIFT   0

Shift value for DMA_CTRLBASE

Definition at line 138 of file efm32zg_dma.h.

#define _DMA_CTRLBASE_MASK   0xFFFFFFFFUL

Mask for DMA_CTRLBASE

Definition at line 137 of file efm32zg_dma.h.

#define _DMA_CTRLBASE_RESETVALUE   0x00000000UL

Default value for DMA_CTRLBASE

Definition at line 136 of file efm32zg_dma.h.

#define _DMA_ERRORC_ERRORC_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_ERRORC

Definition at line 449 of file efm32zg_dma.h.

#define _DMA_ERRORC_ERRORC_MASK   0x1UL

Bit mask for DMA_ERRORC

Definition at line 448 of file efm32zg_dma.h.

#define _DMA_ERRORC_ERRORC_SHIFT   0

Shift value for DMA_ERRORC

Definition at line 447 of file efm32zg_dma.h.

#define _DMA_ERRORC_MASK   0x00000001UL

Mask for DMA_ERRORC

Definition at line 445 of file efm32zg_dma.h.

#define _DMA_ERRORC_RESETVALUE   0x00000000UL

Default value for DMA_ERRORC

Definition at line 444 of file efm32zg_dma.h.

#define _DMA_IEN_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 593 of file efm32zg_dma.h.

#define _DMA_IEN_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 592 of file efm32zg_dma.h.

#define _DMA_IEN_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 591 of file efm32zg_dma.h.

#define _DMA_IEN_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 598 of file efm32zg_dma.h.

#define _DMA_IEN_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 597 of file efm32zg_dma.h.

#define _DMA_IEN_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 596 of file efm32zg_dma.h.

#define _DMA_IEN_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 603 of file efm32zg_dma.h.

#define _DMA_IEN_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 602 of file efm32zg_dma.h.

#define _DMA_IEN_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 601 of file efm32zg_dma.h.

#define _DMA_IEN_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 608 of file efm32zg_dma.h.

#define _DMA_IEN_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 607 of file efm32zg_dma.h.

#define _DMA_IEN_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 606 of file efm32zg_dma.h.

#define _DMA_IEN_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 613 of file efm32zg_dma.h.

#define _DMA_IEN_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 612 of file efm32zg_dma.h.

#define _DMA_IEN_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 611 of file efm32zg_dma.h.

#define _DMA_IEN_MASK   0x8000000FUL

Mask for DMA_IEN

Definition at line 589 of file efm32zg_dma.h.

#define _DMA_IEN_RESETVALUE   0x00000000UL

Default value for DMA_IEN

Definition at line 588 of file efm32zg_dma.h.

Referenced by DMA_Reset(), and DMADRV_DeInit().

#define _DMA_IF_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 506 of file efm32zg_dma.h.

#define _DMA_IF_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 505 of file efm32zg_dma.h.

#define _DMA_IF_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 504 of file efm32zg_dma.h.

#define _DMA_IF_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 511 of file efm32zg_dma.h.

#define _DMA_IF_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 510 of file efm32zg_dma.h.

#define _DMA_IF_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 509 of file efm32zg_dma.h.

#define _DMA_IF_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 516 of file efm32zg_dma.h.

#define _DMA_IF_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 515 of file efm32zg_dma.h.

#define _DMA_IF_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 514 of file efm32zg_dma.h.

#define _DMA_IF_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 521 of file efm32zg_dma.h.

#define _DMA_IF_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 520 of file efm32zg_dma.h.

#define _DMA_IF_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 519 of file efm32zg_dma.h.

#define _DMA_IF_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 526 of file efm32zg_dma.h.

#define _DMA_IF_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 525 of file efm32zg_dma.h.

#define _DMA_IF_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 524 of file efm32zg_dma.h.

#define _DMA_IF_MASK   0x8000000FUL

Mask for DMA_IF

Definition at line 502 of file efm32zg_dma.h.

#define _DMA_IF_RESETVALUE   0x00000000UL

Default value for DMA_IF

Definition at line 501 of file efm32zg_dma.h.

#define _DMA_IFC_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 564 of file efm32zg_dma.h.

#define _DMA_IFC_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 563 of file efm32zg_dma.h.

#define _DMA_IFC_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 562 of file efm32zg_dma.h.

#define _DMA_IFC_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 569 of file efm32zg_dma.h.

#define _DMA_IFC_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 568 of file efm32zg_dma.h.

#define _DMA_IFC_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 567 of file efm32zg_dma.h.

#define _DMA_IFC_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 574 of file efm32zg_dma.h.

#define _DMA_IFC_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 573 of file efm32zg_dma.h.

#define _DMA_IFC_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 572 of file efm32zg_dma.h.

#define _DMA_IFC_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 579 of file efm32zg_dma.h.

#define _DMA_IFC_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 578 of file efm32zg_dma.h.

#define _DMA_IFC_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 577 of file efm32zg_dma.h.

#define _DMA_IFC_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 584 of file efm32zg_dma.h.

#define _DMA_IFC_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 583 of file efm32zg_dma.h.

#define _DMA_IFC_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 582 of file efm32zg_dma.h.

#define _DMA_IFC_MASK   0x8000000FUL

Mask for DMA_IFC

Definition at line 560 of file efm32zg_dma.h.

Referenced by DMA_Reset().

#define _DMA_IFC_RESETVALUE   0x00000000UL

Default value for DMA_IFC

Definition at line 559 of file efm32zg_dma.h.

#define _DMA_IFS_CH0DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 535 of file efm32zg_dma.h.

#define _DMA_IFS_CH0DONE_MASK   0x1UL

Bit mask for DMA_CH0DONE

Definition at line 534 of file efm32zg_dma.h.

#define _DMA_IFS_CH0DONE_SHIFT   0

Shift value for DMA_CH0DONE

Definition at line 533 of file efm32zg_dma.h.

#define _DMA_IFS_CH1DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 540 of file efm32zg_dma.h.

#define _DMA_IFS_CH1DONE_MASK   0x2UL

Bit mask for DMA_CH1DONE

Definition at line 539 of file efm32zg_dma.h.

#define _DMA_IFS_CH1DONE_SHIFT   1

Shift value for DMA_CH1DONE

Definition at line 538 of file efm32zg_dma.h.

#define _DMA_IFS_CH2DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 545 of file efm32zg_dma.h.

#define _DMA_IFS_CH2DONE_MASK   0x4UL

Bit mask for DMA_CH2DONE

Definition at line 544 of file efm32zg_dma.h.

#define _DMA_IFS_CH2DONE_SHIFT   2

Shift value for DMA_CH2DONE

Definition at line 543 of file efm32zg_dma.h.

#define _DMA_IFS_CH3DONE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 550 of file efm32zg_dma.h.

#define _DMA_IFS_CH3DONE_MASK   0x8UL

Bit mask for DMA_CH3DONE

Definition at line 549 of file efm32zg_dma.h.

#define _DMA_IFS_CH3DONE_SHIFT   3

Shift value for DMA_CH3DONE

Definition at line 548 of file efm32zg_dma.h.

#define _DMA_IFS_ERR_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 555 of file efm32zg_dma.h.

#define _DMA_IFS_ERR_MASK   0x80000000UL

Bit mask for DMA_ERR

Definition at line 554 of file efm32zg_dma.h.

#define _DMA_IFS_ERR_SHIFT   31

Shift value for DMA_ERR

Definition at line 553 of file efm32zg_dma.h.

#define _DMA_IFS_MASK   0x8000000FUL

Mask for DMA_IFS

Definition at line 531 of file efm32zg_dma.h.

#define _DMA_IFS_RESETVALUE   0x00000000UL

Default value for DMA_IFS

Definition at line 530 of file efm32zg_dma.h.

#define _DMA_STATUS_CHNUM_DEFAULT   0x00000003UL

Mode DEFAULT for DMA_STATUS

Definition at line 118 of file efm32zg_dma.h.

#define _DMA_STATUS_CHNUM_MASK   0x1F0000UL

Bit mask for DMA_CHNUM

Definition at line 117 of file efm32zg_dma.h.

#define _DMA_STATUS_CHNUM_SHIFT   16

Shift value for DMA_CHNUM

Definition at line 116 of file efm32zg_dma.h.

#define _DMA_STATUS_EN_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_STATUS

Definition at line 88 of file efm32zg_dma.h.

#define _DMA_STATUS_EN_MASK   0x1UL

Bit mask for DMA_EN

Definition at line 87 of file efm32zg_dma.h.

#define _DMA_STATUS_EN_SHIFT   0

Shift value for DMA_EN

Definition at line 86 of file efm32zg_dma.h.

#define _DMA_STATUS_MASK   0x001F00F1UL

Mask for DMA_STATUS

Definition at line 84 of file efm32zg_dma.h.

#define _DMA_STATUS_RESETVALUE   0x10030000UL

Default value for DMA_STATUS

Definition at line 83 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_DEFAULT   0x00000000UL

Mode DEFAULT for DMA_STATUS

Definition at line 92 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_DONE   0x00000009UL

Mode DONE for DMA_STATUS

Definition at line 102 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_IDLE   0x00000000UL

Mode IDLE for DMA_STATUS

Definition at line 93 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_MASK   0xF0UL

Bit mask for DMA_STATE

Definition at line 91 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_PERSCATTRANS   0x0000000AUL

Mode PERSCATTRANS for DMA_STATUS

Definition at line 103 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_RDCHCTRLDATA   0x00000001UL

Mode RDCHCTRLDATA for DMA_STATUS

Definition at line 94 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_RDDSTENDPTR   0x00000003UL

Mode RDDSTENDPTR for DMA_STATUS

Definition at line 96 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_RDSRCDATA   0x00000004UL

Mode RDSRCDATA for DMA_STATUS

Definition at line 97 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_RDSRCENDPTR   0x00000002UL

Mode RDSRCENDPTR for DMA_STATUS

Definition at line 95 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_SHIFT   4

Shift value for DMA_STATE

Definition at line 90 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_STALLED   0x00000008UL

Mode STALLED for DMA_STATUS

Definition at line 101 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_WAITREQCLR   0x00000006UL

Mode WAITREQCLR for DMA_STATUS

Definition at line 99 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_WRCHCTRLDATA   0x00000007UL

Mode WRCHCTRLDATA for DMA_STATUS

Definition at line 100 of file efm32zg_dma.h.

#define _DMA_STATUS_STATE_WRDSTDATA   0x00000005UL

Mode WRDSTDATA for DMA_STATUS

Definition at line 98 of file efm32zg_dma.h.

#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT   (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_ALTCTRLBASE

Definition at line 149 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_ADC0SCAN   (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)

Shifted mode ADC0SCAN for DMA_CH_CTRL

Definition at line 654 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)

Shifted mode ADC0SINGLE for DMA_CH_CTRL

Definition at line 646 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESDATARD   (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)

Shifted mode AESDATARD for DMA_CH_CTRL

Definition at line 665 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESDATAWR   (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)

Shifted mode AESDATAWR for DMA_CH_CTRL

Definition at line 653 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESKEYWR   (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)

Shifted mode AESKEYWR for DMA_CH_CTRL

Definition at line 669 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR   (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)

Shifted mode AESXORDATAWR for DMA_CH_CTRL

Definition at line 660 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV   (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)

Shifted mode I2C0RXDATAV for DMA_CH_CTRL

Definition at line 649 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_I2C0TXBL   (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)

Shifted mode I2C0TXBL for DMA_CH_CTRL

Definition at line 657 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV   (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)

Shifted mode LEUART0RXDATAV for DMA_CH_CTRL

Definition at line 648 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL   (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)

Shifted mode LEUART0TXBL for DMA_CH_CTRL

Definition at line 656 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY   (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)

Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL

Definition at line 662 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_MSCWDATA   (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)

Shifted mode MSCWDATA for DMA_CH_CTRL

Definition at line 652 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC0   (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)

Shifted mode TIMER0CC0 for DMA_CH_CTRL

Definition at line 658 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC1   (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)

Shifted mode TIMER0CC1 for DMA_CH_CTRL

Definition at line 663 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC2   (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)

Shifted mode TIMER0CC2 for DMA_CH_CTRL

Definition at line 667 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)

Shifted mode TIMER0UFOF for DMA_CH_CTRL

Definition at line 650 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC0   (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)

Shifted mode TIMER1CC0 for DMA_CH_CTRL

Definition at line 659 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC1   (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)

Shifted mode TIMER1CC1 for DMA_CH_CTRL

Definition at line 664 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC2   (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)

Shifted mode TIMER1CC2 for DMA_CH_CTRL

Definition at line 668 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)

Shifted mode TIMER1UFOF for DMA_CH_CTRL

Definition at line 651 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)

Shifted mode USART1RXDATAV for DMA_CH_CTRL

Definition at line 647 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT   (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0)

Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL

Definition at line 666 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1TXBL   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)

Shifted mode USART1TXBL for DMA_CH_CTRL

Definition at line 655 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT   (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)

Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL

Definition at line 670 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY   (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)

Shifted mode USART1TXEMPTY for DMA_CH_CTRL

Definition at line 661 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_ADC0   (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)

Shifted mode ADC0 for DMA_CH_CTRL

Definition at line 683 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_AES   (_DMA_CH_CTRL_SOURCESEL_AES << 16)

Shifted mode AES for DMA_CH_CTRL

Definition at line 690 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_I2C0   (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)

Shifted mode I2C0 for DMA_CH_CTRL

Definition at line 686 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_LEUART0   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)

Shifted mode LEUART0 for DMA_CH_CTRL

Definition at line 685 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_MSC   (_DMA_CH_CTRL_SOURCESEL_MSC << 16)

Shifted mode MSC for DMA_CH_CTRL

Definition at line 689 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_NONE   (_DMA_CH_CTRL_SOURCESEL_NONE << 16)

Shifted mode NONE for DMA_CH_CTRL

Definition at line 682 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER0   (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)

Shifted mode TIMER0 for DMA_CH_CTRL

Definition at line 687 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER1   (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)

Shifted mode TIMER1 for DMA_CH_CTRL

Definition at line 688 of file efm32zg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_USART1   (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)

Shifted mode USART1 for DMA_CH_CTRL

Definition at line 684 of file efm32zg_dma.h.

#define DMA_CHALTC_CH0ALTC   (0x1UL << 0)

Channel 0 Alternate Clear

Definition at line 374 of file efm32zg_dma.h.

#define DMA_CHALTC_CH0ALTC_DEFAULT   (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 378 of file efm32zg_dma.h.

#define DMA_CHALTC_CH1ALTC   (0x1UL << 1)

Channel 1 Alternate Clear

Definition at line 379 of file efm32zg_dma.h.

#define DMA_CHALTC_CH1ALTC_DEFAULT   (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 383 of file efm32zg_dma.h.

#define DMA_CHALTC_CH2ALTC   (0x1UL << 2)

Channel 2 Alternate Clear

Definition at line 384 of file efm32zg_dma.h.

#define DMA_CHALTC_CH2ALTC_DEFAULT   (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 388 of file efm32zg_dma.h.

#define DMA_CHALTC_CH3ALTC   (0x1UL << 3)

Channel 3 Alternate Clear

Definition at line 389 of file efm32zg_dma.h.

#define DMA_CHALTC_CH3ALTC_DEFAULT   (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 393 of file efm32zg_dma.h.

#define DMA_CHALTS_CH0ALTS   (0x1UL << 0)

Channel 0 Alternate Structure Set

Definition at line 350 of file efm32zg_dma.h.

#define DMA_CHALTS_CH0ALTS_DEFAULT   (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 354 of file efm32zg_dma.h.

#define DMA_CHALTS_CH1ALTS   (0x1UL << 1)

Channel 1 Alternate Structure Set

Definition at line 355 of file efm32zg_dma.h.

#define DMA_CHALTS_CH1ALTS_DEFAULT   (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 359 of file efm32zg_dma.h.

#define DMA_CHALTS_CH2ALTS   (0x1UL << 2)

Channel 2 Alternate Structure Set

Definition at line 360 of file efm32zg_dma.h.

#define DMA_CHALTS_CH2ALTS_DEFAULT   (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 364 of file efm32zg_dma.h.

#define DMA_CHALTS_CH3ALTS   (0x1UL << 3)

Channel 3 Alternate Structure Set

Definition at line 365 of file efm32zg_dma.h.

#define DMA_CHALTS_CH3ALTS_DEFAULT   (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 369 of file efm32zg_dma.h.

#define DMA_CHENC_CH0ENC   (0x1UL << 0)

Channel 0 Enable Clear

Definition at line 326 of file efm32zg_dma.h.

#define DMA_CHENC_CH0ENC_DEFAULT   (_DMA_CHENC_CH0ENC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 330 of file efm32zg_dma.h.

#define DMA_CHENC_CH1ENC   (0x1UL << 1)

Channel 1 Enable Clear

Definition at line 331 of file efm32zg_dma.h.

#define DMA_CHENC_CH1ENC_DEFAULT   (_DMA_CHENC_CH1ENC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 335 of file efm32zg_dma.h.

#define DMA_CHENC_CH2ENC   (0x1UL << 2)

Channel 2 Enable Clear

Definition at line 336 of file efm32zg_dma.h.

#define DMA_CHENC_CH2ENC_DEFAULT   (_DMA_CHENC_CH2ENC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 340 of file efm32zg_dma.h.

#define DMA_CHENC_CH3ENC   (0x1UL << 3)

Channel 3 Enable Clear

Definition at line 341 of file efm32zg_dma.h.

#define DMA_CHENC_CH3ENC_DEFAULT   (_DMA_CHENC_CH3ENC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 345 of file efm32zg_dma.h.

#define DMA_CHENS_CH0ENS   (0x1UL << 0)

Channel 0 Enable Set

Definition at line 302 of file efm32zg_dma.h.

#define DMA_CHENS_CH0ENS_DEFAULT   (_DMA_CHENS_CH0ENS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 306 of file efm32zg_dma.h.

#define DMA_CHENS_CH1ENS   (0x1UL << 1)

Channel 1 Enable Set

Definition at line 307 of file efm32zg_dma.h.

#define DMA_CHENS_CH1ENS_DEFAULT   (_DMA_CHENS_CH1ENS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 311 of file efm32zg_dma.h.

#define DMA_CHENS_CH2ENS   (0x1UL << 2)

Channel 2 Enable Set

Definition at line 312 of file efm32zg_dma.h.

#define DMA_CHENS_CH2ENS_DEFAULT   (_DMA_CHENS_CH2ENS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 316 of file efm32zg_dma.h.

#define DMA_CHENS_CH3ENS   (0x1UL << 3)

Channel 3 Enable Set

Definition at line 317 of file efm32zg_dma.h.

#define DMA_CHENS_CH3ENS_DEFAULT   (_DMA_CHENS_CH3ENS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 321 of file efm32zg_dma.h.

#define DMA_CHPRIC_CH0PRIC   (0x1UL << 0)

Channel 0 High Priority Clear

Definition at line 422 of file efm32zg_dma.h.

#define DMA_CHPRIC_CH0PRIC_DEFAULT   (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 426 of file efm32zg_dma.h.

#define DMA_CHPRIC_CH1PRIC   (0x1UL << 1)

Channel 1 High Priority Clear

Definition at line 427 of file efm32zg_dma.h.

#define DMA_CHPRIC_CH1PRIC_DEFAULT   (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 431 of file efm32zg_dma.h.

#define DMA_CHPRIC_CH2PRIC   (0x1UL << 2)

Channel 2 High Priority Clear

Definition at line 432 of file efm32zg_dma.h.

#define DMA_CHPRIC_CH2PRIC_DEFAULT   (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 436 of file efm32zg_dma.h.

#define DMA_CHPRIC_CH3PRIC   (0x1UL << 3)

Channel 3 High Priority Clear

Definition at line 437 of file efm32zg_dma.h.

#define DMA_CHPRIC_CH3PRIC_DEFAULT   (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 441 of file efm32zg_dma.h.

#define DMA_CHPRIS_CH0PRIS   (0x1UL << 0)

Channel 0 High Priority Set

Definition at line 398 of file efm32zg_dma.h.

#define DMA_CHPRIS_CH0PRIS_DEFAULT   (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 402 of file efm32zg_dma.h.

#define DMA_CHPRIS_CH1PRIS   (0x1UL << 1)

Channel 1 High Priority Set

Definition at line 403 of file efm32zg_dma.h.

#define DMA_CHPRIS_CH1PRIS_DEFAULT   (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 407 of file efm32zg_dma.h.

#define DMA_CHPRIS_CH2PRIS   (0x1UL << 2)

Channel 2 High Priority Set

Definition at line 408 of file efm32zg_dma.h.

#define DMA_CHPRIS_CH2PRIS_DEFAULT   (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 412 of file efm32zg_dma.h.

#define DMA_CHPRIS_CH3PRIS   (0x1UL << 3)

Channel 3 High Priority Set

Definition at line 413 of file efm32zg_dma.h.

#define DMA_CHPRIS_CH3PRIS_DEFAULT   (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 417 of file efm32zg_dma.h.

#define DMA_CHREQMASKC_CH0REQMASKC   (0x1UL << 0)

Channel 0 Request Mask Clear

Definition at line 278 of file efm32zg_dma.h.

#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 282 of file efm32zg_dma.h.

#define DMA_CHREQMASKC_CH1REQMASKC   (0x1UL << 1)

Channel 1 Request Mask Clear

Definition at line 283 of file efm32zg_dma.h.

#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 287 of file efm32zg_dma.h.

#define DMA_CHREQMASKC_CH2REQMASKC   (0x1UL << 2)

Channel 2 Request Mask Clear

Definition at line 288 of file efm32zg_dma.h.

#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 292 of file efm32zg_dma.h.

#define DMA_CHREQMASKC_CH3REQMASKC   (0x1UL << 3)

Channel 3 Request Mask Clear

Definition at line 293 of file efm32zg_dma.h.

#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT   (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 297 of file efm32zg_dma.h.

#define DMA_CHREQMASKS_CH0REQMASKS   (0x1UL << 0)

Channel 0 Request Mask Set

Definition at line 254 of file efm32zg_dma.h.

#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 258 of file efm32zg_dma.h.

#define DMA_CHREQMASKS_CH1REQMASKS   (0x1UL << 1)

Channel 1 Request Mask Set

Definition at line 259 of file efm32zg_dma.h.

#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 263 of file efm32zg_dma.h.

#define DMA_CHREQMASKS_CH2REQMASKS   (0x1UL << 2)

Channel 2 Request Mask Set

Definition at line 264 of file efm32zg_dma.h.

#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 268 of file efm32zg_dma.h.

#define DMA_CHREQMASKS_CH3REQMASKS   (0x1UL << 3)

Channel 3 Request Mask Set

Definition at line 269 of file efm32zg_dma.h.

#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT   (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 273 of file efm32zg_dma.h.

#define DMA_CHREQSTATUS_CH0REQSTATUS   (0x1UL << 0)

Channel 0 Request Status

Definition at line 455 of file efm32zg_dma.h.

#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 459 of file efm32zg_dma.h.

#define DMA_CHREQSTATUS_CH1REQSTATUS   (0x1UL << 1)

Channel 1 Request Status

Definition at line 460 of file efm32zg_dma.h.

#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 464 of file efm32zg_dma.h.

#define DMA_CHREQSTATUS_CH2REQSTATUS   (0x1UL << 2)

Channel 2 Request Status

Definition at line 465 of file efm32zg_dma.h.

#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 469 of file efm32zg_dma.h.

#define DMA_CHREQSTATUS_CH3REQSTATUS   (0x1UL << 3)

Channel 3 Request Status

Definition at line 470 of file efm32zg_dma.h.

#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT   (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 474 of file efm32zg_dma.h.

#define DMA_CHSREQSTATUS_CH0SREQSTATUS   (0x1UL << 0)

Channel 0 Single Request Status

Definition at line 479 of file efm32zg_dma.h.

#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 483 of file efm32zg_dma.h.

#define DMA_CHSREQSTATUS_CH1SREQSTATUS   (0x1UL << 1)

Channel 1 Single Request Status

Definition at line 484 of file efm32zg_dma.h.

#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 488 of file efm32zg_dma.h.

#define DMA_CHSREQSTATUS_CH2SREQSTATUS   (0x1UL << 2)

Channel 2 Single Request Status

Definition at line 489 of file efm32zg_dma.h.

#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 493 of file efm32zg_dma.h.

#define DMA_CHSREQSTATUS_CH3SREQSTATUS   (0x1UL << 3)

Channel 3 Single Request Status

Definition at line 494 of file efm32zg_dma.h.

#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT   (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 498 of file efm32zg_dma.h.

#define DMA_CHSWREQ_CH0SWREQ   (0x1UL << 0)

Channel 0 Software Request

Definition at line 178 of file efm32zg_dma.h.

#define DMA_CHSWREQ_CH0SWREQ_DEFAULT   (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 182 of file efm32zg_dma.h.

#define DMA_CHSWREQ_CH1SWREQ   (0x1UL << 1)

Channel 1 Software Request

Definition at line 183 of file efm32zg_dma.h.

#define DMA_CHSWREQ_CH1SWREQ_DEFAULT   (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 187 of file efm32zg_dma.h.

#define DMA_CHSWREQ_CH2SWREQ   (0x1UL << 2)

Channel 2 Software Request

Definition at line 188 of file efm32zg_dma.h.

#define DMA_CHSWREQ_CH2SWREQ_DEFAULT   (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 192 of file efm32zg_dma.h.

#define DMA_CHSWREQ_CH3SWREQ   (0x1UL << 3)

Channel 3 Software Request

Definition at line 193 of file efm32zg_dma.h.

#define DMA_CHSWREQ_CH3SWREQ_DEFAULT   (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 197 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTC_CH0USEBURSTC   (0x1UL << 0)

Channel 0 Useburst Clear

Definition at line 230 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 234 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTC_CH1USEBURSTC   (0x1UL << 1)

Channel 1 Useburst Clear

Definition at line 235 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 239 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTC_CH2USEBURSTC   (0x1UL << 2)

Channel 2 Useburst Clear

Definition at line 240 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 244 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTC_CH3USEBURSTC   (0x1UL << 3)

Channel 3 Useburst Clear

Definition at line 245 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT   (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 249 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS   (0x1UL << 0)

Channel 0 Useburst Set

Definition at line 202 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY   (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)

Shifted mode BURSTONLY for DMA_CHUSEBURSTS

Definition at line 210 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 208 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST   (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)

Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS

Definition at line 209 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH1USEBURSTS   (0x1UL << 1)

Channel 1 Useburst Set

Definition at line 211 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 215 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH2USEBURSTS   (0x1UL << 2)

Channel 2 Useburst Set

Definition at line 216 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 220 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH3USEBURSTS   (0x1UL << 3)

Channel 3 Useburst Set

Definition at line 221 of file efm32zg_dma.h.

#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT   (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 225 of file efm32zg_dma.h.

#define DMA_CHWAITSTATUS_CH0WAITSTATUS   (0x1UL << 0)

Channel 0 Wait on Request Status

Definition at line 154 of file efm32zg_dma.h.

#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 158 of file efm32zg_dma.h.

#define DMA_CHWAITSTATUS_CH1WAITSTATUS   (0x1UL << 1)

Channel 1 Wait on Request Status

Definition at line 159 of file efm32zg_dma.h.

#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 163 of file efm32zg_dma.h.

#define DMA_CHWAITSTATUS_CH2WAITSTATUS   (0x1UL << 2)

Channel 2 Wait on Request Status

Definition at line 164 of file efm32zg_dma.h.

#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 168 of file efm32zg_dma.h.

#define DMA_CHWAITSTATUS_CH3WAITSTATUS   (0x1UL << 3)

Channel 3 Wait on Request Status

Definition at line 169 of file efm32zg_dma.h.

#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT   (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 173 of file efm32zg_dma.h.

#define DMA_CONFIG_CHPROT   (0x1UL << 5)

Channel Protection Control

Definition at line 129 of file efm32zg_dma.h.

#define DMA_CONFIG_CHPROT_DEFAULT   (_DMA_CONFIG_CHPROT_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CONFIG

Definition at line 133 of file efm32zg_dma.h.

#define DMA_CONFIG_EN   (0x1UL << 0)

Enable DMA

Definition at line 124 of file efm32zg_dma.h.

Referenced by DMA_Init().

#define DMA_CONFIG_EN_DEFAULT   (_DMA_CONFIG_EN_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CONFIG

Definition at line 128 of file efm32zg_dma.h.

#define DMA_CTRLBASE_CTRLBASE_DEFAULT   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CTRLBASE

Definition at line 141 of file efm32zg_dma.h.

#define DMA_ERRORC_ERRORC   (0x1UL << 0)

Bus Error Clear

Definition at line 446 of file efm32zg_dma.h.

Referenced by DMA_Reset().

#define DMA_ERRORC_ERRORC_DEFAULT   (_DMA_ERRORC_ERRORC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_ERRORC

Definition at line 450 of file efm32zg_dma.h.

#define DMA_IEN_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Enable

Definition at line 590 of file efm32zg_dma.h.

#define DMA_IEN_CH0DONE_DEFAULT   (_DMA_IEN_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IEN

Definition at line 594 of file efm32zg_dma.h.

#define DMA_IEN_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Enable

Definition at line 595 of file efm32zg_dma.h.

#define DMA_IEN_CH1DONE_DEFAULT   (_DMA_IEN_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IEN

Definition at line 599 of file efm32zg_dma.h.

#define DMA_IEN_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Enable

Definition at line 600 of file efm32zg_dma.h.

#define DMA_IEN_CH2DONE_DEFAULT   (_DMA_IEN_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IEN

Definition at line 604 of file efm32zg_dma.h.

#define DMA_IEN_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Enable

Definition at line 605 of file efm32zg_dma.h.

#define DMA_IEN_CH3DONE_DEFAULT   (_DMA_IEN_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IEN

Definition at line 609 of file efm32zg_dma.h.

#define DMA_IEN_ERR   (0x1UL << 31)

DMA Error Interrupt Flag Enable

Definition at line 610 of file efm32zg_dma.h.

Referenced by DMA_Init().

#define DMA_IEN_ERR_DEFAULT   (_DMA_IEN_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IEN

Definition at line 614 of file efm32zg_dma.h.

#define DMA_IF_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag

Definition at line 503 of file efm32zg_dma.h.

#define DMA_IF_CH0DONE_DEFAULT   (_DMA_IF_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IF

Definition at line 507 of file efm32zg_dma.h.

#define DMA_IF_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag

Definition at line 508 of file efm32zg_dma.h.

#define DMA_IF_CH1DONE_DEFAULT   (_DMA_IF_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IF

Definition at line 512 of file efm32zg_dma.h.

#define DMA_IF_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag

Definition at line 513 of file efm32zg_dma.h.

#define DMA_IF_CH2DONE_DEFAULT   (_DMA_IF_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IF

Definition at line 517 of file efm32zg_dma.h.

#define DMA_IF_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag

Definition at line 518 of file efm32zg_dma.h.

#define DMA_IF_CH3DONE_DEFAULT   (_DMA_IF_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IF

Definition at line 522 of file efm32zg_dma.h.

#define DMA_IF_ERR   (0x1UL << 31)

DMA Error Interrupt Flag

Definition at line 523 of file efm32zg_dma.h.

Referenced by DMA_IRQHandler().

#define DMA_IF_ERR_DEFAULT   (_DMA_IF_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IF

Definition at line 527 of file efm32zg_dma.h.

#define DMA_IFC_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag Clear

Definition at line 561 of file efm32zg_dma.h.

#define DMA_IFC_CH0DONE_DEFAULT   (_DMA_IFC_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IFC

Definition at line 565 of file efm32zg_dma.h.

#define DMA_IFC_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag Clear

Definition at line 566 of file efm32zg_dma.h.

#define DMA_IFC_CH1DONE_DEFAULT   (_DMA_IFC_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IFC

Definition at line 570 of file efm32zg_dma.h.

#define DMA_IFC_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag Clear

Definition at line 571 of file efm32zg_dma.h.

#define DMA_IFC_CH2DONE_DEFAULT   (_DMA_IFC_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IFC

Definition at line 575 of file efm32zg_dma.h.

#define DMA_IFC_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag Clear

Definition at line 576 of file efm32zg_dma.h.

#define DMA_IFC_CH3DONE_DEFAULT   (_DMA_IFC_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IFC

Definition at line 580 of file efm32zg_dma.h.

#define DMA_IFC_ERR   (0x1UL << 31)

DMA Error Interrupt Flag Clear

Definition at line 581 of file efm32zg_dma.h.

#define DMA_IFC_ERR_DEFAULT   (_DMA_IFC_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IFC

Definition at line 585 of file efm32zg_dma.h.

#define DMA_IFS_CH0DONE   (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag Set

Definition at line 532 of file efm32zg_dma.h.

#define DMA_IFS_CH0DONE_DEFAULT   (_DMA_IFS_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IFS

Definition at line 536 of file efm32zg_dma.h.

#define DMA_IFS_CH1DONE   (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag Set

Definition at line 537 of file efm32zg_dma.h.

#define DMA_IFS_CH1DONE_DEFAULT   (_DMA_IFS_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IFS

Definition at line 541 of file efm32zg_dma.h.

#define DMA_IFS_CH2DONE   (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag Set

Definition at line 542 of file efm32zg_dma.h.

#define DMA_IFS_CH2DONE_DEFAULT   (_DMA_IFS_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IFS

Definition at line 546 of file efm32zg_dma.h.

#define DMA_IFS_CH3DONE   (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag Set

Definition at line 547 of file efm32zg_dma.h.

#define DMA_IFS_CH3DONE_DEFAULT   (_DMA_IFS_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IFS

Definition at line 551 of file efm32zg_dma.h.

#define DMA_IFS_ERR   (0x1UL << 31)

DMA Error Interrupt Flag Set

Definition at line 552 of file efm32zg_dma.h.

#define DMA_IFS_ERR_DEFAULT   (_DMA_IFS_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IFS

Definition at line 556 of file efm32zg_dma.h.

#define DMA_STATUS_CHNUM_DEFAULT   (_DMA_STATUS_CHNUM_DEFAULT << 16)

Shifted mode DEFAULT for DMA_STATUS

Definition at line 119 of file efm32zg_dma.h.

#define DMA_STATUS_EN   (0x1UL << 0)

DMA Enable Status

Definition at line 85 of file efm32zg_dma.h.

#define DMA_STATUS_EN_DEFAULT   (_DMA_STATUS_EN_DEFAULT << 0)

Shifted mode DEFAULT for DMA_STATUS

Definition at line 89 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_DEFAULT   (_DMA_STATUS_STATE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_STATUS

Definition at line 104 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_DONE   (_DMA_STATUS_STATE_DONE << 4)

Shifted mode DONE for DMA_STATUS

Definition at line 114 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_IDLE   (_DMA_STATUS_STATE_IDLE << 4)

Shifted mode IDLE for DMA_STATUS

Definition at line 105 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_PERSCATTRANS   (_DMA_STATUS_STATE_PERSCATTRANS << 4)

Shifted mode PERSCATTRANS for DMA_STATUS

Definition at line 115 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_RDCHCTRLDATA   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)

Shifted mode RDCHCTRLDATA for DMA_STATUS

Definition at line 106 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_RDDSTENDPTR   (_DMA_STATUS_STATE_RDDSTENDPTR << 4)

Shifted mode RDDSTENDPTR for DMA_STATUS

Definition at line 108 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_RDSRCDATA   (_DMA_STATUS_STATE_RDSRCDATA << 4)

Shifted mode RDSRCDATA for DMA_STATUS

Definition at line 109 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_RDSRCENDPTR   (_DMA_STATUS_STATE_RDSRCENDPTR << 4)

Shifted mode RDSRCENDPTR for DMA_STATUS

Definition at line 107 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_STALLED   (_DMA_STATUS_STATE_STALLED << 4)

Shifted mode STALLED for DMA_STATUS

Definition at line 113 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_WAITREQCLR   (_DMA_STATUS_STATE_WAITREQCLR << 4)

Shifted mode WAITREQCLR for DMA_STATUS

Definition at line 111 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_WRCHCTRLDATA   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)

Shifted mode WRCHCTRLDATA for DMA_STATUS

Definition at line 112 of file efm32zg_dma.h.

#define DMA_STATUS_STATE_WRDSTDATA   (_DMA_STATUS_STATE_WRDSTDATA << 4)

Shifted mode WRDSTDATA for DMA_STATUS

Definition at line 110 of file efm32zg_dma.h.