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#define | ICM20648_ACCEL_BW_111HZ ( ( 0x02 << ICM20648_SHIFT_ACCEL_DLPCFG ) | ICM20648_BIT_ACCEL_FCHOICE ) |
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#define | ICM20648_ACCEL_BW_1210HZ ( 0x00 << ICM20648_SHIFT_ACCEL_DLPCFG ) |
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#define | ICM20648_ACCEL_BW_12HZ ( ( 0x05 << ICM20648_SHIFT_ACCEL_DLPCFG ) | ICM20648_BIT_ACCEL_FCHOICE ) |
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#define | ICM20648_ACCEL_BW_246HZ ( ( 0x00 << ICM20648_SHIFT_ACCEL_DLPCFG ) | ICM20648_BIT_ACCEL_FCHOICE ) |
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#define | ICM20648_ACCEL_BW_24HZ ( ( 0x04 << ICM20648_SHIFT_ACCEL_DLPCFG ) | ICM20648_BIT_ACCEL_FCHOICE ) |
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#define | ICM20648_ACCEL_BW_470HZ ( ( 0x07 << ICM20648_SHIFT_ACCEL_DLPCFG ) | ICM20648_BIT_ACCEL_FCHOICE ) |
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#define | ICM20648_ACCEL_BW_50HZ ( ( 0x03 << ICM20648_SHIFT_ACCEL_DLPCFG ) | ICM20648_BIT_ACCEL_FCHOICE ) |
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#define | ICM20648_ACCEL_BW_6HZ ( ( 0x06 << ICM20648_SHIFT_ACCEL_DLPCFG ) | ICM20648_BIT_ACCEL_FCHOICE ) |
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#define | ICM20648_ACCEL_FULLSCALE_16G ( 0x03 << ICM20648_SHIFT_ACCEL_FS ) |
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#define | ICM20648_ACCEL_FULLSCALE_2G ( 0x00 << ICM20648_SHIFT_ACCEL_FS ) |
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#define | ICM20648_ACCEL_FULLSCALE_4G ( 0x01 << ICM20648_SHIFT_ACCEL_FS ) |
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#define | ICM20648_ACCEL_FULLSCALE_8G ( 0x02 << ICM20648_SHIFT_ACCEL_FS ) |
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#define | ICM20648_BANK_0 ( 0 << 7 ) |
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#define | ICM20648_BANK_1 ( 1 << 7 ) |
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#define | ICM20648_BANK_2 ( 2 << 7 ) |
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#define | ICM20648_BANK_3 ( 3 << 7 ) |
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#define | ICM20648_BIT_ACCEL_CTEN 0x1C |
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#define | ICM20648_BIT_ACCEL_CYCLE 0x20 |
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#define | ICM20648_BIT_ACCEL_FCHOICE 0x01 |
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#define | ICM20648_BIT_ACCEL_FIFO_EN 0x10 |
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#define | ICM20648_BIT_ACCEL_INTEL_EN 0x02 |
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#define | ICM20648_BIT_ACCEL_INTEL_MODE 0x01 |
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#define | ICM20648_BIT_CLK_PLL 0x01 |
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#define | ICM20648_BIT_DIAMOND_DMP_RST 0x04 |
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#define | ICM20648_BIT_DMP_EN 0x80 |
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#define | ICM20648_BIT_DMP_RST 0x08 |
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#define | ICM20648_BIT_FIFO_EN 0x40 |
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#define | ICM20648_BIT_FIFO_OVERFLOW_EN_0 0x01 |
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#define | ICM20648_BIT_GYRO_CTEN 0x38 |
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#define | ICM20648_BIT_GYRO_CYCLE 0x10 |
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#define | ICM20648_BIT_GYRO_FCHOICE 0x01 |
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#define | ICM20648_BIT_H_RESET 0x80 |
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#define | ICM20648_BIT_I2C_BYTE_SW 0x40 |
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#define | ICM20648_BIT_I2C_GRP 0x10 |
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#define | ICM20648_BIT_I2C_IF_DIS 0x10 |
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#define | ICM20648_BIT_I2C_MST_CYCLE 0x40 |
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#define | ICM20648_BIT_I2C_MST_EN 0x20 |
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#define | ICM20648_BIT_I2C_MST_P_NSR 0x10 |
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#define | ICM20648_BIT_I2C_READ 0x80 |
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#define | ICM20648_BIT_I2C_REG_DIS 0x20 |
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#define | ICM20648_BIT_I2C_SLV_EN 0x80 |
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#define | ICM20648_BIT_INT_ACTL 0x80 |
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#define | ICM20648_BIT_INT_LATCH_EN 0x20 |
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#define | ICM20648_BIT_INT_OPEN 0x40 |
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#define | ICM20648_BIT_LP_EN 0x20 |
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#define | ICM20648_BIT_MULTI_FIFO_CFG 0x01 |
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#define | ICM20648_BIT_PLL_RDY 0x04 |
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#define | ICM20648_BIT_PWR_ACCEL_STBY 0x38 |
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#define | ICM20648_BIT_PWR_ALL_OFF 0x7F |
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#define | ICM20648_BIT_PWR_GYRO_STBY 0x07 |
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#define | ICM20648_BIT_RAW_DATA_0_RDY 0x01 |
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#define | ICM20648_BIT_RAW_DATA_0_RDY_EN 0x01 |
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#define | ICM20648_BIT_RAW_DATA_0_RDY_INT 0x01 |
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#define | ICM20648_BIT_SINGLE_FIFO_CFG 0x00 |
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#define | ICM20648_BIT_SLEEP 0x40 |
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#define | ICM20648_BIT_SLV0_DLY_EN 0x01 |
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#define | ICM20648_BIT_SLV1_DLY_EN 0x02 |
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#define | ICM20648_BIT_SLV2_DLY_EN 0x04 |
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#define | ICM20648_BIT_SLV3_DLY_EN 0x08 |
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#define | ICM20648_BIT_TEMP_DIS 0x08 |
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#define | ICM20648_BIT_WOM_INT 0x08 |
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#define | ICM20648_BIT_WOM_INT_EN 0x08 |
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#define | ICM20648_BITS_GYRO_FIFO_EN 0x0E |
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#define | ICM20648_DEVICE_ID 0xE0 |
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#define | ICM20648_ERROR_INVALID_DEVICE_ID 0x0001 |
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#define | ICM20648_GYRO_BW_120HZ ( ( 0x02 << ICM20648_SHIFT_GYRO_DLPCFG ) | ICM20648_BIT_GYRO_FCHOICE ) |
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#define | ICM20648_GYRO_BW_12100HZ ( 0x00 << ICM20648_SHIFT_GYRO_DLPCFG ) |
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#define | ICM20648_GYRO_BW_12HZ ( ( 0x05 << ICM20648_SHIFT_GYRO_DLPCFG ) | ICM20648_BIT_GYRO_FCHOICE ) |
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#define | ICM20648_GYRO_BW_150HZ ( ( 0x01 << ICM20648_SHIFT_GYRO_DLPCFG ) | ICM20648_BIT_GYRO_FCHOICE ) |
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#define | ICM20648_GYRO_BW_200HZ ( ( 0x00 << ICM20648_SHIFT_GYRO_DLPCFG ) | ICM20648_BIT_GYRO_FCHOICE ) |
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#define | ICM20648_GYRO_BW_24HZ ( ( 0x04 << ICM20648_SHIFT_GYRO_DLPCFG ) | ICM20648_BIT_GYRO_FCHOICE ) |
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#define | ICM20648_GYRO_BW_360HZ ( ( 0x07 << ICM20648_SHIFT_GYRO_DLPCFG ) | ICM20648_BIT_GYRO_FCHOICE ) |
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#define | ICM20648_GYRO_BW_51HZ ( ( 0x03 << ICM20648_SHIFT_GYRO_DLPCFG ) | ICM20648_BIT_GYRO_FCHOICE ) |
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#define | ICM20648_GYRO_BW_6HZ ( ( 0x06 << ICM20648_SHIFT_GYRO_DLPCFG ) | ICM20648_BIT_GYRO_FCHOICE ) |
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#define | ICM20648_GYRO_FULLSCALE_1000DPS ( 0x02 << ICM20648_SHIFT_GYRO_FS_SEL ) |
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#define | ICM20648_GYRO_FULLSCALE_2000DPS ( 0x03 << ICM20648_SHIFT_GYRO_FS_SEL ) |
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#define | ICM20648_GYRO_FULLSCALE_250DPS ( 0x00 << ICM20648_SHIFT_GYRO_FS_SEL ) |
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#define | ICM20648_GYRO_FULLSCALE_500DPS ( 0x01 << ICM20648_SHIFT_GYRO_FS_SEL ) |
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#define | ICM20648_MASK_ACCEL_BW 0x39 |
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#define | ICM20648_MASK_ACCEL_FULLSCALE 0x06 |
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#define | ICM20648_MASK_GYRO_BW 0x39 |
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#define | ICM20648_MASK_GYRO_FULLSCALE 0x06 |
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#define | ICM20648_OK 0x0000 |
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#define | ICM20648_REG_ACCEL_CONFIG ( ICM20648_BANK_2 | 0x14 ) |
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#define | ICM20648_REG_ACCEL_CONFIG_2 ( ICM20648_BANK_2 | 0x15 ) |
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#define | ICM20648_REG_ACCEL_INTEL_CTRL ( ICM20648_BANK_2 | 0x12 ) |
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#define | ICM20648_REG_ACCEL_SMPLRT_DIV_1 ( ICM20648_BANK_2 | 0x10 ) |
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#define | ICM20648_REG_ACCEL_SMPLRT_DIV_2 ( ICM20648_BANK_2 | 0x11 ) |
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#define | ICM20648_REG_ACCEL_WOM_THR ( ICM20648_BANK_2 | 0x13 ) |
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#define | ICM20648_REG_ACCEL_XOUT_H_SH ( ICM20648_BANK_0 | 0x2D ) |
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#define | ICM20648_REG_ACCEL_XOUT_L_SH ( ICM20648_BANK_0 | 0x2E ) |
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#define | ICM20648_REG_ACCEL_YOUT_H_SH ( ICM20648_BANK_0 | 0x2F ) |
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#define | ICM20648_REG_ACCEL_YOUT_L_SH ( ICM20648_BANK_0 | 0x30 ) |
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#define | ICM20648_REG_ACCEL_ZOUT_H_SH ( ICM20648_BANK_0 | 0x31 ) |
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#define | ICM20648_REG_ACCEL_ZOUT_L_SH ( ICM20648_BANK_0 | 0x32 ) |
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#define | ICM20648_REG_BANK_SEL 0x7F |
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#define | ICM20648_REG_DATA_RDY_STATUS ( ICM20648_BANK_0 | 0x74 ) |
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#define | ICM20648_REG_FIFO_CFG ( ICM20648_BANK_0 | 0x76 ) |
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#define | ICM20648_REG_FIFO_COUNT_H ( ICM20648_BANK_0 | 0x70 ) |
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#define | ICM20648_REG_FIFO_COUNT_L ( ICM20648_BANK_0 | 0x71 ) |
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#define | ICM20648_REG_FIFO_EN_1 ( ICM20648_BANK_0 | 0x66 ) |
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#define | ICM20648_REG_FIFO_EN_2 ( ICM20648_BANK_0 | 0x67 ) |
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#define | ICM20648_REG_FIFO_MODE ( ICM20648_BANK_0 | 0x69 ) |
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#define | ICM20648_REG_FIFO_R_W ( ICM20648_BANK_0 | 0x72 ) |
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#define | ICM20648_REG_FIFO_RST ( ICM20648_BANK_0 | 0x68 ) |
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#define | ICM20648_REG_GYRO_CONFIG_1 ( ICM20648_BANK_2 | 0x01 ) |
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#define | ICM20648_REG_GYRO_CONFIG_2 ( ICM20648_BANK_2 | 0x02 ) |
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#define | ICM20648_REG_GYRO_SMPLRT_DIV ( ICM20648_BANK_2 | 0x00 ) |
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#define | ICM20648_REG_GYRO_XOUT_H_SH ( ICM20648_BANK_0 | 0x33 ) |
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#define | ICM20648_REG_GYRO_XOUT_L_SH ( ICM20648_BANK_0 | 0x34 ) |
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#define | ICM20648_REG_GYRO_YOUT_H_SH ( ICM20648_BANK_0 | 0x35 ) |
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#define | ICM20648_REG_GYRO_YOUT_L_SH ( ICM20648_BANK_0 | 0x36 ) |
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#define | ICM20648_REG_GYRO_ZOUT_H_SH ( ICM20648_BANK_0 | 0x37 ) |
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#define | ICM20648_REG_GYRO_ZOUT_L_SH ( ICM20648_BANK_0 | 0x38 ) |
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#define | ICM20648_REG_I2C_MST_CTRL ( ICM20648_BANK_3 | 0x01 ) |
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#define | ICM20648_REG_I2C_MST_DELAY_CTRL ( ICM20648_BANK_3 | 0x02 ) |
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#define | ICM20648_REG_I2C_MST_ODR_CONFIG ( ICM20648_BANK_3 | 0x00 ) |
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#define | ICM20648_REG_I2C_SLV0_ADDR ( ICM20648_BANK_3 | 0x03 ) |
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#define | ICM20648_REG_I2C_SLV0_CTRL ( ICM20648_BANK_3 | 0x05 ) |
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#define | ICM20648_REG_I2C_SLV0_DO ( ICM20648_BANK_3 | 0x06 ) |
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#define | ICM20648_REG_I2C_SLV0_REG ( ICM20648_BANK_3 | 0x04 ) |
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#define | ICM20648_REG_I2C_SLV1_ADDR ( ICM20648_BANK_3 | 0x07 ) |
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#define | ICM20648_REG_I2C_SLV1_CTRL ( ICM20648_BANK_3 | 0x09 ) |
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#define | ICM20648_REG_I2C_SLV1_DO ( ICM20648_BANK_3 | 0x0A ) |
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#define | ICM20648_REG_I2C_SLV1_REG ( ICM20648_BANK_3 | 0x08 ) |
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#define | ICM20648_REG_I2C_SLV2_ADDR ( ICM20648_BANK_3 | 0x0B ) |
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#define | ICM20648_REG_I2C_SLV2_CTRL ( ICM20648_BANK_3 | 0x0D ) |
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#define | ICM20648_REG_I2C_SLV2_DO ( ICM20648_BANK_3 | 0x0E ) |
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#define | ICM20648_REG_I2C_SLV2_REG ( ICM20648_BANK_3 | 0x0C ) |
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#define | ICM20648_REG_I2C_SLV3_ADDR ( ICM20648_BANK_3 | 0x0F ) |
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#define | ICM20648_REG_I2C_SLV3_CTRL ( ICM20648_BANK_3 | 0x11 ) |
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#define | ICM20648_REG_I2C_SLV3_DO ( ICM20648_BANK_3 | 0x12 ) |
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#define | ICM20648_REG_I2C_SLV3_REG ( ICM20648_BANK_3 | 0x10 ) |
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#define | ICM20648_REG_I2C_SLV4_ADDR ( ICM20648_BANK_3 | 0x13 ) |
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#define | ICM20648_REG_I2C_SLV4_CTRL ( ICM20648_BANK_3 | 0x15 ) |
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#define | ICM20648_REG_I2C_SLV4_DI ( ICM20648_BANK_3 | 0x17 ) |
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#define | ICM20648_REG_I2C_SLV4_DO ( ICM20648_BANK_3 | 0x16 ) |
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#define | ICM20648_REG_I2C_SLV4_REG ( ICM20648_BANK_3 | 0x14 ) |
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#define | ICM20648_REG_INT_ENABLE ( ICM20648_BANK_0 | 0x10 ) |
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#define | ICM20648_REG_INT_ENABLE_1 ( ICM20648_BANK_0 | 0x11 ) |
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#define | ICM20648_REG_INT_ENABLE_2 ( ICM20648_BANK_0 | 0x12 ) |
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#define | ICM20648_REG_INT_ENABLE_3 ( ICM20648_BANK_0 | 0x13 ) |
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#define | ICM20648_REG_INT_PIN_CFG ( ICM20648_BANK_0 | 0x0F ) |
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#define | ICM20648_REG_INT_STATUS ( ICM20648_BANK_0 | 0x19 ) |
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#define | ICM20648_REG_INT_STATUS_1 ( ICM20648_BANK_0 | 0x1A ) |
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#define | ICM20648_REG_INT_STATUS_2 ( ICM20648_BANK_0 | 0x1B ) |
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#define | ICM20648_REG_LP_CONFIG ( ICM20648_BANK_0 | 0x05 ) |
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#define | ICM20648_REG_ODR_ALIGN_EN ( ICM20648_BANK_2 | 0x09 ) |
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#define | ICM20648_REG_PWR_MGMT_1 ( ICM20648_BANK_0 | 0x06 ) |
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#define | ICM20648_REG_PWR_MGMT_2 ( ICM20648_BANK_0 | 0x07 ) |
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#define | ICM20648_REG_TEMP_CONFIG ( ICM20648_BANK_0 | 0x53 ) |
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#define | ICM20648_REG_TEMPERATURE_H ( ICM20648_BANK_0 | 0x39 ) |
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#define | ICM20648_REG_TEMPERATURE_L ( ICM20648_BANK_0 | 0x3A ) |
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#define | ICM20648_REG_TIMEBASE_CORR_PLL ( ICM20648_BANK_1 | 0x28 ) |
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#define | ICM20648_REG_USER_CTRL ( ICM20648_BANK_0 | 0x03 ) |
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#define | ICM20648_REG_WHO_AM_I ( ICM20648_BANK_0 | 0x00 ) |
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#define | ICM20648_REG_XA_OFFSET_H ( ICM20648_BANK_1 | 0x14 ) |
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#define | ICM20648_REG_XA_OFFSET_L ( ICM20648_BANK_1 | 0x15 ) |
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#define | ICM20648_REG_XG_OFFS_USRH ( ICM20648_BANK_2 | 0x03 ) |
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#define | ICM20648_REG_XG_OFFS_USRL ( ICM20648_BANK_2 | 0x04 ) |
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#define | ICM20648_REG_YA_OFFSET_H ( ICM20648_BANK_1 | 0x17 ) |
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#define | ICM20648_REG_YA_OFFSET_L ( ICM20648_BANK_1 | 0x18 ) |
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#define | ICM20648_REG_YG_OFFS_USRH ( ICM20648_BANK_2 | 0x05 ) |
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#define | ICM20648_REG_YG_OFFS_USRL ( ICM20648_BANK_2 | 0x06 ) |
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#define | ICM20648_REG_ZA_OFFSET_H ( ICM20648_BANK_1 | 0x1A ) |
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#define | ICM20648_REG_ZA_OFFSET_L ( ICM20648_BANK_1 | 0x1B ) |
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#define | ICM20648_REG_ZG_OFFS_USRH ( ICM20648_BANK_2 | 0x07 ) |
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#define | ICM20648_REG_ZG_OFFS_USRL ( ICM20648_BANK_2 | 0x08 ) |
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#define | ICM20648_SHIFT_ACCEL_DLPCFG 3 |
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#define | ICM20648_SHIFT_ACCEL_FS 1 |
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#define | ICM20648_SHIFT_GYRO_DLPCFG 3 |
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#define | ICM20648_SHIFT_GYRO_FS_SEL 1 |
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