EFM32 Happy Gecko Software Documentation  efm32hg-doc-5.1.2
em_timer.h
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1 /***************************************************************************/
33 #ifndef EM_TIMER_H
34 #define EM_TIMER_H
35 
36 #include "em_device.h"
37 #if defined(TIMER_COUNT) && (TIMER_COUNT > 0)
38 
39 #include <stdbool.h>
40 #include "em_assert.h"
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 /***************************************************************************/
51 /***************************************************************************/
56 /*******************************************************************************
57  ******************************* DEFINES ***********************************
58  ******************************************************************************/
59 
63 #define TIMER_REF_VALID(ref) TIMER_Valid(ref)
64 
66 #if defined(_SILICON_LABS_32B_SERIES_0)
67 #define TIMER_CH_VALID(ch) ((ch) < 3)
68 #elif defined(_SILICON_LABS_32B_SERIES_1)
69 #define TIMER_CH_VALID(ch) ((ch) < 4)
70 #else
71 #error "Unknown device. Undefined number of channels."
72 #endif
73 
76 /*******************************************************************************
77  ******************************** ENUMS ************************************
78  ******************************************************************************/
79 
81 typedef enum
82 {
88 
89 
91 typedef enum
92 {
95 
98 
105 
106 
108 typedef enum
109 {
112 
115 
118 
122 
123 
125 typedef enum
126 {
142 
143 
145 typedef enum
146 {
149 
152 
155 
159 
160 
162 typedef enum
163 {
169 
170 
172 typedef enum
173 {
176 
179 
182 
186 
187 
189 typedef enum
190 {
203 
204 
206 typedef enum
207 {
212 #if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH4)
214 #endif
215 #if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH5)
217 #endif
218 #if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH6)
219  timerPRSSELCh6 = _TIMER_CC_CTRL_PRSSEL_PRSCH6,
220 #endif
221 #if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH7)
222  timerPRSSELCh7 = _TIMER_CC_CTRL_PRSSEL_PRSCH7,
223 #endif
224 #if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH8)
225  timerPRSSELCh8 = _TIMER_CC_CTRL_PRSSEL_PRSCH8,
226 #endif
227 #if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH9)
228  timerPRSSELCh9 = _TIMER_CC_CTRL_PRSSEL_PRSCH9,
229 #endif
230 #if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH10)
231  timerPRSSELCh10 = _TIMER_CC_CTRL_PRSSEL_PRSCH10,
232 #endif
233 #if defined(_TIMER_CC_CTRL_PRSSEL_PRSCH11)
234  timerPRSSELCh11 = _TIMER_CC_CTRL_PRSSEL_PRSCH11,
235 #endif
237 
238 #if defined(_TIMER_DTFC_DTFA_NONE)
239 
240 typedef enum
241 {
247 #endif
248 
249 /*******************************************************************************
250  ******************************* STRUCTS ***********************************
251  ******************************************************************************/
252 
254 typedef struct
255 {
257  bool enable;
258 
260  bool debugRun;
261 
264 
267 
268 #if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)
269 
270  bool count2x;
271 
274  bool ati;
275 #endif
276 
279 
282 
285 
287  bool dmaClrAct;
288 
291 
293  bool oneShot;
294 
296  bool sync;
298 
300 #if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI)
301 #define TIMER_INIT_DEFAULT \
302 { \
303  true, /* Enable timer when init complete. */ \
304  false, /* Stop counter during debug halt. */ \
305  timerPrescale1, /* No prescaling. */ \
306  timerClkSelHFPerClk, /* Select HFPER clock. */ \
307  false, /* Not 2x count mode. */ \
308  false, /* No ATI. */ \
309  timerInputActionNone, /* No action on falling input edge. */ \
310  timerInputActionNone, /* No action on rising input edge. */ \
311  timerModeUp, /* Up-counting. */ \
312  false, /* Do not clear DMA requests when DMA channel is active. */ \
313  false, /* Select X2 quadrature decode mode (if used). */ \
314  false, /* Disable one shot. */ \
315  false /* Not started/stopped/reloaded by other timers. */ \
316 }
317 #else
318 #define TIMER_INIT_DEFAULT \
319 { \
320  true, /* Enable timer when init complete. */ \
321  false, /* Stop counter during debug halt. */ \
322  timerPrescale1, /* No prescaling. */ \
323  timerClkSelHFPerClk, /* Select HFPER clock. */ \
324  timerInputActionNone, /* No action on falling input edge. */ \
325  timerInputActionNone, /* No action on rising input edge. */ \
326  timerModeUp, /* Up-counting. */ \
327  false, /* Do not clear DMA requests when DMA channel is active. */ \
328  false, /* Select X2 quadrature decode mode (if used). */ \
329  false, /* Disable one shot. */ \
330  false /* Not started/stopped/reloaded by other timers. */ \
331 }
332 #endif
333 
335 typedef struct
336 {
339 
342 
348 
351 
354 
357 
360 
362  bool filter;
363 
365  bool prsInput;
366 
374  bool coist;
375 
377  bool outInvert;
379 
381 #define TIMER_INITCC_DEFAULT \
382 { \
383  timerEventEveryEdge, /* Event on every capture. */ \
384  timerEdgeRising, /* Input capture edge on rising edge. */ \
385  timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
386  timerOutputActionNone, /* No action on underflow. */ \
387  timerOutputActionNone, /* No action on overflow. */ \
388  timerOutputActionNone, /* No action on match. */ \
389  timerCCModeOff, /* Disable compare/capture channel. */ \
390  false, /* Disable filter. */ \
391  false, /* Select TIMERnCCx input. */ \
392  false, /* Clear output when counter disabled. */ \
393  false /* Do not invert output. */ \
394 }
395 
396 #if defined(_TIMER_DTCTRL_MASK)
397 
398 typedef struct
399 {
401  bool enable;
402 
405 
408 
411 
414 
418 
421 
423  unsigned int riseTime;
424 
426  unsigned int fallTime;
427 
433 
436 
439 
442 
445 
448 
451 
454 
456 
457 
459 #define TIMER_INITDTI_DEFAULT \
460 { \
461  true, /* Enable the DTI. */ \
462  false, /* CC[0|1|2] outputs are active high. */ \
463  false, /* CDTI[0|1|2] outputs are not inverted. */ \
464  false, /* No auto restart when debugger exits. */ \
465  false, /* No PRS source selected. */ \
466  timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
467  timerPrescale1, /* No prescaling. */ \
468  0, /* No rise time. */ \
469  0, /* No fall time. */ \
470  TIMER_DTOGEN_DTOGCC0EN|TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0 */\
471  true, /* Enable core lockup as fault source */ \
472  true, /* Enable debugger as fault source */ \
473  false, /* Disable PRS fault source 0 */ \
474  timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
475  false, /* Disable PRS fault source 1 */ \
476  timerPRSSELCh0, /* Not used by default, select PRS channel 0. */ \
477  timerDtiFaultActionInactive, /* No fault action. */ \
478 }
479 #endif /* _TIMER_DTCTRL_MASK */
480 
481 
482 /*******************************************************************************
483  ***************************** PROTOTYPES **********************************
484  ******************************************************************************/
485 
486 
487 /***************************************************************************/
497 __STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref)
498 {
499  return (ref == TIMER0)
500 #if defined(TIMER1)
501  || (ref == TIMER1)
502 #endif
503 #if defined(TIMER2)
504  || (ref == TIMER2)
505 #endif
506 #if defined(TIMER3)
507  || (ref == TIMER3)
508 #endif
509 #if defined(WTIMER0)
510  || (ref == WTIMER0)
511 #endif
512 #if defined(WTIMER1)
513  || (ref == WTIMER1)
514 #endif
515  ;
516 }
517 
518 /***************************************************************************/
529 __STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref)
530 {
531 #if defined(WTIMER_PRESENT)
532  if ((ref == WTIMER0)
533 #if defined(WTIMER1)
534  || (ref == WTIMER1)
535 #endif
536  )
537  {
538  return 0xFFFFFFFFUL;
539  }
540 #else
541  (void) ref;
542 #endif
543  return 0xFFFFUL;
544 }
545 
546 /***************************************************************************/
560 __STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch)
561 {
562  return timer->CC[ch].CCV;
563 }
564 
565 
566 /***************************************************************************/
585 __STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer,
586  unsigned int ch,
587  uint32_t val)
588 {
589  EFM_ASSERT(val <= TIMER_MaxCount(timer));
590  timer->CC[ch].CCVB = val;
591 }
592 
593 
594 /***************************************************************************/
608 __STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer,
609  unsigned int ch,
610  uint32_t val)
611 {
612  EFM_ASSERT(val <= TIMER_MaxCount(timer));
613  timer->CC[ch].CCV = val;
614 }
615 
616 
617 /***************************************************************************/
627 __STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer)
628 {
629  return timer->CNT;
630 }
631 
632 
633 /***************************************************************************/
643 __STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val)
644 {
645  EFM_ASSERT(val <= TIMER_MaxCount(timer));
646  timer->CNT = val;
647 }
648 
649 
650 /***************************************************************************/
660 __STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable)
661 {
662  EFM_ASSERT(TIMER_REF_VALID(timer));
663 
664  if (enable)
665  {
666  timer->CMD = TIMER_CMD_START;
667  }
668  else
669  {
670  timer->CMD = TIMER_CMD_STOP;
671  }
672 }
673 
674 
675 void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init);
676 void TIMER_InitCC(TIMER_TypeDef *timer,
677  unsigned int ch,
678  const TIMER_InitCC_TypeDef *init);
679 
680 #if defined(_TIMER_DTCTRL_MASK)
681 void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init);
682 
683 /***************************************************************************/
693 __STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable)
694 {
695  EFM_ASSERT(TIMER0 == timer);
696 
697  if (enable)
698  {
699  timer->DTCTRL |= TIMER_DTCTRL_DTEN;
700  }
701  else
702  {
703  timer->DTCTRL &= ~TIMER_DTCTRL_DTEN;
704  }
705 }
706 
707 
708 /***************************************************************************/
722 __STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer)
723 {
724  EFM_ASSERT(TIMER0 == timer);
725  return timer->DTFAULT;
726 }
727 
728 
729 /***************************************************************************/
740 __STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags)
741 
742 {
743  EFM_ASSERT(TIMER0 == timer);
744  timer->DTFAULTC = flags;
745 }
746 #endif /* _TIMER_DTCTRL_MASK */
747 
748 
749 /***************************************************************************/
760 __STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags)
761 {
762  timer->IFC = flags;
763 }
764 
765 
766 /***************************************************************************/
777 __STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags)
778 {
779  timer->IEN &= ~flags;
780 }
781 
782 
783 /***************************************************************************/
799 __STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags)
800 {
801  timer->IEN |= flags;
802 }
803 
804 
805 /***************************************************************************/
819 __STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer)
820 {
821  return timer->IF;
822 }
823 
824 
825 /***************************************************************************/
844 __STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer)
845 {
846  uint32_t ien;
847 
848  /* Store TIMER->IEN in temporary variable in order to define explicit order
849  * of volatile accesses. */
850  ien = timer->IEN;
851 
852  /* Bitwise AND of pending and enabled interrupts */
853  return timer->IF & ien;
854 }
855 
856 
857 /***************************************************************************/
868 __STATIC_INLINE void TIMER_IntSet(TIMER_TypeDef *timer, uint32_t flags)
869 {
870  timer->IFS = flags;
871 }
872 
873 #if defined(_TIMER_DTLOCK_LOCKKEY_LOCK)
874 /***************************************************************************/
890 __STATIC_INLINE void TIMER_Lock(TIMER_TypeDef *timer)
891 {
892  EFM_ASSERT(TIMER0 == timer);
893 
895 }
896 #endif
897 
898 void TIMER_Reset(TIMER_TypeDef *timer);
899 
900 /***************************************************************************/
915 __STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val)
916 {
917  EFM_ASSERT(val <= TIMER_MaxCount(timer));
918  timer->TOPB = val;
919 }
920 
921 
922 /***************************************************************************/
932 __STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer)
933 {
934  return timer->TOP;
935 }
936 
937 
938 /***************************************************************************/
948 __STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val)
949 {
950  EFM_ASSERT(val <= TIMER_MaxCount(timer));
951  timer->TOP = val;
952 }
953 
954 
955 #if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK)
956 /***************************************************************************/
963 __STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer)
964 {
965  EFM_ASSERT(TIMER0 == timer);
966 
968 }
969 #endif
970 
974 #ifdef __cplusplus
975 }
976 #endif
977 
978 #endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */
979 #endif /* EM_TIMER_H */
uint32_t outputsEnableMask
Definition: em_timer.h:432
__STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags)
Disable one or more TIMER interrupts.
Definition: em_timer.h:777
__STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val)
Set top value for timer.
Definition: em_timer.h:948
__IOM uint32_t TOP
Definition: efm32hg_timer.h:50
#define _TIMER_CTRL_MODE_DOWN
Definition: efm32hg_timer.h:80
TIMER_CC_TypeDef CC[3]
Definition: efm32hg_timer.h:56
#define _TIMER_CTRL_PRESC_DIV64
#define _TIMER_CTRL_PRESC_DIV2
#define _TIMER_CC_CTRL_PRSSEL_PRSCH4
#define _TIMER_CTRL_CLKSEL_TIMEROUF
TIMER_ClkSel_TypeDef clkSel
Definition: em_timer.h:266
bool enableFaultSourcePrsSel0
Definition: em_timer.h:441
__IM uint32_t IF
Definition: efm32hg_timer.h:47
#define _TIMER_CTRL_FALLA_RELOADSTART
TIMER_OutputAction_TypeDef cufoa
Definition: em_timer.h:350
#define _TIMER_CC_CTRL_PRSSEL_PRSCH5
Emlib peripheral API "assert" implementation.
TIMER_PRSSEL_TypeDef faultSourcePrsSel0
Definition: em_timer.h:444
void TIMER_Reset(TIMER_TypeDef *timer)
Reset TIMER to same state as after a HW reset.
Definition: em_timer.c:218
TIMER_InputAction_TypeDef fallAction
Definition: em_timer.h:278
__STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable)
Start/stop TIMER.
Definition: em_timer.h:660
#define TIMER_DTCTRL_DTEN
__IOM uint32_t TOPB
Definition: efm32hg_timer.h:51
__STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val)
Set TIMER counter value.
Definition: em_timer.h:643
#define _TIMER_CTRL_MODE_UPDOWN
Definition: efm32hg_timer.h:81
__OM uint32_t DTFAULTC
Definition: efm32hg_timer.h:64
#define _TIMER_CTRL_PRESC_DIV1024
__IM uint32_t DTFAULT
Definition: efm32hg_timer.h:63
__STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags)
Clear one or more pending TIMER interrupts.
Definition: em_timer.h:760
TIMER_Event_TypeDef
Definition: em_timer.h:125
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
TIMER_PRSSEL_TypeDef
Definition: em_timer.h:206
#define _TIMER_CC_CTRL_MODE_OFF
TIMER_Mode_TypeDef mode
Definition: em_timer.h:284
__STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable)
Enable or disable DTI unit.
Definition: em_timer.h:693
#define _TIMER_CC_CTRL_ICEDGE_FALLING
TIMER_CCMode_TypeDef mode
Definition: em_timer.h:359
#define _TIMER_CC_CTRL_CUFOA_CLEAR
void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init)
Initialize the TIMER DTI unit.
Definition: em_timer.c:163
#define _TIMER_CC_CTRL_MODE_PWM
#define _TIMER_CC_CTRL_ICEVCTRL_RISING
__STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags)
Enable one or more TIMER interrupts.
Definition: em_timer.h:799
#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE
#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE
#define TIMER0
#define _TIMER_CTRL_CLKSEL_PRESCHFPERCLK
#define _TIMER_CTRL_PRESC_DIV16
__STATIC_INLINE void TIMER_IntSet(TIMER_TypeDef *timer, uint32_t flags)
Set one or more pending TIMER interrupts from SW.
Definition: em_timer.h:868
TIMER_PRSSEL_TypeDef prsSel
Definition: em_timer.h:347
__STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val)
Set top value buffer for timer.
Definition: em_timer.h:915
#define _TIMER_CTRL_PRESC_DIV32
#define _TIMER_CTRL_PRESC_DIV256
#define TIMER_CMD_START
TIMER_CCMode_TypeDef
Definition: em_timer.h:81
TIMER_Edge_TypeDef edge
Definition: em_timer.h:341
#define TIMER_DTLOCK_LOCKKEY_UNLOCK
#define _TIMER_CC_CTRL_MODE_INPUTCAPTURE
#define _TIMER_CTRL_FALLA_STOP
__STATIC_INLINE void TIMER_Lock(TIMER_TypeDef *timer)
Lock some of the TIMER registers in order to protect them from being modified.
Definition: em_timer.h:890
__IOM uint32_t DTCTRL
Definition: efm32hg_timer.h:59
#define _TIMER_DTFC_DTFA_CLEAR
TIMER_DtiFaultAction_TypeDef faultAction
Definition: em_timer.h:453
__STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer)
Get pending TIMER interrupt flags.
Definition: em_timer.h:819
__IOM uint32_t IFC
Definition: efm32hg_timer.h:49
TIMER_OutputAction_TypeDef
Definition: em_timer.h:172
#define _TIMER_CTRL_PRESC_DIV8
TIMER_PRSSEL_TypeDef faultSourcePrsSel1
Definition: em_timer.h:450
#define _TIMER_CC_CTRL_ICEDGE_BOTH
unsigned int riseTime
Definition: em_timer.h:423
TIMER_Event_TypeDef eventCtrl
Definition: em_timer.h:338
__IOM uint32_t CNT
Definition: efm32hg_timer.h:52
__IOM uint32_t CCV
#define _TIMER_CC_CTRL_ICEVCTRL_FALLING
#define TIMER2
#define _TIMER_CTRL_PRESC_DIV128
TIMER_Prescale_TypeDef prescale
Definition: em_timer.h:420
TIMER_ClkSel_TypeDef
Definition: em_timer.h:91
#define _TIMER_CC_CTRL_PRSSEL_PRSCH3
#define _TIMER_CC_CTRL_PRSSEL_PRSCH1
#define _TIMER_CC_CTRL_ICEDGE_RISING
#define _TIMER_DTFC_DTFA_TRISTATE
__STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val)
Set compare value for compare/capture channel when operating in compare or PWM mode.
Definition: em_timer.h:608
__IOM uint32_t CCVB
__STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer)
Get TIMER counter value.
Definition: em_timer.h:627
unsigned int fallTime
Definition: em_timer.h:426
__STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch)
Get capture value for compare/capture channel when operating in capture mode.
Definition: em_timer.h:560
TIMER_PRSSEL_TypeDef prsSel
Definition: em_timer.h:417
#define _TIMER_CTRL_FALLA_NONE
TIMER_Prescale_TypeDef prescale
Definition: em_timer.h:263
__STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref)
Validate the TIMER register block pointer.
Definition: em_timer.h:497
#define _TIMER_CTRL_MODE_QDEC
Definition: efm32hg_timer.h:82
#define _TIMER_CTRL_PRESC_DIV1
__STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref)
Get the Max count of the timer.
Definition: em_timer.h:529
#define _TIMER_CC_CTRL_CUFOA_SET
TIMER_OutputAction_TypeDef cofoa
Definition: em_timer.h:353
#define _TIMER_DTFC_DTFA_INACTIVE
__IOM uint32_t DTLOCK
Definition: efm32hg_timer.h:65
void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init)
Initialize TIMER.
Definition: em_timer.c:76
TIMER_DtiFaultAction_TypeDef
Definition: em_timer.h:240
#define _TIMER_CC_CTRL_PRSSEL_PRSCH0
__STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer)
Get top value setting for timer.
Definition: em_timer.h:932
#define _TIMER_CC_CTRL_CUFOA_TOGGLE
__IOM uint32_t CMD
Definition: efm32hg_timer.h:44
#define _TIMER_CTRL_MODE_UP
Definition: efm32hg_timer.h:79
TIMER_InputAction_TypeDef riseAction
Definition: em_timer.h:281
#define TIMER_CMD_STOP
#define _TIMER_CTRL_CLKSEL_CC1
__STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, unsigned int ch, uint32_t val)
Set compare value buffer for compare/capture channel when operating in compare or PWM mode...
Definition: em_timer.h:585
__IOM uint32_t IFS
Definition: efm32hg_timer.h:48
__STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer)
Get enabled and pending TIMER interrupt flags. Useful for handling more interrupt sources in the same...
Definition: em_timer.h:844
__STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags)
Clear DTI fault source flags.
Definition: em_timer.h:740
TIMER_Edge_TypeDef
Definition: em_timer.h:108
#define TIMER_DTLOCK_LOCKKEY_LOCK
bool enableFaultSourceCoreLockup
Definition: em_timer.h:435
bool enableFaultSourcePrsSel1
Definition: em_timer.h:447
TIMER_Mode_TypeDef
Definition: em_timer.h:162
#define _TIMER_CC_CTRL_ICEDGE_NONE
#define _TIMER_CTRL_PRESC_DIV4
#define _TIMER_CC_CTRL_PRSSEL_PRSCH2
#define _TIMER_CTRL_FALLA_START
void TIMER_InitCC(TIMER_TypeDef *timer, unsigned int ch, const TIMER_InitCC_TypeDef *init)
Initialize TIMER compare/capture channel.
Definition: em_timer.c:130
TIMER_OutputAction_TypeDef cmoa
Definition: em_timer.h:356
__STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer)
Get DTI fault source flags status.
Definition: em_timer.h:722
#define _TIMER_CC_CTRL_CUFOA_NONE
#define TIMER1
__IOM uint32_t IEN
Definition: efm32hg_timer.h:46
__STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer)
Unlock the TIMER so that writing to locked registers again is possible.
Definition: em_timer.h:963
#define _TIMER_DTFC_DTFA_NONE
#define _TIMER_CTRL_PRESC_DIV512
TIMER_InputAction_TypeDef
Definition: em_timer.h:145
#define _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE
TIMER_Prescale_TypeDef
Definition: em_timer.h:189
bool enableFaultSourceDebugger
Definition: em_timer.h:438