EFM32 Giant Gecko Software Documentation  efm32gg-doc-5.1.2
dmadrv.h
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1 /***************************************************************************/
16 #ifndef __SILICON_LABS_DMADRV_H__
17 #define __SILICON_LABS_DMADRV_H__
18 
19 #include "em_device.h"
20 #include "ecode.h"
21 
22 #if defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
23 #define EMDRV_DMADRV_UDMA
24 #define EMDRV_DMADRV_DMA_PRESENT
25 #include "em_dma.h"
26 #elif defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
27 #define EMDRV_DMADRV_LDMA
28 #define EMDRV_DMADRV_DMA_PRESENT
29 #include "em_ldma.h"
30 #else
31 #error "No valid DMA engine defined."
32 #endif
33 
34 #include "dmadrv_config.h"
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /***************************************************************************/
45 /***************************************************************************/
50 #define ECODE_EMDRV_DMADRV_OK ( ECODE_OK )
51 #define ECODE_EMDRV_DMADRV_PARAM_ERROR ( ECODE_EMDRV_DMADRV_BASE | 0x00000001 )
52 #define ECODE_EMDRV_DMADRV_NOT_INITIALIZED ( ECODE_EMDRV_DMADRV_BASE | 0x00000002 )
53 #define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED ( ECODE_EMDRV_DMADRV_BASE | 0x00000003 )
54 #define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED ( ECODE_EMDRV_DMADRV_BASE | 0x00000004 )
55 #define ECODE_EMDRV_DMADRV_IN_USE ( ECODE_EMDRV_DMADRV_BASE | 0x00000005 )
56 #define ECODE_EMDRV_DMADRV_ALREADY_FREED ( ECODE_EMDRV_DMADRV_BASE | 0x00000006 )
57 #define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED ( ECODE_EMDRV_DMADRV_BASE | 0x00000007 )
58 
59 /***************************************************************************/
80 typedef bool (*DMADRV_Callback_t)( unsigned int channel,
81  unsigned int sequenceNo,
82  void *userParam );
83 
84 #if defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
85 
87 #define DMADRV_MAX_XFER_COUNT ((int)((_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT) + 1))
88 
90 typedef enum
91 {
92  dmadrvPeripheralSignal_NONE = 0,
93  #if defined( DMAREQ_ADC0_SCAN )
94  dmadrvPeripheralSignal_ADC0_SCAN = DMAREQ_ADC0_SCAN,
95  #endif
96  #if defined( DMAREQ_ADC0_SINGLE )
97  dmadrvPeripheralSignal_ADC0_SINGLE = DMAREQ_ADC0_SINGLE,
98  #endif
99  #if defined( DMAREQ_AES_DATARD )
100  dmadrvPeripheralSignal_AES_DATARD = DMAREQ_AES_DATARD,
101  #endif
102  #if defined( DMAREQ_AES_DATAWR )
103  dmadrvPeripheralSignal_AES_DATAWR = DMAREQ_AES_DATAWR,
104  #endif
105  #if defined( DMAREQ_AES_KEYWR )
106  dmadrvPeripheralSignal_AES_KEYWR = DMAREQ_AES_KEYWR,
107  #endif
108  #if defined( DMAREQ_AES_XORDATAWR )
109  dmadrvPeripheralSignal_AES_XORDATAWR = DMAREQ_AES_XORDATAWR,
110  #endif
111  #if defined( DMAREQ_DAC0_CH0 )
112  dmadrvPeripheralSignal_DAC0_CH0 = DMAREQ_DAC0_CH0,
113  #endif
114  #if defined( DMAREQ_DAC0_CH1 )
115  dmadrvPeripheralSignal_DAC0_CH1 = DMAREQ_DAC0_CH1,
116  #endif
117  #if defined( DMAREQ_EBI_DDEMPTY )
118  dmadrvPeripheralSignal_EBI_DDEMPTY = DMAREQ_EBI_DDEMPTY,
119  #endif
120  #if defined( DMAREQ_EBI_PXL0EMPTY )
121  dmadrvPeripheralSignal_EBI_PXL0EMPTY = DMAREQ_EBI_PXL0EMPTY,
122  #endif
123  #if defined( DMAREQ_EBI_PXL1EMPTY )
124  dmadrvPeripheralSignal_EBI_PXL1EMPTY = DMAREQ_EBI_PXL1EMPTY,
125  #endif
126  #if defined( DMAREQ_EBI_PXLFULL )
127  dmadrvPeripheralSignal_EBI_PXLFULL = DMAREQ_EBI_PXLFULL,
128  #endif
129  #if defined( DMAREQ_I2C0_RXDATAV )
130  dmadrvPeripheralSignal_I2C0_RXDATAV = DMAREQ_I2C0_RXDATAV,
131  #endif
132  #if defined( DMAREQ_I2C0_TXBL )
133  dmadrvPeripheralSignal_I2C0_TXBL = DMAREQ_I2C0_TXBL,
134  #endif
135  #if defined( DMAREQ_I2C1_RXDATAV )
136  dmadrvPeripheralSignal_I2C1_RXDATAV = DMAREQ_I2C1_RXDATAV,
137  #endif
138  #if defined( DMAREQ_I2C1_TXBL )
139  dmadrvPeripheralSignal_I2C1_TXBL = DMAREQ_I2C1_TXBL,
140  #endif
141  #if defined( DMAREQ_LESENSE_BUFDATAV )
142  dmadrvPeripheralSignal_LESENSE_BUFDATAV = DMAREQ_LESENSE_BUFDATAV,
143  #endif
144  #if defined( DMAREQ_LEUART0_RXDATAV )
145  dmadrvPeripheralSignal_LEUART0_RXDATAV = DMAREQ_LEUART0_RXDATAV,
146  #endif
147  #if defined( DMAREQ_LEUART0_TXBL )
148  dmadrvPeripheralSignal_LEUART0_TXBL = DMAREQ_LEUART0_TXBL,
149  #endif
150  #if defined( DMAREQ_LEUART0_TXEMPTY )
151  dmadrvPeripheralSignal_LEUART0_TXEMPTY = DMAREQ_LEUART0_TXEMPTY,
152  #endif
153  #if defined( DMAREQ_LEUART1_RXDATAV )
154  dmadrvPeripheralSignal_LEUART1_RXDATAV = DMAREQ_LEUART1_RXDATAV,
155  #endif
156  #if defined( DMAREQ_LEUART1_TXBL )
157  dmadrvPeripheralSignal_LEUART1_TXBL = DMAREQ_LEUART1_TXBL,
158  #endif
159  #if defined( DMAREQ_LEUART1_TXEMPTY )
160  dmadrvPeripheralSignal_LEUART1_TXEMPTY = DMAREQ_LEUART1_TXEMPTY,
161  #endif
162  #if defined( DMAREQ_MSC_WDATA )
163  dmadrvPeripheralSignal_MSC_WDATA = DMAREQ_MSC_WDATA,
164  #endif
165  #if defined( DMAREQ_TIMER0_CC0 )
166  dmadrvPeripheralSignal_TIMER0_CC0 = DMAREQ_TIMER0_CC0,
167  #endif
168  #if defined( DMAREQ_TIMER0_CC1 )
169  dmadrvPeripheralSignal_TIMER0_CC1 = DMAREQ_TIMER0_CC1,
170  #endif
171  #if defined( DMAREQ_TIMER0_CC2 )
172  dmadrvPeripheralSignal_TIMER0_CC2 = DMAREQ_TIMER0_CC2,
173  #endif
174  #if defined( DMAREQ_TIMER0_UFOF )
175  dmadrvPeripheralSignal_TIMER0_UFOF = DMAREQ_TIMER0_UFOF,
176  #endif
177  #if defined( DMAREQ_TIMER1_CC0 )
178  dmadrvPeripheralSignal_TIMER1_CC0 = DMAREQ_TIMER1_CC0,
179  #endif
180  #if defined( DMAREQ_TIMER1_CC1 )
181  dmadrvPeripheralSignal_TIMER1_CC1 = DMAREQ_TIMER1_CC1,
182  #endif
183  #if defined( DMAREQ_TIMER1_CC2 )
184  dmadrvPeripheralSignal_TIMER1_CC2 = DMAREQ_TIMER1_CC2,
185  #endif
186  #if defined( DMAREQ_TIMER1_UFOF )
187  dmadrvPeripheralSignal_TIMER1_UFOF = DMAREQ_TIMER1_UFOF,
188  #endif
189  #if defined( DMAREQ_TIMER2_CC0 )
190  dmadrvPeripheralSignal_TIMER2_CC0 = DMAREQ_TIMER2_CC0,
191  #endif
192  #if defined( DMAREQ_TIMER2_CC1 )
193  dmadrvPeripheralSignal_TIMER2_CC1 = DMAREQ_TIMER2_CC1,
194  #endif
195  #if defined( DMAREQ_TIMER2_CC2 )
196  dmadrvPeripheralSignal_TIMER2_CC2 = DMAREQ_TIMER2_CC2,
197  #endif
198  #if defined( DMAREQ_TIMER2_UFOF )
199  dmadrvPeripheralSignal_TIMER2_UFOF = DMAREQ_TIMER2_UFOF,
200  #endif
201  #if defined( DMAREQ_TIMER3_CC0 )
202  dmadrvPeripheralSignal_TIMER3_CC0 = DMAREQ_TIMER3_CC0,
203  #endif
204  #if defined( DMAREQ_TIMER3_CC1 )
205  dmadrvPeripheralSignal_TIMER3_CC1 = DMAREQ_TIMER3_CC1,
206  #endif
207  #if defined( DMAREQ_TIMER3_CC2 )
208  dmadrvPeripheralSignal_TIMER3_CC2 = DMAREQ_TIMER3_CC2,
209  #endif
210  #if defined( DMAREQ_TIMER3_UFOF )
211  dmadrvPeripheralSignal_TIMER3_UFOF = DMAREQ_TIMER3_UFOF,
212  #endif
213  #if defined( DMAREQ_UART0_RXDATAV )
214  dmadrvPeripheralSignal_UART0_RXDATAV = DMAREQ_UART0_RXDATAV,
215  #endif
216  #if defined( DMAREQ_UART0_TXBL )
217  dmadrvPeripheralSignal_UART0_TXBL = DMAREQ_UART0_TXBL,
218  #endif
219  #if defined( DMAREQ_UART0_TXEMPTY )
220  dmadrvPeripheralSignal_UART0_TXEMPTY = DMAREQ_UART0_TXEMPTY,
221  #endif
222  #if defined( DMAREQ_UART1_RXDATAV )
223  dmadrvPeripheralSignal_UART1_RXDATAV = DMAREQ_UART1_RXDATAV,
224  #endif
225  #if defined( DMAREQ_UART1_TXBL )
226  dmadrvPeripheralSignal_UART1_TXBL = DMAREQ_UART1_TXBL,
227  #endif
228  #if defined( DMAREQ_UART1_TXEMPTY )
229  dmadrvPeripheralSignal_UART1_TXEMPTY = DMAREQ_UART1_TXEMPTY,
230  #endif
231  #if defined( DMAREQ_USART0_RXDATAV )
232  dmadrvPeripheralSignal_USART0_RXDATAV = DMAREQ_USART0_RXDATAV,
233  #endif
234  #if defined( DMAREQ_USART0_TXBL )
235  dmadrvPeripheralSignal_USART0_TXBL = DMAREQ_USART0_TXBL,
236  #endif
237  #if defined( DMAREQ_USART0_TXEMPTY )
238  dmadrvPeripheralSignal_USART0_TXEMPTY = DMAREQ_USART0_TXEMPTY,
239  #endif
240  #if defined( DMAREQ_USARTRF0_RXDATAV )
241  dmadrvPeripheralSignal_USARTRF0_RXDATAV = DMAREQ_USARTRF0_RXDATAV,
242  #endif
243  #if defined( DMAREQ_USARTRF0_TXBL )
244  dmadrvPeripheralSignal_USARTRF0_TXBL = DMAREQ_USARTRF0_TXBL,
245  #endif
246  #if defined( DMAREQ_USARTRF0_TXEMPTY )
247  dmadrvPeripheralSignal_USARTRF0_TXEMPTY = DMAREQ_USARTRF0_TXEMPTY,
248  #endif
249  #if defined( DMAREQ_USARTRF1_RXDATAV )
250  dmadrvPeripheralSignal_USARTRF1_RXDATAV = DMAREQ_USARTRF1_RXDATAV,
251  #endif
252  #if defined( DMAREQ_USARTRF1_TXBL )
253  dmadrvPeripheralSignal_USARTRF1_TXBL = DMAREQ_USARTRF1_TXBL,
254  #endif
255  #if defined( DMAREQ_USARTRF1_TXEMPTY )
256  dmadrvPeripheralSignal_USARTRF1_TXEMPTY = DMAREQ_USARTRF1_TXEMPTY,
257  #endif
258  #if defined( DMAREQ_USART1_RXDATAV )
259  dmadrvPeripheralSignal_USART1_RXDATAV = DMAREQ_USART1_RXDATAV,
260  #endif
261  #if defined( DMAREQ_USART1_RXDATAVRIGHT )
262  dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = DMAREQ_USART1_RXDATAVRIGHT,
263  #endif
264  #if defined( DMAREQ_USART1_TXBL )
265  dmadrvPeripheralSignal_USART1_TXBL = DMAREQ_USART1_TXBL,
266  #endif
267  #if defined( DMAREQ_USART1_TXBLRIGHT )
268  dmadrvPeripheralSignal_USART1_TXBLRIGHT = DMAREQ_USART1_TXBLRIGHT,
269  #endif
270  #if defined( DMAREQ_USART1_TXEMPTY )
271  dmadrvPeripheralSignal_USART1_TXEMPTY = DMAREQ_USART1_TXEMPTY,
272  #endif
273  #if defined( DMAREQ_USART2_RXDATAV )
274  dmadrvPeripheralSignal_USART2_RXDATAV = DMAREQ_USART2_RXDATAV,
275  #endif
276  #if defined( DMAREQ_USART2_RXDATAVRIGHT )
277  dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = DMAREQ_USART2_RXDATAVRIGHT,
278  #endif
279  #if defined( DMAREQ_USART2_TXBL )
280  dmadrvPeripheralSignal_USART2_TXBL = DMAREQ_USART2_TXBL,
281  #endif
282  #if defined( DMAREQ_USART2_TXBLRIGHT )
283  dmadrvPeripheralSignal_USART2_TXBLRIGHT = DMAREQ_USART2_TXBLRIGHT,
284  #endif
285  #if defined( DMAREQ_USART2_TXEMPTY )
286  dmadrvPeripheralSignal_USART2_TXEMPTY = DMAREQ_USART2_TXEMPTY,
287  #endif
288 #ifdef DOXY_DOC_ONLY
289 } DMADRV_Peripheralsignal_t;
290 #else
291 } DMADRV_PeripheralSignal_t;
292 #endif
293 
295 typedef enum
296 {
297  dmadrvDataSize1 = dmaDataSize1,
298  dmadrvDataSize2 = dmaDataSize2,
299  dmadrvDataSize4 = dmaDataSize4
300 #ifdef DOXY_DOC_ONLY
301 } DMADRV_Datasize_t;
302 #else
303 } DMADRV_DataSize_t;
304 #endif
305 
306 #endif // defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
307 
308 #if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
309 
311 #define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1))
312 
314 typedef enum
315 {
316  dmadrvPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE,
317  #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN )
318  dmadrvPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0,
319  #endif
320  #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE )
321  dmadrvPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0,
322  #endif
323  #if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI )
324  dmadrvPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC,
325  #endif
326  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD )
327  dmadrvPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
328  #endif
329  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR )
330  dmadrvPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
331  #endif
332  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR )
333  dmadrvPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
334  #endif
335  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD )
336  dmadrvPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
337  #endif
338  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR )
339  dmadrvPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
340  #endif
341  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD )
342  dmadrvPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
343  #endif
344  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR )
345  dmadrvPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
346  #endif
347  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR )
348  dmadrvPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
349  #endif
350  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD )
351  dmadrvPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
352  #endif
353  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR )
354  dmadrvPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
355  #endif
356  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD )
357  dmadrvPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1,
358  #endif
359  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR )
360  dmadrvPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1,
361  #endif
362  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR )
363  dmadrvPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1,
364  #endif
365  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD )
366  dmadrvPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1,
367  #endif
368  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR )
369  dmadrvPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1,
370  #endif
371  #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV )
372  dmadrvPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0,
373  #endif
374  #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL )
375  dmadrvPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0,
376  #endif
377  #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV )
378  dmadrvPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
379  #endif
380  #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL )
381  dmadrvPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
382  #endif
383  #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY )
384  dmadrvPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
385  #endif
386  #if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG )
387  dmadrvPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM,
388  #endif
389  #if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA )
390  dmadrvPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC,
391  #endif
392  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF )
393  dmadrvPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
394  #endif
395  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 )
396  dmadrvPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
397  #endif
398  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 )
399  dmadrvPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
400  #endif
401  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 )
402  dmadrvPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
403  #endif
404  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 )
405  dmadrvPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
406  #endif
407  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 )
408  dmadrvPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
409  #endif
410  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF )
411  dmadrvPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
412  #endif
413  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF )
414  dmadrvPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
415  #endif
416  #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 )
417  dmadrvPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS,
418  #endif
419  #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 )
420  dmadrvPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS,
421  #endif
422  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 )
423  dmadrvPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
424  #endif
425  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 )
426  dmadrvPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
427  #endif
428  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 )
429  dmadrvPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
430  #endif
431  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF )
432  dmadrvPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
433  #endif
434  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 )
435  dmadrvPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
436  #endif
437  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 )
438  dmadrvPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
439  #endif
440  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 )
441  dmadrvPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
442  #endif
443  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 )
444  dmadrvPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
445  #endif
446  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF )
447  dmadrvPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
448  #endif
449  #if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV )
450  dmadrvPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0,
451  #endif
452  #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL )
453  dmadrvPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0,
454  #endif
455  #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY )
456  dmadrvPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0,
457  #endif
458  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV )
459  dmadrvPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1,
460  #endif
461  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT )
462  dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,
463  #endif
464  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL )
465  dmadrvPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1,
466  #endif
467  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT )
468  dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,
469  #endif
470  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY )
471  dmadrvPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1,
472  #endif
473  #if defined( LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV )
474  dmadrvPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2,
475  #endif
476  #if defined( LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT )
477  dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2,
478  #endif
479  #if defined( LDMA_CH_REQSEL_SIGSEL_USART2TXBL )
480  dmadrvPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2,
481  #endif
482  #if defined( LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT )
483  dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2,
484  #endif
485  #if defined( LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY )
486  dmadrvPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2,
487  #endif
488  #if defined( LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV )
489  dmadrvPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3,
490  #endif
491  #if defined( LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT )
492  dmadrvPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3,
493  #endif
494  #if defined( LDMA_CH_REQSEL_SIGSEL_USART3TXBL )
495  dmadrvPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3,
496  #endif
497  #if defined( LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT )
498  dmadrvPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3,
499  #endif
500  #if defined( LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY )
501  dmadrvPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3
502  #endif
503 
504 
505 } DMADRV_PeripheralSignal_t;
506 
508 typedef enum
509 {
510  dmadrvDataSize1 = ldmaCtrlSizeByte,
511  dmadrvDataSize2 = ldmaCtrlSizeHalf,
512  dmadrvDataSize4 = ldmaCtrlSizeWord
513 } DMADRV_DataSize_t;
514 
515 #endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */
516 
517 Ecode_t DMADRV_AllocateChannel( unsigned int *channelId, void *capabilities );
518 Ecode_t DMADRV_DeInit( void );
519 Ecode_t DMADRV_FreeChannel( unsigned int channelId );
520 Ecode_t DMADRV_Init( void );
521 
522 #if !defined( EMDRV_DMADRV_USE_NATIVE_API ) || defined( DOXY_DOC_ONLY )
523 Ecode_t DMADRV_MemoryPeripheral( unsigned int channelId,
524  DMADRV_PeripheralSignal_t
525  peripheralSignal,
526  void *dst,
527  void *src,
528  bool srcInc,
529  int len,
530  DMADRV_DataSize_t size,
531  DMADRV_Callback_t callback,
532  void *cbUserParam );
533 Ecode_t DMADRV_PeripheralMemory( unsigned int channelId,
534  DMADRV_PeripheralSignal_t
535  peripheralSignal,
536  void *dst,
537  void *src,
538  bool dstInc,
539  int len,
540  DMADRV_DataSize_t size,
541  DMADRV_Callback_t callback,
542  void *cbUserParam );
543 Ecode_t DMADRV_MemoryPeripheralPingPong(
544  unsigned int channelId,
545  DMADRV_PeripheralSignal_t
546  peripheralSignal,
547  void *dst,
548  void *src0,
549  void *src1,
550  bool srcInc,
551  int len,
552  DMADRV_DataSize_t size,
553  DMADRV_Callback_t callback,
554  void *cbUserParam );
555 Ecode_t DMADRV_PeripheralMemoryPingPong(
556  unsigned int channelId,
557  DMADRV_PeripheralSignal_t
558  peripheralSignal,
559  void *dst0,
560  void *dst1,
561  void *src,
562  bool dstInc,
563  int len,
564  DMADRV_DataSize_t size,
565  DMADRV_Callback_t callback,
566  void *cbUserParam );
567 #endif
568 
569 #if defined( EMDRV_DMADRV_LDMA ) && defined( EMDRV_DMADRV_USE_NATIVE_API )
570 
571 Ecode_t DMADRV_LdmaStartTransfer(
572  int channelId,
573  LDMA_TransferCfg_t *transfer,
574  LDMA_Descriptor_t *descriptor,
575  DMADRV_Callback_t callback,
576  void *cbUserParam );
577 
578 #endif /* !defined( EMDRV_DMADRV_USE_NATIVE_API ) */
579 
580 Ecode_t DMADRV_PauseTransfer( unsigned int channelId );
581 Ecode_t DMADRV_ResumeTransfer( unsigned int channelId );
582 Ecode_t DMADRV_StopTransfer( unsigned int channelId );
583 Ecode_t DMADRV_TransferActive( unsigned int channelId, bool *active );
584 Ecode_t DMADRV_TransferCompletePending( unsigned int channelId, bool *pending );
585 Ecode_t DMADRV_TransferDone( unsigned int channelId, bool *done );
586 Ecode_t DMADRV_TransferRemainingCount( unsigned int channelId,
587  int *remaining );
588 
592 #ifdef __cplusplus
593 }
594 #endif
595 
596 #endif /* __SILICON_LABS_DMADRV_H__ */
DMAREQ_LESENSE_BUFDATAV
#define DMAREQ_LESENSE_BUFDATAV
Definition: efm32gg_dmareq.h:95
DMAREQ_EBI_PXLFULL
#define DMAREQ_EBI_PXLFULL
Definition: efm32gg_dmareq.h:98
dmaDataSize4
Definition: em_dma.h:78
dmadrvPeripheralSignal_TIMER1_UFOF
Trig on TIMER1_UFOF.
Definition: dmadrv.h:187
DMAREQ_AES_XORDATAWR
#define DMAREQ_AES_XORDATAWR
Definition: efm32gg_dmareq.h:92
DMAREQ_USART1_TXBL
#define DMAREQ_USART1_TXBL
Definition: efm32gg_dmareq.h:49
DMAREQ_USART1_TXEMPTY
#define DMAREQ_USART1_TXEMPTY
Definition: efm32gg_dmareq.h:50
DMAREQ_TIMER3_CC1
#define DMAREQ_TIMER3_CC1
Definition: efm32gg_dmareq.h:82
DMAREQ_USART2_TXBL
#define DMAREQ_USART2_TXBL
Definition: efm32gg_dmareq.h:54
dmadrvPeripheralSignal_TIMER0_CC0
Trig on TIMER0_CC0.
Definition: dmadrv.h:166
DMAREQ_ADC0_SCAN
#define DMAREQ_ADC0_SCAN
Definition: efm32gg_dmareq.h:42
dmadrvPeripheralSignal_USART2_TXBLRIGHT
Trig on USART2_TXBLRIGHT.
Definition: dmadrv.h:283
dmadrvPeripheralSignal_USART2_TXEMPTY
Trig on USART2_TXEMPTY.
Definition: dmadrv.h:286
dmadrvPeripheralSignal_USART0_RXDATAV
Trig on USART0_RXDATAV.
Definition: dmadrv.h:232
dmadrvPeripheralSignal_USART0_TXBL
Trig on USART0_TXBL.
Definition: dmadrv.h:235
DMAREQ_EBI_PXL1EMPTY
#define DMAREQ_EBI_PXL1EMPTY
Definition: efm32gg_dmareq.h:97
dmadrvPeripheralSignal_AES_XORDATAWR
Trig on AES_XORDATAWR.
Definition: dmadrv.h:109
dmadrvPeripheralSignal_TIMER3_UFOF
Trig on TIMER3_UFOF.
Definition: dmadrv.h:211
dmadrvPeripheralSignal_USART1_RXDATAV
Trig on USART1_RXDATAV.
Definition: dmadrv.h:259
DMADRV_PeripheralMemory
Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a peripheral to memory DMA transfer.
Definition: dmadrv.c:539
dmadrvPeripheralSignal_USART1_TXEMPTY
Trig on USART1_TXEMPTY.
Definition: dmadrv.h:271
DMAREQ_TIMER1_CC2
#define DMAREQ_TIMER1_CC2
Definition: efm32gg_dmareq.h:75
dmadrvPeripheralSignal_AES_KEYWR
Trig on AES_KEYWR.
Definition: dmadrv.h:106
DMADRV_TransferActive
Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active)
Check if a transfer is running.
Definition: dmadrv.c:759
ecode.h
Energy Aware drivers error code definitions.
DMAREQ_DAC0_CH0
#define DMAREQ_DAC0_CH0
Definition: efm32gg_dmareq.h:43
DMADRV_Callback_t
bool(* DMADRV_Callback_t)(unsigned int channel, unsigned int sequenceNo, void *userParam)
DMADRV transfer completion callback function.
Definition: dmadrv.h:80
DMAREQ_UART0_TXBL
#define DMAREQ_UART0_TXBL
Definition: efm32gg_dmareq.h:85
dmadrvPeripheralSignal_LEUART1_RXDATAV
Trig on LEUART1_RXDATAV.
Definition: dmadrv.h:154
dmadrvPeripheralSignal_EBI_PXLFULL
Trig on EBI_PXLFULL.
Definition: dmadrv.h:127
dmadrvPeripheralSignal_LEUART0_TXEMPTY
Trig on LEUART0_TXEMPTY.
Definition: dmadrv.h:151
DMAREQ_UART1_TXEMPTY
#define DMAREQ_UART1_TXEMPTY
Definition: efm32gg_dmareq.h:89
DMAREQ_UART1_TXBL
#define DMAREQ_UART1_TXBL
Definition: efm32gg_dmareq.h:88
dmadrvPeripheralSignal_ADC0_SCAN
Trig on ADC0_SCAN.
Definition: dmadrv.h:94
dmadrvPeripheralSignal_NONE
No peripheral selected for DMA triggering.
Definition: dmadrv.h:92
DMAREQ_LEUART0_TXEMPTY
#define DMAREQ_LEUART0_TXEMPTY
Definition: efm32gg_dmareq.h:60
DMADRV_StopTransfer
Ecode_t DMADRV_StopTransfer(unsigned int channelId)
Stop an ongoing DMA transfer.
Definition: dmadrv.c:719
dmadrvPeripheralSignal_TIMER2_UFOF
Trig on TIMER2_UFOF.
Definition: dmadrv.h:199
dmadrvPeripheralSignal_LEUART0_RXDATAV
Trig on LEUART0_RXDATAV.
Definition: dmadrv.h:145
dmadrvDataSize2
Halfword.
Definition: dmadrv.h:298
DMAREQ_LEUART1_TXEMPTY
#define DMAREQ_LEUART1_TXEMPTY
Definition: efm32gg_dmareq.h:63
em_device.h
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
dmadrvPeripheralSignal_TIMER1_CC2
Trig on TIMER1_CC2.
Definition: dmadrv.h:184
DMAREQ_USART1_RXDATAV
#define DMAREQ_USART1_RXDATAV
Definition: efm32gg_dmareq.h:48
dmadrvPeripheralSignal_UART0_RXDATAV
Trig on UART0_RXDATAV.
Definition: dmadrv.h:214
dmaDataSize1
Definition: em_dma.h:76
dmadrvPeripheralSignal_UART1_TXEMPTY
Trig on UART1_TXEMPTY.
Definition: dmadrv.h:229
DMAREQ_UART0_RXDATAV
#define DMAREQ_UART0_RXDATAV
Definition: efm32gg_dmareq.h:84
DMAREQ_LEUART1_TXBL
#define DMAREQ_LEUART1_TXBL
Definition: efm32gg_dmareq.h:62
dmadrvPeripheralSignal_UART1_RXDATAV
Trig on UART1_RXDATAV.
Definition: dmadrv.h:223
DMADRV_TransferDone
Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done)
Check if a transfer has completed.
Definition: dmadrv.c:864
dmadrvPeripheralSignal_DAC0_CH1
Trig on DAC0_CH1.
Definition: dmadrv.h:115
DMAREQ_TIMER0_CC0
#define DMAREQ_TIMER0_CC0
Definition: efm32gg_dmareq.h:69
dmadrvDataSize1
Byte.
Definition: dmadrv.h:297
dmadrvPeripheralSignal_LESENSE_BUFDATAV
Trig on LESENSE_BUFDATAV.
Definition: dmadrv.h:142
DMAREQ_LEUART1_RXDATAV
#define DMAREQ_LEUART1_RXDATAV
Definition: efm32gg_dmareq.h:61
DMAREQ_AES_KEYWR
#define DMAREQ_AES_KEYWR
Definition: efm32gg_dmareq.h:94
dmadrvPeripheralSignal_TIMER3_CC2
Trig on TIMER3_CC2.
Definition: dmadrv.h:208
DMAREQ_TIMER2_CC2
#define DMAREQ_TIMER2_CC2
Definition: efm32gg_dmareq.h:79
dmadrvPeripheralSignal_LEUART0_TXBL
Trig on LEUART0_TXBL.
Definition: dmadrv.h:148
DMADRV_TransferRemainingCount
Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, int *remaining)
Get number of items remaining in a transfer.
Definition: dmadrv.c:930
dmadrvPeripheralSignal_USART1_TXBL
Trig on USART1_TXBL.
Definition: dmadrv.h:265
DMADRV_ResumeTransfer
Ecode_t DMADRV_ResumeTransfer(unsigned int channelId)
Resume an ongoing DMA transfer.
Definition: dmadrv.c:682
dmadrvPeripheralSignal_TIMER2_CC2
Trig on TIMER2_CC2.
Definition: dmadrv.h:196
dmadrvPeripheralSignal_TIMER0_CC1
Trig on TIMER0_CC1.
Definition: dmadrv.h:169
DMAREQ_I2C1_TXBL
#define DMAREQ_I2C1_TXBL
Definition: efm32gg_dmareq.h:67
DMAREQ_USART2_RXDATAVRIGHT
#define DMAREQ_USART2_RXDATAVRIGHT
Definition: efm32gg_dmareq.h:56
dmadrvPeripheralSignal_LEUART1_TXBL
Trig on LEUART1_TXBL.
Definition: dmadrv.h:157
dmadrvPeripheralSignal_EBI_PXL0EMPTY
Trig on EBI_PXL0EMPTY.
Definition: dmadrv.h:121
DMAREQ_USART0_TXBL
#define DMAREQ_USART0_TXBL
Definition: efm32gg_dmareq.h:46
DMADRV_Datasize_t
DMADRV_Datasize_t
Data size of one UDMA transfer item.
Definition: dmadrv.h:295
dmadrvPeripheralSignal_UART0_TXBL
Trig on UART0_TXBL.
Definition: dmadrv.h:217
dmadrvPeripheralSignal_EBI_DDEMPTY
Trig on EBI_DDEMPTY.
Definition: dmadrv.h:118
DMADRV_MemoryPeripheralPingPong
Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src0, void *src1, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a memory to peripheral ping-pong DMA transfer.
Definition: dmadrv.c:473
DMAREQ_USART0_TXEMPTY
#define DMAREQ_USART0_TXEMPTY
Definition: efm32gg_dmareq.h:47
dmadrvPeripheralSignal_TIMER3_CC0
Trig on TIMER3_CC0.
Definition: dmadrv.h:202
dmadrvPeripheralSignal_I2C0_RXDATAV
Trig on I2C0_RXDATAV.
Definition: dmadrv.h:130
DMAREQ_TIMER0_CC1
#define DMAREQ_TIMER0_CC1
Definition: efm32gg_dmareq.h:70
Ecode_t
uint32_t Ecode_t
Typedef for API function error code return values.
Definition: ecode.h:51
DMAREQ_USART0_RXDATAV
#define DMAREQ_USART0_RXDATAV
Definition: efm32gg_dmareq.h:45
DMAREQ_DAC0_CH1
#define DMAREQ_DAC0_CH1
Definition: efm32gg_dmareq.h:44
dmadrvPeripheralSignal_AES_DATAWR
Trig on AES_DATAWR.
Definition: dmadrv.h:103
dmadrvPeripheralSignal_ADC0_SINGLE
Trig on ADC0_SINGLE.
Definition: dmadrv.h:97
DMAREQ_I2C0_RXDATAV
#define DMAREQ_I2C0_RXDATAV
Definition: efm32gg_dmareq.h:64
DMADRV_Init
Ecode_t DMADRV_Init(void)
Initialize DMADRV.
Definition: dmadrv.c:262
DMAREQ_TIMER2_CC0
#define DMAREQ_TIMER2_CC0
Definition: efm32gg_dmareq.h:77
DMAREQ_MSC_WDATA
#define DMAREQ_MSC_WDATA
Definition: efm32gg_dmareq.h:90
dmadrvPeripheralSignal_MSC_WDATA
Trig on MSC_WDATA.
Definition: dmadrv.h:163
DMAREQ_TIMER0_CC2
#define DMAREQ_TIMER0_CC2
Definition: efm32gg_dmareq.h:71
DMAREQ_TIMER2_CC1
#define DMAREQ_TIMER2_CC1
Definition: efm32gg_dmareq.h:78
DMAREQ_EBI_DDEMPTY
#define DMAREQ_EBI_DDEMPTY
Definition: efm32gg_dmareq.h:99
dmadrvPeripheralSignal_USART0_TXEMPTY
Trig on USART0_TXEMPTY.
Definition: dmadrv.h:238
em_ldma.h
Direct memory access (LDMA) API.
dmadrvPeripheralSignal_TIMER1_CC0
Trig on TIMER1_CC0.
Definition: dmadrv.h:178
dmadrvPeripheralSignal_USART2_RXDATAVRIGHT
Trig on USART2_RXDATAVRIGHT.
Definition: dmadrv.h:277
DMAREQ_USART1_TXBLRIGHT
#define DMAREQ_USART1_TXBLRIGHT
Definition: efm32gg_dmareq.h:52
dmadrvPeripheralSignal_TIMER0_UFOF
Trig on TIMER0_UFOF.
Definition: dmadrv.h:175
dmadrvPeripheralSignal_USART1_RXDATAVRIGHT
Trig on USART1_RXDATAVRIGHT.
Definition: dmadrv.h:262
DMADRV_DeInit
Ecode_t DMADRV_DeInit(void)
Deinitialize DMADRV.
Definition: dmadrv.c:177
DMAREQ_TIMER3_CC2
#define DMAREQ_TIMER3_CC2
Definition: efm32gg_dmareq.h:83
DMAREQ_USART2_RXDATAV
#define DMAREQ_USART2_RXDATAV
Definition: efm32gg_dmareq.h:53
DMAREQ_I2C0_TXBL
#define DMAREQ_I2C0_TXBL
Definition: efm32gg_dmareq.h:65
dmadrvPeripheralSignal_DAC0_CH0
Trig on DAC0_CH0.
Definition: dmadrv.h:112
DMAREQ_TIMER3_CC0
#define DMAREQ_TIMER3_CC0
Definition: efm32gg_dmareq.h:81
DMAREQ_UART0_TXEMPTY
#define DMAREQ_UART0_TXEMPTY
Definition: efm32gg_dmareq.h:86
DMADRV_AllocateChannel
Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities)
Allocate (reserve) a DMA channel.
Definition: dmadrv.c:131
DMAREQ_TIMER1_UFOF
#define DMAREQ_TIMER1_UFOF
Definition: efm32gg_dmareq.h:72
DMADRV_MemoryPeripheral
Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a memory to peripheral DMA transfer.
Definition: dmadrv.c:406
DMAREQ_TIMER1_CC1
#define DMAREQ_TIMER1_CC1
Definition: efm32gg_dmareq.h:74
dmadrvPeripheralSignal_USART2_RXDATAV
Trig on USART2_RXDATAV.
Definition: dmadrv.h:274
dmadrvPeripheralSignal_I2C0_TXBL
Trig on I2C0_TXBL.
Definition: dmadrv.h:133
DMAREQ_TIMER2_UFOF
#define DMAREQ_TIMER2_UFOF
Definition: efm32gg_dmareq.h:76
DMADRV_TransferCompletePending
Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending)
Check if a transfer complete is pending.
Definition: dmadrv.c:811
DMAREQ_LEUART0_RXDATAV
#define DMAREQ_LEUART0_RXDATAV
Definition: efm32gg_dmareq.h:58
dmadrvDataSize4
Word.
Definition: dmadrv.h:299
DMAREQ_I2C1_RXDATAV
#define DMAREQ_I2C1_RXDATAV
Definition: efm32gg_dmareq.h:66
dmadrvPeripheralSignal_EBI_PXL1EMPTY
Trig on EBI_PXL1EMPTY.
Definition: dmadrv.h:124
DMAREQ_TIMER1_CC0
#define DMAREQ_TIMER1_CC0
Definition: efm32gg_dmareq.h:73
DMAREQ_EBI_PXL0EMPTY
#define DMAREQ_EBI_PXL0EMPTY
Definition: efm32gg_dmareq.h:96
dmadrvPeripheralSignal_I2C1_TXBL
Trig on I2C1_TXBL.
Definition: dmadrv.h:139
DMAREQ_AES_DATAWR
#define DMAREQ_AES_DATAWR
Definition: efm32gg_dmareq.h:91
DMAREQ_USART1_RXDATAVRIGHT
#define DMAREQ_USART1_RXDATAVRIGHT
Definition: efm32gg_dmareq.h:51
dmadrvPeripheralSignal_TIMER0_CC2
Trig on TIMER0_CC2.
Definition: dmadrv.h:172
DMADRV_Peripheralsignal_t
DMADRV_Peripheralsignal_t
Peripherals that can trigger UDMA transfers.
Definition: dmadrv.h:90
dmadrvPeripheralSignal_AES_DATARD
Trig on AES_DATARD.
Definition: dmadrv.h:100
DMAREQ_USART2_TXEMPTY
#define DMAREQ_USART2_TXEMPTY
Definition: efm32gg_dmareq.h:55
dmadrvPeripheralSignal_USART2_TXBL
Trig on USART2_TXBL.
Definition: dmadrv.h:280
DMAREQ_ADC0_SINGLE
#define DMAREQ_ADC0_SINGLE
Definition: efm32gg_dmareq.h:41
dmadrvPeripheralSignal_TIMER1_CC1
Trig on TIMER1_CC1.
Definition: dmadrv.h:181
DMAREQ_AES_DATARD
#define DMAREQ_AES_DATARD
Definition: efm32gg_dmareq.h:93
DMAREQ_USART2_TXBLRIGHT
#define DMAREQ_USART2_TXBLRIGHT
Definition: efm32gg_dmareq.h:57
DMADRV_PeripheralMemoryPingPong
Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst0, void *dst1, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a peripheral to memory ping-pong DMA transfer.
Definition: dmadrv.c:606
DMAREQ_UART1_RXDATAV
#define DMAREQ_UART1_RXDATAV
Definition: efm32gg_dmareq.h:87
dmadrvPeripheralSignal_UART1_TXBL
Trig on UART1_TXBL.
Definition: dmadrv.h:226
em_dma.h
Direct memory access (DMA) API.
dmadrvPeripheralSignal_LEUART1_TXEMPTY
Trig on LEUART1_TXEMPTY.
Definition: dmadrv.h:160
DMAREQ_TIMER3_UFOF
#define DMAREQ_TIMER3_UFOF
Definition: efm32gg_dmareq.h:80
DMAREQ_LEUART0_TXBL
#define DMAREQ_LEUART0_TXBL
Definition: efm32gg_dmareq.h:59
dmadrvPeripheralSignal_I2C1_RXDATAV
Trig on I2C1_RXDATAV.
Definition: dmadrv.h:136
dmadrvPeripheralSignal_TIMER3_CC1
Trig on TIMER3_CC1.
Definition: dmadrv.h:205
DMADRV_PauseTransfer
Ecode_t DMADRV_PauseTransfer(unsigned int channelId)
Pause an ongoing DMA transfer.
Definition: dmadrv.c:645
dmadrvPeripheralSignal_USART1_TXBLRIGHT
Trig on USART1_TXBLRIGHT.
Definition: dmadrv.h:268
DMADRV_FreeChannel
Ecode_t DMADRV_FreeChannel(unsigned int channelId)
Free an allocate (reserved) DMA channel.
Definition: dmadrv.c:225
dmaDataSize2
Definition: em_dma.h:77
dmadrvPeripheralSignal_TIMER2_CC1
Trig on TIMER2_CC1.
Definition: dmadrv.h:193
dmadrvPeripheralSignal_TIMER2_CC0
Trig on TIMER2_CC0.
Definition: dmadrv.h:190
DMAREQ_TIMER0_UFOF
#define DMAREQ_TIMER0_UFOF
Definition: efm32gg_dmareq.h:68
dmadrvPeripheralSignal_UART0_TXEMPTY
Trig on UART0_TXEMPTY.
Definition: dmadrv.h:220