EFM32 Gecko Software Documentation  efm32g-doc-5.1.2
em_pcnt.c
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1 /***************************************************************************/
33 #include "em_pcnt.h"
34 #if defined(PCNT_COUNT) && (PCNT_COUNT > 0)
35 
36 #include "em_cmu.h"
37 #include "em_assert.h"
38 #include "em_bus.h"
39 
40 /***************************************************************************/
45 /***************************************************************************/
56 /*******************************************************************************
57  ******************************* DEFINES ***********************************
58  ******************************************************************************/
59 
64 #if (PCNT_COUNT == 1)
65 #define PCNT_REF_VALID(ref) ((ref) == PCNT0)
66 #elif (PCNT_COUNT == 2)
67 #define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1))
68 #elif (PCNT_COUNT == 3)
69 #define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) || \
70  ((ref) == PCNT2))
71 #else
72 #error "Undefined number of pulse counters (PCNT)."
73 #endif
74 
78 /*******************************************************************************
79  ************************** LOCAL FUNCTIONS ********************************
80  ******************************************************************************/
81 
84 /***************************************************************************/
94 __STATIC_INLINE unsigned int PCNT_Map(PCNT_TypeDef *pcnt)
95 {
96  return ((uint32_t)pcnt - PCNT0_BASE) / 0x400;
97 }
98 
99 
100 /***************************************************************************/
111 __STATIC_INLINE void PCNT_Sync(PCNT_TypeDef *pcnt, uint32_t mask)
112 {
113  /* Avoid deadlock if modifying the same register twice when freeze mode is
114  * activated. */
115  if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE)
116  {
117  return;
118  }
119 
120  /* Wait for any pending previous write operation to have been completed in low
121  * frequency domain. */
122  while (pcnt->SYNCBUSY & mask)
123  ;
124 }
125 
128 /*******************************************************************************
129  ************************** GLOBAL FUNCTIONS *******************************
130  ******************************************************************************/
131 
132 /***************************************************************************/
147 {
148  EFM_ASSERT(PCNT_REF_VALID(pcnt));
149 
150  /* Enable reset of CNT and TOP register */
152 
153  /* Disable reset of CNT and TOP register */
155 }
156 
157 
158 /***************************************************************************/
182 void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
183 {
184  uint32_t ctrl;
185 
186  EFM_ASSERT(PCNT_REF_VALID(pcnt));
187 
188 #ifdef PCNT0
189  if (PCNT0 == pcnt)
190  {
191  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > count);
192  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > top);
193  }
194 #endif
195 
196 #ifdef PCNT1
197  if (PCNT1 == pcnt)
198  {
199  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > count);
200  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > top);
201  }
202 #endif
203 
204 #ifdef PCNT2
205  if (PCNT2 == pcnt)
206  {
207  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > count);
208  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > top);
209  }
210 #endif
211 
212  /* Keep current control setting, must be restored */
213  ctrl = pcnt->CTRL;
214 
215  /* If enabled, disable pulse counter before changing values */
217  {
218  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
219  pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE;
220  }
221 
222  /* Load into TOPB */
223  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB);
224  pcnt->TOPB = count;
225 
226  /* Load TOPB value into TOP */
227  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD);
228 
229  /* This bit has no effect on rev. C and onwards parts - for compatibility */
230  pcnt->CMD = PCNT_CMD_LTOPBIM;
231  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD);
232 
233  /* Load TOP into CNT */
234  pcnt->CMD = PCNT_CMD_LCNTIM;
235 
236  /* Restore TOP? ('count' setting has been loaded into pcnt->TOP, better
237  * to use 'top' than pcnt->TOP in compare, since latter may in theory not
238  * be visible yet.) */
239  if (top != count)
240  {
241  /* Wait for command to sync LCNTIM before setting TOPB */
242  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD);
243 
244  /* Load into TOPB, we don't need to check for TOPB sync complete here,
245  * it has been ensured above. */
246  pcnt->TOPB = top;
247 
248  /* Load TOPB value into TOP */
249  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD);
250  pcnt->CMD = PCNT_CMD_LTOPBIM;
251  }
252 
253  /* Reenable if it was enabled */
254  if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE)
255  {
256  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL | PCNT_SYNCBUSY_CMD);
257  pcnt->CTRL = ctrl;
258  }
259 }
260 
261 
262 /***************************************************************************/
285 {
286  uint32_t tmp;
287 
288  EFM_ASSERT(PCNT_REF_VALID(pcnt));
289 
290  /* Set as specified */
291  tmp = pcnt->CTRL & ~_PCNT_CTRL_MODE_MASK;
292  tmp |= (uint32_t)mode << _PCNT_CTRL_MODE_SHIFT;
293 
294  /* LF register about to be modified require sync. busy check */
295  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
296  pcnt->CTRL = tmp;
297 }
298 
299 #if defined(_PCNT_INPUT_MASK)
300 /***************************************************************************/
316 void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt,
317  PCNT_PRSInput_TypeDef prsInput,
318  bool enable)
319 {
320  EFM_ASSERT(PCNT_REF_VALID(pcnt));
321 
322  /* Enable/disable the selected PRS input on the selected PCNT module. */
323  switch (prsInput)
324  {
325  /* Enable/disable PRS input S0. */
326  case pcntPRSInputS0:
327  BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, enable);
328  break;
329 
330  /* Enable/disable PRS input S1. */
331  case pcntPRSInputS1:
332  BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S1PRSEN_SHIFT, enable);
333  break;
334 
335  /* Invalid parameter, asserted. */
336  default:
337  EFM_ASSERT(0);
338  break;
339  }
340 }
341 #endif
342 
343 
344 /***************************************************************************/
371 void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable)
372 {
373  EFM_ASSERT(PCNT_REF_VALID(pcnt));
374 
375  if (enable)
376  {
377  /* Wait for any ongoing LF synchronization to complete. This is just to
378  * protect against the rare case when a user:
379  * - modifies a register requiring LF sync
380  * - then enables freeze before LF sync completed
381  * - then modifies the same register again
382  * since modifying a register while it is in sync progress should be
383  * avoided. */
384  while (pcnt->SYNCBUSY)
385  ;
386 
388  }
389  else
390  {
391  pcnt->FREEZE = 0;
392  }
393 }
394 
395 
396 /***************************************************************************/
435 void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
436 {
437  unsigned int inst;
438  uint32_t tmp;
439 
440  EFM_ASSERT(PCNT_REF_VALID(pcnt));
441 
442 #ifdef PCNT0
443  if (PCNT0 == pcnt)
444  {
445  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > init->counter);
446  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > init->top);
447  }
448 #endif
449 
450 #ifdef PCNT1
451  if (PCNT1 == pcnt)
452  {
453  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->counter);
454  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->top);
455  }
456 #endif
457 
458 #ifdef PCNT2
459  if (PCNT2 == pcnt)
460  {
461  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->counter);
462  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->top);
463  }
464 #endif
465 
466  /* Map pointer to instance */
467  inst = PCNT_Map(pcnt);
468 
469 #if defined(_PCNT_INPUT_MASK)
470  /* Selecting the PRS channels for the PRS input sources of the PCNT. These are
471  * written with a Read-Modify-Write sequence in order to keep the value of the
472  * input enable bits which can be modified using PCNT_PRSInputEnable(). */
473  tmp = pcnt->INPUT & ~(_PCNT_INPUT_S0PRSSEL_MASK | _PCNT_INPUT_S1PRSSEL_MASK);
474  tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT) |
475  ((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT);
476  pcnt->INPUT = tmp;
477 #endif
478 
479  /* Build CTRL setting, except for mode */
480  tmp = 0;
481  if (init->negEdge)
482  {
483  tmp |= PCNT_CTRL_EDGE_NEG;
484  }
485 
486  if (init->countDown)
487  {
488  tmp |= PCNT_CTRL_CNTDIR_DOWN;
489  }
490 
491  if (init->filter)
492  {
493  tmp |= PCNT_CTRL_FILT;
494  }
495 
496 #if defined(PCNT_CTRL_HYST)
497  if (init->hyst)
498  {
499  tmp |= PCNT_CTRL_HYST;
500  }
501 #endif
502 
503 #if defined(PCNT_CTRL_S1CDIR)
504  if (init->s1CntDir)
505  {
506  tmp |= PCNT_CTRL_S1CDIR;
507  }
508 #endif
509 
510  /* Configure counter events for regular and auxiliary counter. */
511 #if defined(_PCNT_CTRL_CNTEV_SHIFT)
512  tmp |= init->cntEvent << _PCNT_CTRL_CNTEV_SHIFT;
513 #endif
514 
515 #if defined(_PCNT_CTRL_AUXCNTEV_SHIFT)
516  {
517  /* Modify the auxCntEvent value before writing to the AUXCNTEV field in
518  the CTRL register because the AUXCNTEV field values are different from
519  the CNTEV field values, and cntEvent and auxCntEvent are of the same type
520  PCNT_CntEvent_TypeDef.
521  */
522  uint32_t auxCntEventField = 0; /* Get rid of compiler warning. */
523  switch (init->auxCntEvent)
524  {
525  case pcntCntEventBoth:
526  auxCntEventField = pcntCntEventNone;
527  break;
528  case pcntCntEventNone:
529  auxCntEventField = pcntCntEventBoth;
530  break;
531  case pcntCntEventUp:
532  case pcntCntEventDown:
533  auxCntEventField = init->auxCntEvent;
534  break;
535  default:
536  /* Invalid parameter, asserted. */
537  EFM_ASSERT(0);
538  break;
539  }
540  tmp |= auxCntEventField << _PCNT_CTRL_AUXCNTEV_SHIFT;
541  }
542 #endif
543 
544  /* Reset pulse counter while changing clock source. The reset bit */
545  /* is asynchronous, we don't have to check for SYNCBUSY. */
547 
548  /* Select LFACLK to clock in control setting */
549  CMU_PCNTClockExternalSet(inst, false);
550 
551  /* Handling depends on whether using external clock or not. */
552  switch (init->mode)
553  {
554  case pcntModeExtSingle:
555  case pcntModeExtQuad:
556  tmp |= init->mode << _PCNT_CTRL_MODE_SHIFT;
557 
558  /* In most cases, the SYNCBUSY bit is set due to reset bit set, and waiting
559  * for asynchronous reset bit is strictly not necessary.
560  * But in theory, other operations on CTRL register may have been done
561  * outside this function, so wait. */
562  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
563 
564  /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing
565  * the clock source to an external clock */
566  pcnt->CTRL = PCNT_CTRL_RSTEN;
567 
568  /* Wait until CTRL write synchronized into LF domain. */
569  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
570 
571  /* Change to external clock BEFORE disabling reset */
572  CMU_PCNTClockExternalSet(inst, true);
573 
574  /* Write to TOPB. If using external clock TOPB will sync to TOP at the same
575  * time as the mode. This will insure that if the user chooses to count
576  * down, the first "countable" pulse will make CNT go to TOP and not 0xFF
577  * (default TOP value). */
578  pcnt->TOPB = init->top;
579 
580  /* This bit has no effect on rev. C and onwards parts - for compatibility */
581  pcnt->CMD = PCNT_CMD_LTOPBIM;
582 
583  /* Write the CTRL register with the configurations.
584  * This should be written after TOPB in the eventuality of a pulse between
585  * these two writes that would cause the CTRL register to be synced one
586  * clock cycle earlier than the TOPB. */
587  pcnt->CTRL = tmp;
588 
589  /* There are no syncs for TOP, CMD or CTRL because the clock rate is unknown
590  * and the program could stall
591  * These will be synced within 3 clock cycles of the external clock /
592  * For the same reason CNT cannot be written here. */
593  break;
594 
595  /* pcntModeDisable */
596  /* pcntModeOvsSingle */
597  default:
598  /* No need to set disabled mode if already disabled. */
600  {
601  /* Set control to disabled mode, leave reset on until ensured disabled.
602  * We don't need to wait for CTRL SYNCBUSY completion here, it was
603  * triggered by reset bit above, which is asynchronous. */
605 
606  /* Wait until CTRL write synchronized into LF domain before proceeding
607  * to disable reset. */
608  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
609  }
610 
611  /* Disable reset bit, counter should now be in disabled mode. */
613 
614  /* Set counter and top values as specified. */
615  PCNT_CounterTopSet(pcnt, init->counter, init->top);
616 
617  /* Enter oversampling mode if selected. */
618  if (init->mode == pcntModeOvsSingle)
619  {
620  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
621  pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT);
622  }
623  break;
624  }
625 }
626 
627 
628 /***************************************************************************/
645 {
646  unsigned int inst;
647 
648  EFM_ASSERT(PCNT_REF_VALID(pcnt));
649 
650  /* Map pointer to instance and clock info */
651  inst = PCNT_Map(pcnt);
652 
653  pcnt->IEN = _PCNT_IEN_RESETVALUE;
654 
655  /* Notice that special SYNCBUSY handling is not applicable for the RSTEN
656  * bit of the control register, so we don't need to wait for it when only
657  * modifying RSTEN. The SYNCBUSY bit will be set, leading to a
658  * synchronization in the LF domain, with in reality no changes to LF domain.
659  * Enable reset of CNT and TOP register. */
661 
662  /* Select LFACLK as default */
663  CMU_PCNTClockExternalSet(inst, false);
664 
666 
667  /* Reset CTRL leaving RSTEN set */
669 
670  /* Disable reset after CTRL reg has been synchronized */
671  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
673 
674  /* Clear pending interrupts */
675  pcnt->IFC = _PCNT_IFC_MASK;
676 
677  /* Do not reset route register, setting should be done independently */
678 }
679 
680 #if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
681 /***************************************************************************/
698 void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable) {
699  uint32_t ovscfg = 0;
700 
701  EFM_ASSERT(PCNT_REF_VALID(pcnt));
702 
703  /* Construct new filter setting value */
704  ovscfg = ((config->filtLen & _PCNT_OVSCFG_FILTLEN_MASK) << _PCNT_OVSCFG_FILTLEN_SHIFT)
705  | ((config->flutterrm & 0x1) << _PCNT_OVSCFG_FLUTTERRM_SHIFT);
706 
707  /* Set new configuration. LF register requires sync check before writing. */
708  PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG);
709  pcnt->OVSCFG = ovscfg;
710 
711 
712  /* Set new state of filter. LF register requires sync check before writing. */
713  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
714  if(enable)
715  {
716  pcnt->CTRL |= PCNT_CTRL_FILT;
717  }
718  else
719  {
720  pcnt->CTRL &= ~PCNT_CTRL_FILT;
721  }
722 }
723 #endif
724 
725 #if defined(PCNT_CTRL_TCCMODE_DEFAULT)
726 /***************************************************************************/
747 void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config){
748  uint32_t ctrl = 0;
749  uint32_t mask = _PCNT_CTRL_TCCMODE_MASK
750  | _PCNT_CTRL_TCCPRESC_MASK
751  | _PCNT_CTRL_TCCCOMP_MASK
752  | _PCNT_CTRL_PRSGATEEN_MASK
753  | _PCNT_CTRL_TCCPRSPOL_MASK
754  | _PCNT_CTRL_TCCPRSSEL_MASK;
755 
756  EFM_ASSERT(PCNT_REF_VALID(pcnt));
757 
758  /* construct TCC part of configuration register */
759  ctrl |= (config->mode << _PCNT_CTRL_TCCMODE_SHIFT ) & _PCNT_CTRL_TCCMODE_MASK;
760  ctrl |= (config->prescaler << _PCNT_CTRL_TCCPRESC_SHIFT ) & _PCNT_CTRL_TCCPRESC_MASK;
761  ctrl |= (config->compare << _PCNT_CTRL_TCCCOMP_SHIFT ) & _PCNT_CTRL_TCCCOMP_MASK;
762  ctrl |= (config->tccPRS << _PCNT_CTRL_TCCPRSSEL_SHIFT ) & _PCNT_CTRL_TCCPRSSEL_MASK;
763  ctrl |= (config->prsPolarity << _PCNT_CTRL_TCCPRSPOL_SHIFT ) & _PCNT_CTRL_TCCPRSPOL_MASK;
764  ctrl |= (config->prsGateEnable << _PCNT_CTRL_PRSGATEEN_SHIFT ) & _PCNT_CTRL_PRSGATEEN_MASK;
765 
766  /* Load new TCC config to PCNT. LF register requires sync check before write. */
767  PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL);
768  pcnt->CTRL = (pcnt->CTRL & (~mask)) | ctrl;
769 }
770 #endif
771 
772 /***************************************************************************/
788 void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val)
789 {
790  EFM_ASSERT(PCNT_REF_VALID(pcnt));
791 
792  /* LF register about to be modified require sync. busy check */
793  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB);
794  pcnt->TOPB = val;
795 }
796 
797 
798 /***************************************************************************/
814 void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val)
815 {
816  EFM_ASSERT(PCNT_REF_VALID(pcnt));
817 
818 #ifdef PCNT0
819  if (PCNT0 == pcnt)
820  {
821  EFM_ASSERT((1<<PCNT0_CNT_SIZE) > val);
822  }
823 #endif
824 
825 #ifdef PCNT1
826  if (PCNT1 == pcnt)
827  {
828  EFM_ASSERT((1<<PCNT1_CNT_SIZE) > val);
829  }
830 #endif
831 
832 #ifdef PCNT2
833  if (PCNT2 == pcnt)
834  {
835  EFM_ASSERT((1<<PCNT2_CNT_SIZE) > val);
836  }
837 #endif
838 
839  /* LF register about to be modified require sync. busy check */
840 
841  /* Load into TOPB */
842  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB);
843  pcnt->TOPB = val;
844 
845  /* Load TOPB value into TOP */
846  PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD);
847  pcnt->CMD = PCNT_CMD_LTOPBIM;
848 }
849 
852 #endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */
Clock management unit (CMU) API.
#define PCNT0
#define PCNT_SYNCBUSY_CTRL
Definition: efm32g_pcnt.h:265
#define _PCNT_CTRL_RESETVALUE
Definition: efm32g_pcnt.h:65
void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
Set counter and top values.
Definition: em_pcnt.c:182
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
Definition: em_cmu.c:4061
#define PCNT2_CNT_SIZE
Definition: em_pcnt.h:72
#define _PCNT_CTRL_MODE_MASK
Definition: efm32g_pcnt.h:68
#define PCNT_FREEZE_REGFREEZE
Definition: efm32g_pcnt.h:252
void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode)
Set PCNT operational mode.
Definition: em_pcnt.c:284
Emlib peripheral API "assert" implementation.
#define _PCNT_CTRL_RSTEN_SHIFT
Definition: efm32g_pcnt.h:103
RAM and peripheral bit-field set and clear API.
__IOM uint32_t IFC
Definition: efm32g_pcnt.h:51
void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val)
Set top value.
Definition: em_pcnt.c:814
__IOM uint32_t CMD
Definition: efm32g_pcnt.h:44
__IM uint32_t SYNCBUSY
Definition: efm32g_pcnt.h:56
#define PCNT0_BASE
#define _PCNT_CTRL_MODE_SHIFT
Definition: efm32g_pcnt.h:67
Pulse Counter (PCNT) peripheral API.
#define PCNT_CTRL_CNTDIR_DOWN
Definition: efm32g_pcnt.h:87
#define PCNT_CTRL_EDGE_NEG
Definition: efm32g_pcnt.h:96
#define PCNT_CTRL_MODE_DISABLE
Definition: efm32g_pcnt.h:75
#define PCNT1_CNT_SIZE
Definition: em_pcnt.h:67
uint32_t counter
Definition: em_pcnt.h:187
#define _PCNT_IEN_RESETVALUE
Definition: efm32g_pcnt.h:217
__IOM uint32_t TOPB
Definition: efm32g_pcnt.h:48
uint32_t top
Definition: em_pcnt.h:193
PCNT_Mode_TypeDef
Definition: em_pcnt.h:81
void PCNT_CounterReset(PCNT_TypeDef *pcnt)
Reset PCNT counters and TOP register.
Definition: em_pcnt.c:146
void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
Init pulse counter.
Definition: em_pcnt.c:435
#define PCNT1
#define PCNT0_CNT_SIZE
Definition: em_pcnt.h:60
void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val)
Set top buffer value.
Definition: em_pcnt.c:788
#define PCNT_CTRL_FILT
Definition: efm32g_pcnt.h:97
#define _PCNT_TOPB_RESETVALUE
Definition: efm32g_pcnt.h:152
#define PCNT2
__IOM uint32_t CTRL
Definition: efm32g_pcnt.h:43
void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable)
PCNT register synchronization freeze control.
Definition: em_pcnt.c:371
__IOM uint32_t FREEZE
Definition: efm32g_pcnt.h:55
#define PCNT_CMD_LTOPBIM
Definition: efm32g_pcnt.h:116
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148
#define _PCNT_IFC_MASK
Definition: efm32g_pcnt.h:199
#define PCNT_CMD_LCNTIM
Definition: efm32g_pcnt.h:111
#define PCNT_SYNCBUSY_TOPB
Definition: efm32g_pcnt.h:275
PCNT_Mode_TypeDef mode
Definition: em_pcnt.h:181
void PCNT_Reset(PCNT_TypeDef *pcnt)
Reset PCNT to same state as after a HW reset.
Definition: em_pcnt.c:644
#define PCNT_CTRL_RSTEN
Definition: efm32g_pcnt.h:102
#define PCNT_SYNCBUSY_CMD
Definition: efm32g_pcnt.h:270
__IOM uint32_t IEN
Definition: efm32g_pcnt.h:52