CPU Section

The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.

<cpu>
    <name>cpuNameType</name>
    <revision>revisionType</revision>
    <endian>endianType</endian>
    <mpuPresent>xs:boolean</mpuPresent>
    <fpuPresent>xs:boolean</fpuPresent>
    <fpuDP>xs:boolean</fpuDP>
    <icachePresent>xs:boolean</icachePresent>
    <dcachePresent>xs:boolean</dcachePresent>
    <itcmPresent>xs:boolean</itcmPresent>
    <dtcmPresent>xs:boolean</dtcmPresent>
    <vtorPresent>xs:boolean</vtorPresent>
    <nvicPrioBits>scaledNonNegativeInteger</nvicPrioBits>
    <vendorSystickConfig>xs:boolean</vendorSystickConfig>
    <deviceNumInterrupts>scaledNonNegativeInteger<deviceNumInterrupts>
    <sauNumRegions>scaledNonNegativeInteger</sauRegions>
    <sauRegionsConfig>sauRegionsConfigType</sauRegionsConfig>
    
</cpu>

Element Name	Description	Type	Occurrence
name	The predefined tokens are: CM0: ARM Cortex-M0 CM0PLUS: ARM Cortex-M0+ CM3: ARM Cortex-M3 CM4: ARM Cortex-M4 CM7: ARM Cortex-M7 SC000: ARM Secure Core SC000 SC300: ARM Secure Core SC300 other: other processor architectures	cpuNameType	1..1
revisionType	Defines the HW revision of the processor. The defined version format is rNpM (N,M = [0 - 9]).	revisionType	1..1
endian	Defines the endianess of the processor being one of: little: little endian memory (least significant byte gets allocated at the lowest address). big: byte invariant big endian data organization (most significant byte gets allocated at the lowest address). selectable: little and big endian are configurable for the device and become active after the next reset. other: the endianess is neither little nor big endian.	endianType	1..1
mpuPresent	Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to true or false, 1 or 0.	boolean	1..1
fpuPresent	Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 and Cortex-M7 are the only available Cortex-M processor with an optional FPU. This tag is either set to true or false, 1 or 0.	boolean	1..1
fpuDP	Indicates that the processor is equipped with a double precision floating point unit. Flag is only valid if fpuPresent is set true. Cortex-M7 is currently the only Cortex-M processor available with a double precision floating point unit.	boolean	0..1
icachePresent	Indicates that the processor has an instruction cache. Note: only an option for Cortex-M7 based devices.	boolean	0..1
dcachePresent	Indicates that the processor has an data cache. Note: only an option for Cortex-M7 based devices.	boolean	0..1
itcmPresent	Indicates that the processor has an instruction tightly coupled memory. Note: only an option for Cortex-M7 based devices.	boolean	0..1
dtcmPresent	Indicates that the processor has an data tightly coupled memory. Note: only an option for Cortex-M7 based devices.	boolean	0..1
vtorPresent	This is an optional flag used for the Cortex-M0+ based devices only. It indicates whether the Vector Table Offset Register (VTOR) is implemented in the Cortex-M0+ device or not. This tag is either set to true or false, 1 or 0. If it is not specified VTOR is assumed to be present.	boolean	1..1
nvicPrioBits	Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority.	scaledNonNegativeInteger	1..1
vendorSystickConfig	Indicates whether the processor implements a vendor-specific System Tick Timer. If false, then the ARM defined System Tick Timer is available. If true, then a vendor-specific System Tick Timer must be implemented. This tag is either set to true or false, 1 or 0.	boolean	1..1
deviceNumInterrupts	Specifies the total number of interrupts implemented by the device. This value can be used to validate the number of described interrupts	scaledNonNegativeInteger	0..1
sauNumRegions	If set and not zero this flag indicates that the device is equipped with a Security Attribution Unit (SAU) and the maximum number of available address regions.	scaledNonNegativeInteger	0..1
sauRegionsConfig	If the Secure Attribution Unit is preconfigured by HW or Firmware, the settings are described here. <sauRegionsConfig enabled=true protectionWhenDisabled="s"> <base>adddress</base>: SAU Region base adddress (type=scaledNonNegativeInteger) [1..1] <limit>address</limit>: SAU Region limit adddress (type=scaledNonNegativeInteger) [1..1] <access>flag</access>: one of "n" = non-secure or "c" = secure callable (type=string) [1..1] attribute: enabled = [true|false]: SAU Region is active (type=boolean) [0..1] attribute: name = [string]: brief name for identifying the SAU Region(type=string) [0..1] </sauRegionsConfig> attribute: enabled = [true|false]: enable/disable the complete SAU (type=boolean) [0..1] attribute: protectionWhenDisabled = [s|n]: if the complete SAU is disabled the whole memory is treated either "s" = secure or "n" non-secure - [0..1] (default="s")	SauRegionsConfigType	0..1

Example:

...
<cpu>
    <name>CM7</name> 
    <revision>r0p0</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <!-- has double precision FPU -->
    <fpuPresent>true</fpuPresent>
    <fpuDP>true</fpuDP>
    <!-- has instruction and data cache -->
    <icachePresent>true</icachePresent>
    <dcachePresent>true</dcachePresent>
    <!-- has no instruction nor data tighly coupled memory -->
    <itcmPresent>false</itcmPresent>
    <dtcmPresent>false</dtcmPresent>
    <nvicPrioBits>4</nvicPrioBits>
    <vendorSystickConfig>false</vendorSystickConfig> 
</cpu>
...

This example describes a device based on a Cortex-M7 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and double precision hardware Floating Point Unit. It has and instruction and a data cache but no Tightly Coupled Memories. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM.