Detailed Description

Macros
#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL

#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0

#define	_DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL

#define	_DMA_CH_CTRL_MASK 0x003F000FUL

#define	_DMA_CH_CTRL_RESETVALUE 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_MASK 0xFUL

#define	_DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_SHIFT 0

#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAV 0x00000000UL

#define	_DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAVRIGHT 0x00000003UL

#define	_DMA_CH_CTRL_SIGSEL_USARTRF1TXBL 0x00000001UL

#define	_DMA_CH_CTRL_SIGSEL_USARTRF1TXBLRIGHT 0x00000004UL

#define	_DMA_CH_CTRL_SIGSEL_USARTRF1TXEMPTY 0x00000002UL

#define	_DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL

#define	_DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL

#define	_DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL

#define	_DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL

#define	_DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL

#define	_DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL

#define	_DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL

#define	_DMA_CH_CTRL_SOURCESEL_SHIFT 16

#define	_DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL

#define	_DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL

#define	_DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL

#define	_DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL

#define	_DMA_CH_CTRL_SOURCESEL_USARTRF1 0x0000000DUL

#define	_DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH0ALTC_MASK 0x1UL

#define	_DMA_CHALTC_CH0ALTC_SHIFT 0

#define	_DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH1ALTC_MASK 0x2UL

#define	_DMA_CHALTC_CH1ALTC_SHIFT 1

#define	_DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH2ALTC_MASK 0x4UL

#define	_DMA_CHALTC_CH2ALTC_SHIFT 2

#define	_DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH3ALTC_MASK 0x8UL

#define	_DMA_CHALTC_CH3ALTC_SHIFT 3

#define	_DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH4ALTC_MASK 0x10UL

#define	_DMA_CHALTC_CH4ALTC_SHIFT 4

#define	_DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL

#define	_DMA_CHALTC_CH5ALTC_MASK 0x20UL

#define	_DMA_CHALTC_CH5ALTC_SHIFT 5

#define	_DMA_CHALTC_MASK 0x0000003FUL

#define	_DMA_CHALTC_RESETVALUE 0x00000000UL

#define	_DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH0ALTS_MASK 0x1UL

#define	_DMA_CHALTS_CH0ALTS_SHIFT 0

#define	_DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH1ALTS_MASK 0x2UL

#define	_DMA_CHALTS_CH1ALTS_SHIFT 1

#define	_DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH2ALTS_MASK 0x4UL

#define	_DMA_CHALTS_CH2ALTS_SHIFT 2

#define	_DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH3ALTS_MASK 0x8UL

#define	_DMA_CHALTS_CH3ALTS_SHIFT 3

#define	_DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH4ALTS_MASK 0x10UL

#define	_DMA_CHALTS_CH4ALTS_SHIFT 4

#define	_DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL

#define	_DMA_CHALTS_CH5ALTS_MASK 0x20UL

#define	_DMA_CHALTS_CH5ALTS_SHIFT 5

#define	_DMA_CHALTS_MASK 0x0000003FUL

#define	_DMA_CHALTS_RESETVALUE 0x00000000UL

#define	_DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH0ENC_MASK 0x1UL

#define	_DMA_CHENC_CH0ENC_SHIFT 0

#define	_DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH1ENC_MASK 0x2UL

#define	_DMA_CHENC_CH1ENC_SHIFT 1

#define	_DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH2ENC_MASK 0x4UL

#define	_DMA_CHENC_CH2ENC_SHIFT 2

#define	_DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH3ENC_MASK 0x8UL

#define	_DMA_CHENC_CH3ENC_SHIFT 3

#define	_DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH4ENC_MASK 0x10UL

#define	_DMA_CHENC_CH4ENC_SHIFT 4

#define	_DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL

#define	_DMA_CHENC_CH5ENC_MASK 0x20UL

#define	_DMA_CHENC_CH5ENC_SHIFT 5

#define	_DMA_CHENC_MASK 0x0000003FUL

#define	_DMA_CHENC_RESETVALUE 0x00000000UL

#define	_DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH0ENS_MASK 0x1UL

#define	_DMA_CHENS_CH0ENS_SHIFT 0

#define	_DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH1ENS_MASK 0x2UL

#define	_DMA_CHENS_CH1ENS_SHIFT 1

#define	_DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH2ENS_MASK 0x4UL

#define	_DMA_CHENS_CH2ENS_SHIFT 2

#define	_DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH3ENS_MASK 0x8UL

#define	_DMA_CHENS_CH3ENS_SHIFT 3

#define	_DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH4ENS_MASK 0x10UL

#define	_DMA_CHENS_CH4ENS_SHIFT 4

#define	_DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL

#define	_DMA_CHENS_CH5ENS_MASK 0x20UL

#define	_DMA_CHENS_CH5ENS_SHIFT 5

#define	_DMA_CHENS_MASK 0x0000003FUL

#define	_DMA_CHENS_RESETVALUE 0x00000000UL

#define	_DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH0PRIC_MASK 0x1UL

#define	_DMA_CHPRIC_CH0PRIC_SHIFT 0

#define	_DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH1PRIC_MASK 0x2UL

#define	_DMA_CHPRIC_CH1PRIC_SHIFT 1

#define	_DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH2PRIC_MASK 0x4UL

#define	_DMA_CHPRIC_CH2PRIC_SHIFT 2

#define	_DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH3PRIC_MASK 0x8UL

#define	_DMA_CHPRIC_CH3PRIC_SHIFT 3

#define	_DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH4PRIC_MASK 0x10UL

#define	_DMA_CHPRIC_CH4PRIC_SHIFT 4

#define	_DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL

#define	_DMA_CHPRIC_CH5PRIC_MASK 0x20UL

#define	_DMA_CHPRIC_CH5PRIC_SHIFT 5

#define	_DMA_CHPRIC_MASK 0x0000003FUL

#define	_DMA_CHPRIC_RESETVALUE 0x00000000UL

#define	_DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH0PRIS_MASK 0x1UL

#define	_DMA_CHPRIS_CH0PRIS_SHIFT 0

#define	_DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH1PRIS_MASK 0x2UL

#define	_DMA_CHPRIS_CH1PRIS_SHIFT 1

#define	_DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH2PRIS_MASK 0x4UL

#define	_DMA_CHPRIS_CH2PRIS_SHIFT 2

#define	_DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH3PRIS_MASK 0x8UL

#define	_DMA_CHPRIS_CH3PRIS_SHIFT 3

#define	_DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH4PRIS_MASK 0x10UL

#define	_DMA_CHPRIS_CH4PRIS_SHIFT 4

#define	_DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL

#define	_DMA_CHPRIS_CH5PRIS_MASK 0x20UL

#define	_DMA_CHPRIS_CH5PRIS_SHIFT 5

#define	_DMA_CHPRIS_MASK 0x0000003FUL

#define	_DMA_CHPRIS_RESETVALUE 0x00000000UL

#define	_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL

#define	_DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0

#define	_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL

#define	_DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1

#define	_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL

#define	_DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2

#define	_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL

#define	_DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3

#define	_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL

#define	_DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4

#define	_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL

#define	_DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5

#define	_DMA_CHREQMASKC_MASK 0x0000003FUL

#define	_DMA_CHREQMASKC_RESETVALUE 0x00000000UL

#define	_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL

#define	_DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0

#define	_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL

#define	_DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1

#define	_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL

#define	_DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2

#define	_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL

#define	_DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3

#define	_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL

#define	_DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4

#define	_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL

#define	_DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL

#define	_DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5

#define	_DMA_CHREQMASKS_MASK 0x0000003FUL

#define	_DMA_CHREQMASKS_RESETVALUE 0x00000000UL

#define	_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL

#define	_DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0

#define	_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL

#define	_DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1

#define	_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL

#define	_DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2

#define	_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL

#define	_DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3

#define	_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL

#define	_DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4

#define	_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL

#define	_DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5

#define	_DMA_CHREQSTATUS_MASK 0x0000003FUL

#define	_DMA_CHREQSTATUS_RESETVALUE 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL

#define	_DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0

#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL

#define	_DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1

#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL

#define	_DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2

#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL

#define	_DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3

#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL

#define	_DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4

#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL

#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL

#define	_DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5

#define	_DMA_CHSREQSTATUS_MASK 0x0000003FUL

#define	_DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL

#define	_DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL

#define	_DMA_CHSWREQ_CH0SWREQ_SHIFT 0

#define	_DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL

#define	_DMA_CHSWREQ_CH1SWREQ_SHIFT 1

#define	_DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL

#define	_DMA_CHSWREQ_CH2SWREQ_SHIFT 2

#define	_DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL

#define	_DMA_CHSWREQ_CH3SWREQ_SHIFT 3

#define	_DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL

#define	_DMA_CHSWREQ_CH4SWREQ_SHIFT 4

#define	_DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL

#define	_DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL

#define	_DMA_CHSWREQ_CH5SWREQ_SHIFT 5

#define	_DMA_CHSWREQ_MASK 0x0000003FUL

#define	_DMA_CHSWREQ_RESETVALUE 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL

#define	_DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0

#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL

#define	_DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1

#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL

#define	_DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2

#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL

#define	_DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3

#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL

#define	_DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4

#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL

#define	_DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5

#define	_DMA_CHUSEBURSTC_MASK 0x0000003FUL

#define	_DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0

#define	_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL

#define	_DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1

#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL

#define	_DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2

#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL

#define	_DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3

#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL

#define	_DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4

#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL

#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL

#define	_DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5

#define	_DMA_CHUSEBURSTS_MASK 0x0000003FUL

#define	_DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL

#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL

#define	_DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0

#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL

#define	_DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1

#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL

#define	_DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2

#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL

#define	_DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3

#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL

#define	_DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4

#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL

#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL

#define	_DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5

#define	_DMA_CHWAITSTATUS_MASK 0x0000003FUL

#define	_DMA_CHWAITSTATUS_RESETVALUE 0x0000003FUL

#define	_DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL

#define	_DMA_CONFIG_CHPROT_MASK 0x20UL

#define	_DMA_CONFIG_CHPROT_SHIFT 5

#define	_DMA_CONFIG_EN_DEFAULT 0x00000000UL

#define	_DMA_CONFIG_EN_MASK 0x1UL

#define	_DMA_CONFIG_EN_SHIFT 0

#define	_DMA_CONFIG_MASK 0x00000021UL

#define	_DMA_CONFIG_RESETVALUE 0x00000000UL

#define	_DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL

#define	_DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_CTRLBASE_CTRLBASE_SHIFT 0

#define	_DMA_CTRLBASE_MASK 0xFFFFFFFFUL

#define	_DMA_CTRLBASE_RESETVALUE 0x00000000UL

#define	_DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL

#define	_DMA_ERRORC_ERRORC_MASK 0x1UL

#define	_DMA_ERRORC_ERRORC_SHIFT 0

#define	_DMA_ERRORC_MASK 0x00000001UL

#define	_DMA_ERRORC_RESETVALUE 0x00000000UL

#define	_DMA_IEN_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH0DONE_MASK 0x1UL

#define	_DMA_IEN_CH0DONE_SHIFT 0

#define	_DMA_IEN_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH1DONE_MASK 0x2UL

#define	_DMA_IEN_CH1DONE_SHIFT 1

#define	_DMA_IEN_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH2DONE_MASK 0x4UL

#define	_DMA_IEN_CH2DONE_SHIFT 2

#define	_DMA_IEN_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH3DONE_MASK 0x8UL

#define	_DMA_IEN_CH3DONE_SHIFT 3

#define	_DMA_IEN_CH4DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH4DONE_MASK 0x10UL

#define	_DMA_IEN_CH4DONE_SHIFT 4

#define	_DMA_IEN_CH5DONE_DEFAULT 0x00000000UL

#define	_DMA_IEN_CH5DONE_MASK 0x20UL

#define	_DMA_IEN_CH5DONE_SHIFT 5

#define	_DMA_IEN_ERR_DEFAULT 0x00000000UL

#define	_DMA_IEN_ERR_MASK 0x80000000UL

#define	_DMA_IEN_ERR_SHIFT 31

#define	_DMA_IEN_MASK 0x8000003FUL

#define	_DMA_IEN_RESETVALUE 0x00000000UL

#define	_DMA_IF_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH0DONE_MASK 0x1UL

#define	_DMA_IF_CH0DONE_SHIFT 0

#define	_DMA_IF_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH1DONE_MASK 0x2UL

#define	_DMA_IF_CH1DONE_SHIFT 1

#define	_DMA_IF_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH2DONE_MASK 0x4UL

#define	_DMA_IF_CH2DONE_SHIFT 2

#define	_DMA_IF_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH3DONE_MASK 0x8UL

#define	_DMA_IF_CH3DONE_SHIFT 3

#define	_DMA_IF_CH4DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH4DONE_MASK 0x10UL

#define	_DMA_IF_CH4DONE_SHIFT 4

#define	_DMA_IF_CH5DONE_DEFAULT 0x00000000UL

#define	_DMA_IF_CH5DONE_MASK 0x20UL

#define	_DMA_IF_CH5DONE_SHIFT 5

#define	_DMA_IF_ERR_DEFAULT 0x00000000UL

#define	_DMA_IF_ERR_MASK 0x80000000UL

#define	_DMA_IF_ERR_SHIFT 31

#define	_DMA_IF_MASK 0x8000003FUL

#define	_DMA_IF_RESETVALUE 0x00000000UL

#define	_DMA_IFC_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH0DONE_MASK 0x1UL

#define	_DMA_IFC_CH0DONE_SHIFT 0

#define	_DMA_IFC_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH1DONE_MASK 0x2UL

#define	_DMA_IFC_CH1DONE_SHIFT 1

#define	_DMA_IFC_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH2DONE_MASK 0x4UL

#define	_DMA_IFC_CH2DONE_SHIFT 2

#define	_DMA_IFC_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH3DONE_MASK 0x8UL

#define	_DMA_IFC_CH3DONE_SHIFT 3

#define	_DMA_IFC_CH4DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH4DONE_MASK 0x10UL

#define	_DMA_IFC_CH4DONE_SHIFT 4

#define	_DMA_IFC_CH5DONE_DEFAULT 0x00000000UL

#define	_DMA_IFC_CH5DONE_MASK 0x20UL

#define	_DMA_IFC_CH5DONE_SHIFT 5

#define	_DMA_IFC_ERR_DEFAULT 0x00000000UL

#define	_DMA_IFC_ERR_MASK 0x80000000UL

#define	_DMA_IFC_ERR_SHIFT 31

#define	_DMA_IFC_MASK 0x8000003FUL

#define	_DMA_IFC_RESETVALUE 0x00000000UL

#define	_DMA_IFS_CH0DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH0DONE_MASK 0x1UL

#define	_DMA_IFS_CH0DONE_SHIFT 0

#define	_DMA_IFS_CH1DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH1DONE_MASK 0x2UL

#define	_DMA_IFS_CH1DONE_SHIFT 1

#define	_DMA_IFS_CH2DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH2DONE_MASK 0x4UL

#define	_DMA_IFS_CH2DONE_SHIFT 2

#define	_DMA_IFS_CH3DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH3DONE_MASK 0x8UL

#define	_DMA_IFS_CH3DONE_SHIFT 3

#define	_DMA_IFS_CH4DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH4DONE_MASK 0x10UL

#define	_DMA_IFS_CH4DONE_SHIFT 4

#define	_DMA_IFS_CH5DONE_DEFAULT 0x00000000UL

#define	_DMA_IFS_CH5DONE_MASK 0x20UL

#define	_DMA_IFS_CH5DONE_SHIFT 5

#define	_DMA_IFS_ERR_DEFAULT 0x00000000UL

#define	_DMA_IFS_ERR_MASK 0x80000000UL

#define	_DMA_IFS_ERR_SHIFT 31

#define	_DMA_IFS_MASK 0x8000003FUL

#define	_DMA_IFS_RESETVALUE 0x00000000UL

#define	_DMA_STATUS_CHNUM_DEFAULT 0x00000005UL

#define	_DMA_STATUS_CHNUM_MASK 0x1F0000UL

#define	_DMA_STATUS_CHNUM_SHIFT 16

#define	_DMA_STATUS_EN_DEFAULT 0x00000000UL

#define	_DMA_STATUS_EN_MASK 0x1UL

#define	_DMA_STATUS_EN_SHIFT 0

#define	_DMA_STATUS_MASK 0x001F00F1UL

#define	_DMA_STATUS_RESETVALUE 0x10050000UL

#define	_DMA_STATUS_STATE_DEFAULT 0x00000000UL

#define	_DMA_STATUS_STATE_DONE 0x00000009UL

#define	_DMA_STATUS_STATE_IDLE 0x00000000UL

#define	_DMA_STATUS_STATE_MASK 0xF0UL

#define	_DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL

#define	_DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL

#define	_DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL

#define	_DMA_STATUS_STATE_RDSRCDATA 0x00000004UL

#define	_DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL

#define	_DMA_STATUS_STATE_SHIFT 4

#define	_DMA_STATUS_STATE_STALLED 0x00000008UL

#define	_DMA_STATUS_STATE_WAITREQCLR 0x00000006UL

#define	_DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL

#define	_DMA_STATUS_STATE_WRDSTDATA 0x00000005UL

#define	DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)

#define	DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)

#define	DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)

#define	DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)

#define	DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)

#define	DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)

#define	DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)

#define	DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)

#define	DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)

#define	DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)

#define	DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)

#define	DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAV (_DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAV << 0)

#define	DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAVRIGHT << 0)

#define	DMA_CH_CTRL_SIGSEL_USARTRF1TXBL (_DMA_CH_CTRL_SIGSEL_USARTRF1TXBL << 0)

#define	DMA_CH_CTRL_SIGSEL_USARTRF1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USARTRF1TXBLRIGHT << 0)

#define	DMA_CH_CTRL_SIGSEL_USARTRF1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USARTRF1TXEMPTY << 0)

#define	DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16)

#define	DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)

#define	DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)

#define	DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)

#define	DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)

#define	DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)

#define	DMA_CH_CTRL_SOURCESEL_USARTRF1 (_DMA_CH_CTRL_SOURCESEL_USARTRF1 << 16)

#define	DMA_CHALTC_CH0ALTC (0x1UL << 0)

#define	DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)

#define	DMA_CHALTC_CH1ALTC (0x1UL << 1)

#define	DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)

#define	DMA_CHALTC_CH2ALTC (0x1UL << 2)

#define	DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)

#define	DMA_CHALTC_CH3ALTC (0x1UL << 3)

#define	DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)

#define	DMA_CHALTC_CH4ALTC (0x1UL << 4)

#define	DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)

#define	DMA_CHALTC_CH5ALTC (0x1UL << 5)

#define	DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)

#define	DMA_CHALTS_CH0ALTS (0x1UL << 0)

#define	DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)

#define	DMA_CHALTS_CH1ALTS (0x1UL << 1)

#define	DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)

#define	DMA_CHALTS_CH2ALTS (0x1UL << 2)

#define	DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)

#define	DMA_CHALTS_CH3ALTS (0x1UL << 3)

#define	DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)

#define	DMA_CHALTS_CH4ALTS (0x1UL << 4)

#define	DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)

#define	DMA_CHALTS_CH5ALTS (0x1UL << 5)

#define	DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)

#define	DMA_CHENC_CH0ENC (0x1UL << 0)

#define	DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)

#define	DMA_CHENC_CH1ENC (0x1UL << 1)

#define	DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)

#define	DMA_CHENC_CH2ENC (0x1UL << 2)

#define	DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)

#define	DMA_CHENC_CH3ENC (0x1UL << 3)

#define	DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)

#define	DMA_CHENC_CH4ENC (0x1UL << 4)

#define	DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4)

#define	DMA_CHENC_CH5ENC (0x1UL << 5)

#define	DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5)

#define	DMA_CHENS_CH0ENS (0x1UL << 0)

#define	DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)

#define	DMA_CHENS_CH1ENS (0x1UL << 1)

#define	DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)

#define	DMA_CHENS_CH2ENS (0x1UL << 2)

#define	DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)

#define	DMA_CHENS_CH3ENS (0x1UL << 3)

#define	DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)

#define	DMA_CHENS_CH4ENS (0x1UL << 4)

#define	DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4)

#define	DMA_CHENS_CH5ENS (0x1UL << 5)

#define	DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5)

#define	DMA_CHPRIC_CH0PRIC (0x1UL << 0)

#define	DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)

#define	DMA_CHPRIC_CH1PRIC (0x1UL << 1)

#define	DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)

#define	DMA_CHPRIC_CH2PRIC (0x1UL << 2)

#define	DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)

#define	DMA_CHPRIC_CH3PRIC (0x1UL << 3)

#define	DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)

#define	DMA_CHPRIC_CH4PRIC (0x1UL << 4)

#define	DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)

#define	DMA_CHPRIC_CH5PRIC (0x1UL << 5)

#define	DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)

#define	DMA_CHPRIS_CH0PRIS (0x1UL << 0)

#define	DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)

#define	DMA_CHPRIS_CH1PRIS (0x1UL << 1)

#define	DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)

#define	DMA_CHPRIS_CH2PRIS (0x1UL << 2)

#define	DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)

#define	DMA_CHPRIS_CH3PRIS (0x1UL << 3)

#define	DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)

#define	DMA_CHPRIS_CH4PRIS (0x1UL << 4)

#define	DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)

#define	DMA_CHPRIS_CH5PRIS (0x1UL << 5)

#define	DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)

#define	DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)

#define	DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)

#define	DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)

#define	DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)

#define	DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)

#define	DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)

#define	DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)

#define	DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)

#define	DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4)

#define	DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)

#define	DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5)

#define	DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)

#define	DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)

#define	DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)

#define	DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)

#define	DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)

#define	DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)

#define	DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)

#define	DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)

#define	DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)

#define	DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4)

#define	DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)

#define	DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5)

#define	DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)

#define	DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)

#define	DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)

#define	DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)

#define	DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)

#define	DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)

#define	DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)

#define	DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)

#define	DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)

#define	DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4)

#define	DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)

#define	DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5)

#define	DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)

#define	DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)

#define	DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)

#define	DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)

#define	DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)

#define	DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)

#define	DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)

#define	DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)

#define	DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)

#define	DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4)

#define	DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)

#define	DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5)

#define	DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)

#define	DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)

#define	DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)

#define	DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)

#define	DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)

#define	DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)

#define	DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)

#define	DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)

#define	DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)

#define	DMA_CHSWREQ_CH4SWREQ (0x1UL << 4)

#define	DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)

#define	DMA_CHSWREQ_CH5SWREQ (0x1UL << 5)

#define	DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)

#define	DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)

#define	DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)

#define	DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)

#define	DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)

#define	DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)

#define	DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)

#define	DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)

#define	DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)

#define	DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4)

#define	DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)

#define	DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5)

#define	DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)

#define	DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)

#define	DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)

#define	DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)

#define	DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)

#define	DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)

#define	DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)

#define	DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)

#define	DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4)

#define	DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)

#define	DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5)

#define	DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)

#define	DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)

#define	DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)

#define	DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)

#define	DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)

#define	DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)

#define	DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)

#define	DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)

#define	DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)

#define	DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4)

#define	DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)

#define	DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5)

#define	DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)

#define	DMA_CONFIG_CHPROT (0x1UL << 5)

#define	DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)

#define	DMA_CONFIG_EN (0x1UL << 0)

#define	DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)

#define	DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)

#define	DMA_ERRORC_ERRORC (0x1UL << 0)

#define	DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)

#define	DMA_IEN_CH0DONE (0x1UL << 0)

#define	DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)

#define	DMA_IEN_CH1DONE (0x1UL << 1)

#define	DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)

#define	DMA_IEN_CH2DONE (0x1UL << 2)

#define	DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)

#define	DMA_IEN_CH3DONE (0x1UL << 3)

#define	DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)

#define	DMA_IEN_CH4DONE (0x1UL << 4)

#define	DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4)

#define	DMA_IEN_CH5DONE (0x1UL << 5)

#define	DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5)

#define	DMA_IEN_ERR (0x1UL << 31)

#define	DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)

#define	DMA_IF_CH0DONE (0x1UL << 0)

#define	DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)

#define	DMA_IF_CH1DONE (0x1UL << 1)

#define	DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)

#define	DMA_IF_CH2DONE (0x1UL << 2)

#define	DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)

#define	DMA_IF_CH3DONE (0x1UL << 3)

#define	DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)

#define	DMA_IF_CH4DONE (0x1UL << 4)

#define	DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4)

#define	DMA_IF_CH5DONE (0x1UL << 5)

#define	DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5)

#define	DMA_IF_ERR (0x1UL << 31)

#define	DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)

#define	DMA_IFC_CH0DONE (0x1UL << 0)

#define	DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)

#define	DMA_IFC_CH1DONE (0x1UL << 1)

#define	DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)

#define	DMA_IFC_CH2DONE (0x1UL << 2)

#define	DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)

#define	DMA_IFC_CH3DONE (0x1UL << 3)

#define	DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)

#define	DMA_IFC_CH4DONE (0x1UL << 4)

#define	DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4)

#define	DMA_IFC_CH5DONE (0x1UL << 5)

#define	DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5)

#define	DMA_IFC_ERR (0x1UL << 31)

#define	DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)

#define	DMA_IFS_CH0DONE (0x1UL << 0)

#define	DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)

#define	DMA_IFS_CH1DONE (0x1UL << 1)

#define	DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1)

#define	DMA_IFS_CH2DONE (0x1UL << 2)

#define	DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2)

#define	DMA_IFS_CH3DONE (0x1UL << 3)

#define	DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3)

#define	DMA_IFS_CH4DONE (0x1UL << 4)

#define	DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4)

#define	DMA_IFS_CH5DONE (0x1UL << 5)

#define	DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5)

#define	DMA_IFS_ERR (0x1UL << 31)

#define	DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31)

#define	DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16)

#define	DMA_STATUS_EN (0x1UL << 0)

#define	DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0)

#define	DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4)

#define	DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4)

#define	DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4)

#define	DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4)

#define	DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)

#define	DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4)

#define	DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4)

#define	DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4)

#define	DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4)

#define	DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4)

#define	DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)

#define	DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4)

Macro Definition Documentation

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL

Mode DEFAULT for DMA_ALTCTRLBASE

Definition at line 148 of file ezr32hg_dma.h.

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL

Bit mask for DMA_ALTCTRLBASE

Definition at line 147 of file ezr32hg_dma.h.

#define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0

Shift value for DMA_ALTCTRLBASE

Definition at line 146 of file ezr32hg_dma.h.

#define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL

Mask for DMA_ALTCTRLBASE

Definition at line 145 of file ezr32hg_dma.h.

#define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL

Default value for DMA_ALTCTRLBASE

Definition at line 144 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_MASK 0x003F000FUL

Mask for DMA_CH_CTRL

Definition at line 798 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_RESETVALUE 0x00000000UL

Default value for DMA_CH_CTRL

Definition at line 797 of file ezr32hg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL

Mode ADC0SCAN for DMA_CH_CTRL

Definition at line 811 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL

Mode ADC0SINGLE for DMA_CH_CTRL

Definition at line 801 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL

Mode AESDATARD for DMA_CH_CTRL

Definition at line 826 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL

Mode AESDATAWR for DMA_CH_CTRL

Definition at line 810 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL

Mode AESKEYWR for DMA_CH_CTRL

Definition at line 831 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL

Mode AESXORDATAWR for DMA_CH_CTRL

Definition at line 819 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL

Mode I2C0RXDATAV for DMA_CH_CTRL

Definition at line 805 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL

Mode I2C0TXBL for DMA_CH_CTRL

Definition at line 815 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL

Mode LEUART0RXDATAV for DMA_CH_CTRL

Definition at line 804 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL

Mode LEUART0TXBL for DMA_CH_CTRL

Definition at line 814 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL

Mode LEUART0TXEMPTY for DMA_CH_CTRL

Definition at line 822 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL

Bit mask for DMA_SIGSEL

Definition at line 800 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL

Mode MSCWDATA for DMA_CH_CTRL

Definition at line 809 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_SHIFT 0

Shift value for DMA_SIGSEL

Definition at line 799 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL

Mode TIMER0CC0 for DMA_CH_CTRL

Definition at line 816 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL

Mode TIMER0CC1 for DMA_CH_CTRL

Definition at line 823 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL

Mode TIMER0CC2 for DMA_CH_CTRL

Definition at line 828 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL

Mode TIMER0UFOF for DMA_CH_CTRL

Definition at line 806 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL

Mode TIMER1CC0 for DMA_CH_CTRL

Definition at line 817 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL

Mode TIMER1CC1 for DMA_CH_CTRL

Definition at line 824 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL

Mode TIMER1CC2 for DMA_CH_CTRL

Definition at line 829 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL

Mode TIMER1UFOF for DMA_CH_CTRL

Definition at line 807 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL

Mode TIMER2CC0 for DMA_CH_CTRL

Definition at line 818 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL

Mode TIMER2CC1 for DMA_CH_CTRL

Definition at line 825 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL

Mode TIMER2CC2 for DMA_CH_CTRL

Definition at line 830 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL

Mode TIMER2UFOF for DMA_CH_CTRL

Definition at line 808 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL

Mode USART0RXDATAV for DMA_CH_CTRL

Definition at line 802 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL

Mode USART0TXBL for DMA_CH_CTRL

Definition at line 812 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL

Mode USART0TXEMPTY for DMA_CH_CTRL

Definition at line 820 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAV 0x00000000UL

Mode USARTRF1RXDATAV for DMA_CH_CTRL

Definition at line 803 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAVRIGHT 0x00000003UL

Mode USARTRF1RXDATAVRIGHT for DMA_CH_CTRL

Definition at line 827 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USARTRF1TXBL 0x00000001UL

Mode USARTRF1TXBL for DMA_CH_CTRL

Definition at line 813 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USARTRF1TXBLRIGHT 0x00000004UL

Mode USARTRF1TXBLRIGHT for DMA_CH_CTRL

Definition at line 832 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SIGSEL_USARTRF1TXEMPTY 0x00000002UL

Mode USARTRF1TXEMPTY for DMA_CH_CTRL

Definition at line 821 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL

Mode ADC0 for DMA_CH_CTRL

Definition at line 868 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL

Mode AES for DMA_CH_CTRL

Definition at line 877 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL

Mode I2C0 for DMA_CH_CTRL

Definition at line 872 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL

Mode LEUART0 for DMA_CH_CTRL

Definition at line 871 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL

Bit mask for DMA_SOURCESEL

Definition at line 866 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL

Mode MSC for DMA_CH_CTRL

Definition at line 876 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL

Mode NONE for DMA_CH_CTRL

Definition at line 867 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_SHIFT 16

Shift value for DMA_SOURCESEL

Definition at line 865 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL

Mode TIMER0 for DMA_CH_CTRL

Definition at line 873 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL

Mode TIMER1 for DMA_CH_CTRL

Definition at line 874 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL

Mode TIMER2 for DMA_CH_CTRL

Definition at line 875 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL

Mode USART0 for DMA_CH_CTRL

Definition at line 869 of file ezr32hg_dma.h.

#define _DMA_CH_CTRL_SOURCESEL_USARTRF1 0x0000000DUL

Mode USARTRF1 for DMA_CH_CTRL

Definition at line 870 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 467 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH0ALTC_MASK 0x1UL

Bit mask for DMA_CH0ALTC

Definition at line 466 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH0ALTC_SHIFT 0

Shift value for DMA_CH0ALTC

Definition at line 465 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 472 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH1ALTC_MASK 0x2UL

Bit mask for DMA_CH1ALTC

Definition at line 471 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH1ALTC_SHIFT 1

Shift value for DMA_CH1ALTC

Definition at line 470 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 477 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH2ALTC_MASK 0x4UL

Bit mask for DMA_CH2ALTC

Definition at line 476 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH2ALTC_SHIFT 2

Shift value for DMA_CH2ALTC

Definition at line 475 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 482 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH3ALTC_MASK 0x8UL

Bit mask for DMA_CH3ALTC

Definition at line 481 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH3ALTC_SHIFT 3

Shift value for DMA_CH3ALTC

Definition at line 480 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 487 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH4ALTC_MASK 0x10UL

Bit mask for DMA_CH4ALTC

Definition at line 486 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH4ALTC_SHIFT 4

Shift value for DMA_CH4ALTC

Definition at line 485 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTC

Definition at line 492 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH5ALTC_MASK 0x20UL

Bit mask for DMA_CH5ALTC

Definition at line 491 of file ezr32hg_dma.h.

#define _DMA_CHALTC_CH5ALTC_SHIFT 5

Shift value for DMA_CH5ALTC

Definition at line 490 of file ezr32hg_dma.h.

#define _DMA_CHALTC_MASK 0x0000003FUL

Mask for DMA_CHALTC

Definition at line 463 of file ezr32hg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHALTC_RESETVALUE 0x00000000UL

Default value for DMA_CHALTC

Definition at line 462 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 433 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH0ALTS_MASK 0x1UL

Bit mask for DMA_CH0ALTS

Definition at line 432 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH0ALTS_SHIFT 0

Shift value for DMA_CH0ALTS

Definition at line 431 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 438 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH1ALTS_MASK 0x2UL

Bit mask for DMA_CH1ALTS

Definition at line 437 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH1ALTS_SHIFT 1

Shift value for DMA_CH1ALTS

Definition at line 436 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 443 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH2ALTS_MASK 0x4UL

Bit mask for DMA_CH2ALTS

Definition at line 442 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH2ALTS_SHIFT 2

Shift value for DMA_CH2ALTS

Definition at line 441 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 448 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH3ALTS_MASK 0x8UL

Bit mask for DMA_CH3ALTS

Definition at line 447 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH3ALTS_SHIFT 3

Shift value for DMA_CH3ALTS

Definition at line 446 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 453 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH4ALTS_MASK 0x10UL

Bit mask for DMA_CH4ALTS

Definition at line 452 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH4ALTS_SHIFT 4

Shift value for DMA_CH4ALTS

Definition at line 451 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHALTS

Definition at line 458 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH5ALTS_MASK 0x20UL

Bit mask for DMA_CH5ALTS

Definition at line 457 of file ezr32hg_dma.h.

#define _DMA_CHALTS_CH5ALTS_SHIFT 5

Shift value for DMA_CH5ALTS

Definition at line 456 of file ezr32hg_dma.h.

#define _DMA_CHALTS_MASK 0x0000003FUL

Mask for DMA_CHALTS

Definition at line 429 of file ezr32hg_dma.h.

#define _DMA_CHALTS_RESETVALUE 0x00000000UL

Default value for DMA_CHALTS

Definition at line 428 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 399 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH0ENC_MASK 0x1UL

Bit mask for DMA_CH0ENC

Definition at line 398 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH0ENC_SHIFT 0

Shift value for DMA_CH0ENC

Definition at line 397 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 404 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH1ENC_MASK 0x2UL

Bit mask for DMA_CH1ENC

Definition at line 403 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH1ENC_SHIFT 1

Shift value for DMA_CH1ENC

Definition at line 402 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 409 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH2ENC_MASK 0x4UL

Bit mask for DMA_CH2ENC

Definition at line 408 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH2ENC_SHIFT 2

Shift value for DMA_CH2ENC

Definition at line 407 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 414 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH3ENC_MASK 0x8UL

Bit mask for DMA_CH3ENC

Definition at line 413 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH3ENC_SHIFT 3

Shift value for DMA_CH3ENC

Definition at line 412 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 419 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH4ENC_MASK 0x10UL

Bit mask for DMA_CH4ENC

Definition at line 418 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH4ENC_SHIFT 4

Shift value for DMA_CH4ENC

Definition at line 417 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENC

Definition at line 424 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH5ENC_MASK 0x20UL

Bit mask for DMA_CH5ENC

Definition at line 423 of file ezr32hg_dma.h.

#define _DMA_CHENC_CH5ENC_SHIFT 5

Shift value for DMA_CH5ENC

Definition at line 422 of file ezr32hg_dma.h.

#define _DMA_CHENC_MASK 0x0000003FUL

Mask for DMA_CHENC

Definition at line 395 of file ezr32hg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHENC_RESETVALUE 0x00000000UL

Default value for DMA_CHENC

Definition at line 394 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 365 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH0ENS_MASK 0x1UL

Bit mask for DMA_CH0ENS

Definition at line 364 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH0ENS_SHIFT 0

Shift value for DMA_CH0ENS

Definition at line 363 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 370 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH1ENS_MASK 0x2UL

Bit mask for DMA_CH1ENS

Definition at line 369 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH1ENS_SHIFT 1

Shift value for DMA_CH1ENS

Definition at line 368 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 375 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH2ENS_MASK 0x4UL

Bit mask for DMA_CH2ENS

Definition at line 374 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH2ENS_SHIFT 2

Shift value for DMA_CH2ENS

Definition at line 373 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 380 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH3ENS_MASK 0x8UL

Bit mask for DMA_CH3ENS

Definition at line 379 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH3ENS_SHIFT 3

Shift value for DMA_CH3ENS

Definition at line 378 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 385 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH4ENS_MASK 0x10UL

Bit mask for DMA_CH4ENS

Definition at line 384 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH4ENS_SHIFT 4

Shift value for DMA_CH4ENS

Definition at line 383 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHENS

Definition at line 390 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH5ENS_MASK 0x20UL

Bit mask for DMA_CH5ENS

Definition at line 389 of file ezr32hg_dma.h.

#define _DMA_CHENS_CH5ENS_SHIFT 5

Shift value for DMA_CH5ENS

Definition at line 388 of file ezr32hg_dma.h.

#define _DMA_CHENS_MASK 0x0000003FUL

Mask for DMA_CHENS

Definition at line 361 of file ezr32hg_dma.h.

#define _DMA_CHENS_RESETVALUE 0x00000000UL

Default value for DMA_CHENS

Definition at line 360 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 535 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL

Bit mask for DMA_CH0PRIC

Definition at line 534 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH0PRIC_SHIFT 0

Shift value for DMA_CH0PRIC

Definition at line 533 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 540 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL

Bit mask for DMA_CH1PRIC

Definition at line 539 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH1PRIC_SHIFT 1

Shift value for DMA_CH1PRIC

Definition at line 538 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 545 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL

Bit mask for DMA_CH2PRIC

Definition at line 544 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH2PRIC_SHIFT 2

Shift value for DMA_CH2PRIC

Definition at line 543 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 550 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL

Bit mask for DMA_CH3PRIC

Definition at line 549 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH3PRIC_SHIFT 3

Shift value for DMA_CH3PRIC

Definition at line 548 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 555 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL

Bit mask for DMA_CH4PRIC

Definition at line 554 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH4PRIC_SHIFT 4

Shift value for DMA_CH4PRIC

Definition at line 553 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIC

Definition at line 560 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL

Bit mask for DMA_CH5PRIC

Definition at line 559 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_CH5PRIC_SHIFT 5

Shift value for DMA_CH5PRIC

Definition at line 558 of file ezr32hg_dma.h.

#define _DMA_CHPRIC_MASK 0x0000003FUL

Mask for DMA_CHPRIC

Definition at line 531 of file ezr32hg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHPRIC_RESETVALUE 0x00000000UL

Default value for DMA_CHPRIC

Definition at line 530 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 501 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL

Bit mask for DMA_CH0PRIS

Definition at line 500 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH0PRIS_SHIFT 0

Shift value for DMA_CH0PRIS

Definition at line 499 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 506 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL

Bit mask for DMA_CH1PRIS

Definition at line 505 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH1PRIS_SHIFT 1

Shift value for DMA_CH1PRIS

Definition at line 504 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 511 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL

Bit mask for DMA_CH2PRIS

Definition at line 510 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH2PRIS_SHIFT 2

Shift value for DMA_CH2PRIS

Definition at line 509 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 516 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL

Bit mask for DMA_CH3PRIS

Definition at line 515 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH3PRIS_SHIFT 3

Shift value for DMA_CH3PRIS

Definition at line 514 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 521 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL

Bit mask for DMA_CH4PRIS

Definition at line 520 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH4PRIS_SHIFT 4

Shift value for DMA_CH4PRIS

Definition at line 519 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHPRIS

Definition at line 526 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL

Bit mask for DMA_CH5PRIS

Definition at line 525 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_CH5PRIS_SHIFT 5

Shift value for DMA_CH5PRIS

Definition at line 524 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_MASK 0x0000003FUL

Mask for DMA_CHPRIS

Definition at line 497 of file ezr32hg_dma.h.

#define _DMA_CHPRIS_RESETVALUE 0x00000000UL

Default value for DMA_CHPRIS

Definition at line 496 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 331 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL

Bit mask for DMA_CH0REQMASKC

Definition at line 330 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0

Shift value for DMA_CH0REQMASKC

Definition at line 329 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 336 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL

Bit mask for DMA_CH1REQMASKC

Definition at line 335 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1

Shift value for DMA_CH1REQMASKC

Definition at line 334 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 341 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL

Bit mask for DMA_CH2REQMASKC

Definition at line 340 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2

Shift value for DMA_CH2REQMASKC

Definition at line 339 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 346 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL

Bit mask for DMA_CH3REQMASKC

Definition at line 345 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3

Shift value for DMA_CH3REQMASKC

Definition at line 344 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 351 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL

Bit mask for DMA_CH4REQMASKC

Definition at line 350 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4

Shift value for DMA_CH4REQMASKC

Definition at line 349 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKC

Definition at line 356 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL

Bit mask for DMA_CH5REQMASKC

Definition at line 355 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5

Shift value for DMA_CH5REQMASKC

Definition at line 354 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKC_MASK 0x0000003FUL

Mask for DMA_CHREQMASKC

Definition at line 327 of file ezr32hg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL

Default value for DMA_CHREQMASKC

Definition at line 326 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 297 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL

Bit mask for DMA_CH0REQMASKS

Definition at line 296 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0

Shift value for DMA_CH0REQMASKS

Definition at line 295 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 302 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL

Bit mask for DMA_CH1REQMASKS

Definition at line 301 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1

Shift value for DMA_CH1REQMASKS

Definition at line 300 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 307 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL

Bit mask for DMA_CH2REQMASKS

Definition at line 306 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2

Shift value for DMA_CH2REQMASKS

Definition at line 305 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 312 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL

Bit mask for DMA_CH3REQMASKS

Definition at line 311 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3

Shift value for DMA_CH3REQMASKS

Definition at line 310 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 317 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL

Bit mask for DMA_CH4REQMASKS

Definition at line 316 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4

Shift value for DMA_CH4REQMASKS

Definition at line 315 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQMASKS

Definition at line 322 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL

Bit mask for DMA_CH5REQMASKS

Definition at line 321 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5

Shift value for DMA_CH5REQMASKS

Definition at line 320 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_MASK 0x0000003FUL

Mask for DMA_CHREQMASKS

Definition at line 293 of file ezr32hg_dma.h.

#define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL

Default value for DMA_CHREQMASKS

Definition at line 292 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 578 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL

Bit mask for DMA_CH0REQSTATUS

Definition at line 577 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0

Shift value for DMA_CH0REQSTATUS

Definition at line 576 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 583 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL

Bit mask for DMA_CH1REQSTATUS

Definition at line 582 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1

Shift value for DMA_CH1REQSTATUS

Definition at line 581 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 588 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL

Bit mask for DMA_CH2REQSTATUS

Definition at line 587 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2

Shift value for DMA_CH2REQSTATUS

Definition at line 586 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 593 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL

Bit mask for DMA_CH3REQSTATUS

Definition at line 592 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3

Shift value for DMA_CH3REQSTATUS

Definition at line 591 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 598 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL

Bit mask for DMA_CH4REQSTATUS

Definition at line 597 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4

Shift value for DMA_CH4REQSTATUS

Definition at line 596 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHREQSTATUS

Definition at line 603 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL

Bit mask for DMA_CH5REQSTATUS

Definition at line 602 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5

Shift value for DMA_CH5REQSTATUS

Definition at line 601 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_MASK 0x0000003FUL

Mask for DMA_CHREQSTATUS

Definition at line 574 of file ezr32hg_dma.h.

#define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL

Default value for DMA_CHREQSTATUS

Definition at line 573 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 612 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL

Bit mask for DMA_CH0SREQSTATUS

Definition at line 611 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0

Shift value for DMA_CH0SREQSTATUS

Definition at line 610 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 617 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL

Bit mask for DMA_CH1SREQSTATUS

Definition at line 616 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1

Shift value for DMA_CH1SREQSTATUS

Definition at line 615 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 622 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL

Bit mask for DMA_CH2SREQSTATUS

Definition at line 621 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2

Shift value for DMA_CH2SREQSTATUS

Definition at line 620 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 627 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL

Bit mask for DMA_CH3SREQSTATUS

Definition at line 626 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3

Shift value for DMA_CH3SREQSTATUS

Definition at line 625 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 632 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL

Bit mask for DMA_CH4SREQSTATUS

Definition at line 631 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4

Shift value for DMA_CH4SREQSTATUS

Definition at line 630 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 637 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL

Bit mask for DMA_CH5SREQSTATUS

Definition at line 636 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5

Shift value for DMA_CH5SREQSTATUS

Definition at line 635 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_MASK 0x0000003FUL

Mask for DMA_CHSREQSTATUS

Definition at line 608 of file ezr32hg_dma.h.

#define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL

Default value for DMA_CHSREQSTATUS

Definition at line 607 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 191 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL

Bit mask for DMA_CH0SWREQ

Definition at line 190 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0

Shift value for DMA_CH0SWREQ

Definition at line 189 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 196 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL

Bit mask for DMA_CH1SWREQ

Definition at line 195 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1

Shift value for DMA_CH1SWREQ

Definition at line 194 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 201 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL

Bit mask for DMA_CH2SWREQ

Definition at line 200 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2

Shift value for DMA_CH2SWREQ

Definition at line 199 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 206 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL

Bit mask for DMA_CH3SWREQ

Definition at line 205 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3

Shift value for DMA_CH3SWREQ

Definition at line 204 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 211 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL

Bit mask for DMA_CH4SWREQ

Definition at line 210 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4

Shift value for DMA_CH4SWREQ

Definition at line 209 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHSWREQ

Definition at line 216 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL

Bit mask for DMA_CH5SWREQ

Definition at line 215 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5

Shift value for DMA_CH5SWREQ

Definition at line 214 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_MASK 0x0000003FUL

Mask for DMA_CHSWREQ

Definition at line 187 of file ezr32hg_dma.h.

#define _DMA_CHSWREQ_RESETVALUE 0x00000000UL

Default value for DMA_CHSWREQ

Definition at line 186 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 263 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL

Bit mask for DMA_CH0USEBURSTC

Definition at line 262 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0

Shift value for DMA_CH0USEBURSTC

Definition at line 261 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 268 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL

Bit mask for DMA_CH1USEBURSTC

Definition at line 267 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1

Shift value for DMA_CH1USEBURSTC

Definition at line 266 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 273 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL

Bit mask for DMA_CH2USEBURSTC

Definition at line 272 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2

Shift value for DMA_CH2USEBURSTC

Definition at line 271 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 278 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL

Bit mask for DMA_CH3USEBURSTC

Definition at line 277 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3

Shift value for DMA_CH3USEBURSTC

Definition at line 276 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 283 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL

Bit mask for DMA_CH4USEBURSTC

Definition at line 282 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4

Shift value for DMA_CH4USEBURSTC

Definition at line 281 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 288 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL

Bit mask for DMA_CH5USEBURSTC

Definition at line 287 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5

Shift value for DMA_CH5USEBURSTC

Definition at line 286 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTC_MASK 0x0000003FUL

Mask for DMA_CHUSEBURSTC

Definition at line 259 of file ezr32hg_dma.h.

Referenced by DMA_Reset().

#define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL

Default value for DMA_CHUSEBURSTC

Definition at line 258 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL

Mode BURSTONLY for DMA_CHUSEBURSTS

Definition at line 227 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 225 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL

Bit mask for DMA_CH0USEBURSTS

Definition at line 224 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0

Shift value for DMA_CH0USEBURSTS

Definition at line 223 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL

Mode SINGLEANDBURST for DMA_CHUSEBURSTS

Definition at line 226 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 234 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL

Bit mask for DMA_CH1USEBURSTS

Definition at line 233 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1

Shift value for DMA_CH1USEBURSTS

Definition at line 232 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 239 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL

Bit mask for DMA_CH2USEBURSTS

Definition at line 238 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2

Shift value for DMA_CH2USEBURSTS

Definition at line 237 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 244 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL

Bit mask for DMA_CH3USEBURSTS

Definition at line 243 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3

Shift value for DMA_CH3USEBURSTS

Definition at line 242 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 249 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL

Bit mask for DMA_CH4USEBURSTS

Definition at line 248 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4

Shift value for DMA_CH4USEBURSTS

Definition at line 247 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 254 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL

Bit mask for DMA_CH5USEBURSTS

Definition at line 253 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5

Shift value for DMA_CH5USEBURSTS

Definition at line 252 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_MASK 0x0000003FUL

Mask for DMA_CHUSEBURSTS

Definition at line 221 of file ezr32hg_dma.h.

#define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL

Default value for DMA_CHUSEBURSTS

Definition at line 220 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 157 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL

Bit mask for DMA_CH0WAITSTATUS

Definition at line 156 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0

Shift value for DMA_CH0WAITSTATUS

Definition at line 155 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 162 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL

Bit mask for DMA_CH1WAITSTATUS

Definition at line 161 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1

Shift value for DMA_CH1WAITSTATUS

Definition at line 160 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 167 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL

Bit mask for DMA_CH2WAITSTATUS

Definition at line 166 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2

Shift value for DMA_CH2WAITSTATUS

Definition at line 165 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 172 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL

Bit mask for DMA_CH3WAITSTATUS

Definition at line 171 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3

Shift value for DMA_CH3WAITSTATUS

Definition at line 170 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 177 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL

Bit mask for DMA_CH4WAITSTATUS

Definition at line 176 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4

Shift value for DMA_CH4WAITSTATUS

Definition at line 175 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL

Mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 182 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL

Bit mask for DMA_CH5WAITSTATUS

Definition at line 181 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5

Shift value for DMA_CH5WAITSTATUS

Definition at line 180 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_MASK 0x0000003FUL

Mask for DMA_CHWAITSTATUS

Definition at line 153 of file ezr32hg_dma.h.

#define _DMA_CHWAITSTATUS_RESETVALUE 0x0000003FUL

Default value for DMA_CHWAITSTATUS

Definition at line 152 of file ezr32hg_dma.h.

#define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CONFIG

Definition at line 132 of file ezr32hg_dma.h.

#define _DMA_CONFIG_CHPROT_MASK 0x20UL

Bit mask for DMA_CHPROT

Definition at line 131 of file ezr32hg_dma.h.

#define _DMA_CONFIG_CHPROT_SHIFT 5

Shift value for DMA_CHPROT

Definition at line 130 of file ezr32hg_dma.h.

Referenced by DMA_Init().

#define _DMA_CONFIG_EN_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CONFIG

Definition at line 127 of file ezr32hg_dma.h.

#define _DMA_CONFIG_EN_MASK 0x1UL

Bit mask for DMA_EN

Definition at line 126 of file ezr32hg_dma.h.

#define _DMA_CONFIG_EN_SHIFT 0

Shift value for DMA_EN

Definition at line 125 of file ezr32hg_dma.h.

#define _DMA_CONFIG_MASK 0x00000021UL

Mask for DMA_CONFIG

Definition at line 123 of file ezr32hg_dma.h.

#define _DMA_CONFIG_RESETVALUE 0x00000000UL

Default value for DMA_CONFIG

Definition at line 122 of file ezr32hg_dma.h.

Referenced by DMA_Reset(), and DMADRV_DeInit().

#define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_CTRLBASE

Definition at line 140 of file ezr32hg_dma.h.

#define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL

Bit mask for DMA_CTRLBASE

Definition at line 139 of file ezr32hg_dma.h.

#define _DMA_CTRLBASE_CTRLBASE_SHIFT 0

Shift value for DMA_CTRLBASE

Definition at line 138 of file ezr32hg_dma.h.

#define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL

Mask for DMA_CTRLBASE

Definition at line 137 of file ezr32hg_dma.h.

#define _DMA_CTRLBASE_RESETVALUE 0x00000000UL

Default value for DMA_CTRLBASE

Definition at line 136 of file ezr32hg_dma.h.

#define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_ERRORC

Definition at line 569 of file ezr32hg_dma.h.

#define _DMA_ERRORC_ERRORC_MASK 0x1UL

Bit mask for DMA_ERRORC

Definition at line 568 of file ezr32hg_dma.h.

#define _DMA_ERRORC_ERRORC_SHIFT 0

Shift value for DMA_ERRORC

Definition at line 567 of file ezr32hg_dma.h.

#define _DMA_ERRORC_MASK 0x00000001UL

Mask for DMA_ERRORC

Definition at line 565 of file ezr32hg_dma.h.

#define _DMA_ERRORC_RESETVALUE 0x00000000UL

Default value for DMA_ERRORC

Definition at line 564 of file ezr32hg_dma.h.

#define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 763 of file ezr32hg_dma.h.

#define _DMA_IEN_CH0DONE_MASK 0x1UL

Bit mask for DMA_CH0DONE

Definition at line 762 of file ezr32hg_dma.h.

#define _DMA_IEN_CH0DONE_SHIFT 0

Shift value for DMA_CH0DONE

Definition at line 761 of file ezr32hg_dma.h.

#define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 768 of file ezr32hg_dma.h.

#define _DMA_IEN_CH1DONE_MASK 0x2UL

Bit mask for DMA_CH1DONE

Definition at line 767 of file ezr32hg_dma.h.

#define _DMA_IEN_CH1DONE_SHIFT 1

Shift value for DMA_CH1DONE

Definition at line 766 of file ezr32hg_dma.h.

#define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 773 of file ezr32hg_dma.h.

#define _DMA_IEN_CH2DONE_MASK 0x4UL

Bit mask for DMA_CH2DONE

Definition at line 772 of file ezr32hg_dma.h.

#define _DMA_IEN_CH2DONE_SHIFT 2

Shift value for DMA_CH2DONE

Definition at line 771 of file ezr32hg_dma.h.

#define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 778 of file ezr32hg_dma.h.

#define _DMA_IEN_CH3DONE_MASK 0x8UL

Bit mask for DMA_CH3DONE

Definition at line 777 of file ezr32hg_dma.h.

#define _DMA_IEN_CH3DONE_SHIFT 3

Shift value for DMA_CH3DONE

Definition at line 776 of file ezr32hg_dma.h.

#define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 783 of file ezr32hg_dma.h.

#define _DMA_IEN_CH4DONE_MASK 0x10UL

Bit mask for DMA_CH4DONE

Definition at line 782 of file ezr32hg_dma.h.

#define _DMA_IEN_CH4DONE_SHIFT 4

Shift value for DMA_CH4DONE

Definition at line 781 of file ezr32hg_dma.h.

#define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 788 of file ezr32hg_dma.h.

#define _DMA_IEN_CH5DONE_MASK 0x20UL

Bit mask for DMA_CH5DONE

Definition at line 787 of file ezr32hg_dma.h.

#define _DMA_IEN_CH5DONE_SHIFT 5

Shift value for DMA_CH5DONE

Definition at line 786 of file ezr32hg_dma.h.

#define _DMA_IEN_ERR_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IEN

Definition at line 793 of file ezr32hg_dma.h.

#define _DMA_IEN_ERR_MASK 0x80000000UL

Bit mask for DMA_ERR

Definition at line 792 of file ezr32hg_dma.h.

#define _DMA_IEN_ERR_SHIFT 31

Shift value for DMA_ERR

Definition at line 791 of file ezr32hg_dma.h.

#define _DMA_IEN_MASK 0x8000003FUL

Mask for DMA_IEN

Definition at line 759 of file ezr32hg_dma.h.

#define _DMA_IEN_RESETVALUE 0x00000000UL

Default value for DMA_IEN

Definition at line 758 of file ezr32hg_dma.h.

Referenced by DMA_Reset(), and DMADRV_DeInit().

#define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 646 of file ezr32hg_dma.h.

#define _DMA_IF_CH0DONE_MASK 0x1UL

Bit mask for DMA_CH0DONE

Definition at line 645 of file ezr32hg_dma.h.

#define _DMA_IF_CH0DONE_SHIFT 0

Shift value for DMA_CH0DONE

Definition at line 644 of file ezr32hg_dma.h.

#define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 651 of file ezr32hg_dma.h.

#define _DMA_IF_CH1DONE_MASK 0x2UL

Bit mask for DMA_CH1DONE

Definition at line 650 of file ezr32hg_dma.h.

#define _DMA_IF_CH1DONE_SHIFT 1

Shift value for DMA_CH1DONE

Definition at line 649 of file ezr32hg_dma.h.

#define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 656 of file ezr32hg_dma.h.

#define _DMA_IF_CH2DONE_MASK 0x4UL

Bit mask for DMA_CH2DONE

Definition at line 655 of file ezr32hg_dma.h.

#define _DMA_IF_CH2DONE_SHIFT 2

Shift value for DMA_CH2DONE

Definition at line 654 of file ezr32hg_dma.h.

#define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 661 of file ezr32hg_dma.h.

#define _DMA_IF_CH3DONE_MASK 0x8UL

Bit mask for DMA_CH3DONE

Definition at line 660 of file ezr32hg_dma.h.

#define _DMA_IF_CH3DONE_SHIFT 3

Shift value for DMA_CH3DONE

Definition at line 659 of file ezr32hg_dma.h.

#define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 666 of file ezr32hg_dma.h.

#define _DMA_IF_CH4DONE_MASK 0x10UL

Bit mask for DMA_CH4DONE

Definition at line 665 of file ezr32hg_dma.h.

#define _DMA_IF_CH4DONE_SHIFT 4

Shift value for DMA_CH4DONE

Definition at line 664 of file ezr32hg_dma.h.

#define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 671 of file ezr32hg_dma.h.

#define _DMA_IF_CH5DONE_MASK 0x20UL

Bit mask for DMA_CH5DONE

Definition at line 670 of file ezr32hg_dma.h.

#define _DMA_IF_CH5DONE_SHIFT 5

Shift value for DMA_CH5DONE

Definition at line 669 of file ezr32hg_dma.h.

#define _DMA_IF_ERR_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IF

Definition at line 676 of file ezr32hg_dma.h.

#define _DMA_IF_ERR_MASK 0x80000000UL

Bit mask for DMA_ERR

Definition at line 675 of file ezr32hg_dma.h.

#define _DMA_IF_ERR_SHIFT 31

Shift value for DMA_ERR

Definition at line 674 of file ezr32hg_dma.h.

#define _DMA_IF_MASK 0x8000003FUL

Mask for DMA_IF

Definition at line 642 of file ezr32hg_dma.h.

#define _DMA_IF_RESETVALUE 0x00000000UL

Default value for DMA_IF

Definition at line 641 of file ezr32hg_dma.h.

#define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 724 of file ezr32hg_dma.h.

#define _DMA_IFC_CH0DONE_MASK 0x1UL

Bit mask for DMA_CH0DONE

Definition at line 723 of file ezr32hg_dma.h.

#define _DMA_IFC_CH0DONE_SHIFT 0

Shift value for DMA_CH0DONE

Definition at line 722 of file ezr32hg_dma.h.

#define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 729 of file ezr32hg_dma.h.

#define _DMA_IFC_CH1DONE_MASK 0x2UL

Bit mask for DMA_CH1DONE

Definition at line 728 of file ezr32hg_dma.h.

#define _DMA_IFC_CH1DONE_SHIFT 1

Shift value for DMA_CH1DONE

Definition at line 727 of file ezr32hg_dma.h.

#define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 734 of file ezr32hg_dma.h.

#define _DMA_IFC_CH2DONE_MASK 0x4UL

Bit mask for DMA_CH2DONE

Definition at line 733 of file ezr32hg_dma.h.

#define _DMA_IFC_CH2DONE_SHIFT 2

Shift value for DMA_CH2DONE

Definition at line 732 of file ezr32hg_dma.h.

#define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 739 of file ezr32hg_dma.h.

#define _DMA_IFC_CH3DONE_MASK 0x8UL

Bit mask for DMA_CH3DONE

Definition at line 738 of file ezr32hg_dma.h.

#define _DMA_IFC_CH3DONE_SHIFT 3

Shift value for DMA_CH3DONE

Definition at line 737 of file ezr32hg_dma.h.

#define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 744 of file ezr32hg_dma.h.

#define _DMA_IFC_CH4DONE_MASK 0x10UL

Bit mask for DMA_CH4DONE

Definition at line 743 of file ezr32hg_dma.h.

#define _DMA_IFC_CH4DONE_SHIFT 4

Shift value for DMA_CH4DONE

Definition at line 742 of file ezr32hg_dma.h.

#define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 749 of file ezr32hg_dma.h.

#define _DMA_IFC_CH5DONE_MASK 0x20UL

Bit mask for DMA_CH5DONE

Definition at line 748 of file ezr32hg_dma.h.

#define _DMA_IFC_CH5DONE_SHIFT 5

Shift value for DMA_CH5DONE

Definition at line 747 of file ezr32hg_dma.h.

#define _DMA_IFC_ERR_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFC

Definition at line 754 of file ezr32hg_dma.h.

#define _DMA_IFC_ERR_MASK 0x80000000UL

Bit mask for DMA_ERR

Definition at line 753 of file ezr32hg_dma.h.

#define _DMA_IFC_ERR_SHIFT 31

Shift value for DMA_ERR

Definition at line 752 of file ezr32hg_dma.h.

#define _DMA_IFC_MASK 0x8000003FUL

Mask for DMA_IFC

Definition at line 720 of file ezr32hg_dma.h.

Referenced by DMA_Reset().

#define _DMA_IFC_RESETVALUE 0x00000000UL

Default value for DMA_IFC

Definition at line 719 of file ezr32hg_dma.h.

#define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 685 of file ezr32hg_dma.h.

#define _DMA_IFS_CH0DONE_MASK 0x1UL

Bit mask for DMA_CH0DONE

Definition at line 684 of file ezr32hg_dma.h.

#define _DMA_IFS_CH0DONE_SHIFT 0

Shift value for DMA_CH0DONE

Definition at line 683 of file ezr32hg_dma.h.

#define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 690 of file ezr32hg_dma.h.

#define _DMA_IFS_CH1DONE_MASK 0x2UL

Bit mask for DMA_CH1DONE

Definition at line 689 of file ezr32hg_dma.h.

#define _DMA_IFS_CH1DONE_SHIFT 1

Shift value for DMA_CH1DONE

Definition at line 688 of file ezr32hg_dma.h.

#define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 695 of file ezr32hg_dma.h.

#define _DMA_IFS_CH2DONE_MASK 0x4UL

Bit mask for DMA_CH2DONE

Definition at line 694 of file ezr32hg_dma.h.

#define _DMA_IFS_CH2DONE_SHIFT 2

Shift value for DMA_CH2DONE

Definition at line 693 of file ezr32hg_dma.h.

#define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 700 of file ezr32hg_dma.h.

#define _DMA_IFS_CH3DONE_MASK 0x8UL

Bit mask for DMA_CH3DONE

Definition at line 699 of file ezr32hg_dma.h.

#define _DMA_IFS_CH3DONE_SHIFT 3

Shift value for DMA_CH3DONE

Definition at line 698 of file ezr32hg_dma.h.

#define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 705 of file ezr32hg_dma.h.

#define _DMA_IFS_CH4DONE_MASK 0x10UL

Bit mask for DMA_CH4DONE

Definition at line 704 of file ezr32hg_dma.h.

#define _DMA_IFS_CH4DONE_SHIFT 4

Shift value for DMA_CH4DONE

Definition at line 703 of file ezr32hg_dma.h.

#define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 710 of file ezr32hg_dma.h.

#define _DMA_IFS_CH5DONE_MASK 0x20UL

Bit mask for DMA_CH5DONE

Definition at line 709 of file ezr32hg_dma.h.

#define _DMA_IFS_CH5DONE_SHIFT 5

Shift value for DMA_CH5DONE

Definition at line 708 of file ezr32hg_dma.h.

#define _DMA_IFS_ERR_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_IFS

Definition at line 715 of file ezr32hg_dma.h.

#define _DMA_IFS_ERR_MASK 0x80000000UL

Bit mask for DMA_ERR

Definition at line 714 of file ezr32hg_dma.h.

#define _DMA_IFS_ERR_SHIFT 31

Shift value for DMA_ERR

Definition at line 713 of file ezr32hg_dma.h.

#define _DMA_IFS_MASK 0x8000003FUL

Mask for DMA_IFS

Definition at line 681 of file ezr32hg_dma.h.

#define _DMA_IFS_RESETVALUE 0x00000000UL

Default value for DMA_IFS

Definition at line 680 of file ezr32hg_dma.h.

#define _DMA_STATUS_CHNUM_DEFAULT 0x00000005UL

Mode DEFAULT for DMA_STATUS

Definition at line 118 of file ezr32hg_dma.h.

#define _DMA_STATUS_CHNUM_MASK 0x1F0000UL

Bit mask for DMA_CHNUM

Definition at line 117 of file ezr32hg_dma.h.

#define _DMA_STATUS_CHNUM_SHIFT 16

Shift value for DMA_CHNUM

Definition at line 116 of file ezr32hg_dma.h.

#define _DMA_STATUS_EN_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_STATUS

Definition at line 88 of file ezr32hg_dma.h.

#define _DMA_STATUS_EN_MASK 0x1UL

Bit mask for DMA_EN

Definition at line 87 of file ezr32hg_dma.h.

#define _DMA_STATUS_EN_SHIFT 0

Shift value for DMA_EN

Definition at line 86 of file ezr32hg_dma.h.

#define _DMA_STATUS_MASK 0x001F00F1UL

Mask for DMA_STATUS

Definition at line 84 of file ezr32hg_dma.h.

#define _DMA_STATUS_RESETVALUE 0x10050000UL

Default value for DMA_STATUS

Definition at line 83 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_DEFAULT 0x00000000UL

Mode DEFAULT for DMA_STATUS

Definition at line 92 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_DONE 0x00000009UL

Mode DONE for DMA_STATUS

Definition at line 102 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_IDLE 0x00000000UL

Mode IDLE for DMA_STATUS

Definition at line 93 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_MASK 0xF0UL

Bit mask for DMA_STATE

Definition at line 91 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL

Mode PERSCATTRANS for DMA_STATUS

Definition at line 103 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL

Mode RDCHCTRLDATA for DMA_STATUS

Definition at line 94 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL

Mode RDDSTENDPTR for DMA_STATUS

Definition at line 96 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL

Mode RDSRCDATA for DMA_STATUS

Definition at line 97 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL

Mode RDSRCENDPTR for DMA_STATUS

Definition at line 95 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_SHIFT 4

Shift value for DMA_STATE

Definition at line 90 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_STALLED 0x00000008UL

Mode STALLED for DMA_STATUS

Definition at line 101 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL

Mode WAITREQCLR for DMA_STATUS

Definition at line 99 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL

Mode WRCHCTRLDATA for DMA_STATUS

Definition at line 100 of file ezr32hg_dma.h.

#define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL

Mode WRDSTDATA for DMA_STATUS

Definition at line 98 of file ezr32hg_dma.h.

#define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_ALTCTRLBASE

Definition at line 149 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)

Shifted mode ADC0SCAN for DMA_CH_CTRL

Definition at line 843 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)

Shifted mode ADC0SINGLE for DMA_CH_CTRL

Definition at line 833 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)

Shifted mode AESDATARD for DMA_CH_CTRL

Definition at line 858 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)

Shifted mode AESDATAWR for DMA_CH_CTRL

Definition at line 842 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)

Shifted mode AESKEYWR for DMA_CH_CTRL

Definition at line 863 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)

Shifted mode AESXORDATAWR for DMA_CH_CTRL

Definition at line 851 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)

Shifted mode I2C0RXDATAV for DMA_CH_CTRL

Definition at line 837 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)

Shifted mode I2C0TXBL for DMA_CH_CTRL

Definition at line 847 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)

Shifted mode LEUART0RXDATAV for DMA_CH_CTRL

Definition at line 836 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)

Shifted mode LEUART0TXBL for DMA_CH_CTRL

Definition at line 846 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)

Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL

Definition at line 854 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)

Shifted mode MSCWDATA for DMA_CH_CTRL

Definition at line 841 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)

Shifted mode TIMER0CC0 for DMA_CH_CTRL

Definition at line 848 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)

Shifted mode TIMER0CC1 for DMA_CH_CTRL

Definition at line 855 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)

Shifted mode TIMER0CC2 for DMA_CH_CTRL

Definition at line 860 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)

Shifted mode TIMER0UFOF for DMA_CH_CTRL

Definition at line 838 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)

Shifted mode TIMER1CC0 for DMA_CH_CTRL

Definition at line 849 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)

Shifted mode TIMER1CC1 for DMA_CH_CTRL

Definition at line 856 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)

Shifted mode TIMER1CC2 for DMA_CH_CTRL

Definition at line 861 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)

Shifted mode TIMER1UFOF for DMA_CH_CTRL

Definition at line 839 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)

Shifted mode TIMER2CC0 for DMA_CH_CTRL

Definition at line 850 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)

Shifted mode TIMER2CC1 for DMA_CH_CTRL

Definition at line 857 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)

Shifted mode TIMER2CC2 for DMA_CH_CTRL

Definition at line 862 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)

Shifted mode TIMER2UFOF for DMA_CH_CTRL

Definition at line 840 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)

Shifted mode USART0RXDATAV for DMA_CH_CTRL

Definition at line 834 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)

Shifted mode USART0TXBL for DMA_CH_CTRL

Definition at line 844 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)

Shifted mode USART0TXEMPTY for DMA_CH_CTRL

Definition at line 852 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAV (_DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAV << 0)

Shifted mode USARTRF1RXDATAV for DMA_CH_CTRL

Definition at line 835 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USARTRF1RXDATAVRIGHT << 0)

Shifted mode USARTRF1RXDATAVRIGHT for DMA_CH_CTRL

Definition at line 859 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USARTRF1TXBL (_DMA_CH_CTRL_SIGSEL_USARTRF1TXBL << 0)

Shifted mode USARTRF1TXBL for DMA_CH_CTRL

Definition at line 845 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USARTRF1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USARTRF1TXBLRIGHT << 0)

Shifted mode USARTRF1TXBLRIGHT for DMA_CH_CTRL

Definition at line 864 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SIGSEL_USARTRF1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USARTRF1TXEMPTY << 0)

Shifted mode USARTRF1TXEMPTY for DMA_CH_CTRL

Definition at line 853 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)

Shifted mode ADC0 for DMA_CH_CTRL

Definition at line 879 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16)

Shifted mode AES for DMA_CH_CTRL

Definition at line 888 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)

Shifted mode I2C0 for DMA_CH_CTRL

Definition at line 883 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)

Shifted mode LEUART0 for DMA_CH_CTRL

Definition at line 882 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)

Shifted mode MSC for DMA_CH_CTRL

Definition at line 887 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)

Shifted mode NONE for DMA_CH_CTRL

Definition at line 878 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)

Shifted mode TIMER0 for DMA_CH_CTRL

Definition at line 884 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)

Shifted mode TIMER1 for DMA_CH_CTRL

Definition at line 885 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)

Shifted mode TIMER2 for DMA_CH_CTRL

Definition at line 886 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)

Shifted mode USART0 for DMA_CH_CTRL

Definition at line 880 of file ezr32hg_dma.h.

#define DMA_CH_CTRL_SOURCESEL_USARTRF1 (_DMA_CH_CTRL_SOURCESEL_USARTRF1 << 16)

Shifted mode USARTRF1 for DMA_CH_CTRL

Definition at line 881 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH0ALTC (0x1UL << 0)

Channel 0 Alternate Clear

Definition at line 464 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 468 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH1ALTC (0x1UL << 1)

Channel 1 Alternate Clear

Definition at line 469 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 473 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH2ALTC (0x1UL << 2)

Channel 2 Alternate Clear

Definition at line 474 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 478 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH3ALTC (0x1UL << 3)

Channel 3 Alternate Clear

Definition at line 479 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 483 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH4ALTC (0x1UL << 4)

Channel 4 Alternate Clear

Definition at line 484 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 488 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH5ALTC (0x1UL << 5)

Channel 5 Alternate Clear

Definition at line 489 of file ezr32hg_dma.h.

#define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHALTC

Definition at line 493 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH0ALTS (0x1UL << 0)

Channel 0 Alternate Structure Set

Definition at line 430 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 434 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH1ALTS (0x1UL << 1)

Channel 1 Alternate Structure Set

Definition at line 435 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 439 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH2ALTS (0x1UL << 2)

Channel 2 Alternate Structure Set

Definition at line 440 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 444 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH3ALTS (0x1UL << 3)

Channel 3 Alternate Structure Set

Definition at line 445 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 449 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH4ALTS (0x1UL << 4)

Channel 4 Alternate Structure Set

Definition at line 450 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 454 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH5ALTS (0x1UL << 5)

Channel 5 Alternate Structure Set

Definition at line 455 of file ezr32hg_dma.h.

#define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHALTS

Definition at line 459 of file ezr32hg_dma.h.

#define DMA_CHENC_CH0ENC (0x1UL << 0)

Channel 0 Enable Clear

Definition at line 396 of file ezr32hg_dma.h.

#define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 400 of file ezr32hg_dma.h.

#define DMA_CHENC_CH1ENC (0x1UL << 1)

Channel 1 Enable Clear

Definition at line 401 of file ezr32hg_dma.h.

#define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 405 of file ezr32hg_dma.h.

#define DMA_CHENC_CH2ENC (0x1UL << 2)

Channel 2 Enable Clear

Definition at line 406 of file ezr32hg_dma.h.

#define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 410 of file ezr32hg_dma.h.

#define DMA_CHENC_CH3ENC (0x1UL << 3)

Channel 3 Enable Clear

Definition at line 411 of file ezr32hg_dma.h.

#define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 415 of file ezr32hg_dma.h.

#define DMA_CHENC_CH4ENC (0x1UL << 4)

Channel 4 Enable Clear

Definition at line 416 of file ezr32hg_dma.h.

#define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 420 of file ezr32hg_dma.h.

#define DMA_CHENC_CH5ENC (0x1UL << 5)

Channel 5 Enable Clear

Definition at line 421 of file ezr32hg_dma.h.

#define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHENC

Definition at line 425 of file ezr32hg_dma.h.

#define DMA_CHENS_CH0ENS (0x1UL << 0)

Channel 0 Enable Set

Definition at line 362 of file ezr32hg_dma.h.

#define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 366 of file ezr32hg_dma.h.

#define DMA_CHENS_CH1ENS (0x1UL << 1)

Channel 1 Enable Set

Definition at line 367 of file ezr32hg_dma.h.

#define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 371 of file ezr32hg_dma.h.

#define DMA_CHENS_CH2ENS (0x1UL << 2)

Channel 2 Enable Set

Definition at line 372 of file ezr32hg_dma.h.

#define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 376 of file ezr32hg_dma.h.

#define DMA_CHENS_CH3ENS (0x1UL << 3)

Channel 3 Enable Set

Definition at line 377 of file ezr32hg_dma.h.

#define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 381 of file ezr32hg_dma.h.

#define DMA_CHENS_CH4ENS (0x1UL << 4)

Channel 4 Enable Set

Definition at line 382 of file ezr32hg_dma.h.

#define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 386 of file ezr32hg_dma.h.

#define DMA_CHENS_CH5ENS (0x1UL << 5)

Channel 5 Enable Set

Definition at line 387 of file ezr32hg_dma.h.

#define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHENS

Definition at line 391 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH0PRIC (0x1UL << 0)

Channel 0 High Priority Clear

Definition at line 532 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 536 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH1PRIC (0x1UL << 1)

Channel 1 High Priority Clear

Definition at line 537 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 541 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH2PRIC (0x1UL << 2)

Channel 2 High Priority Clear

Definition at line 542 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 546 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH3PRIC (0x1UL << 3)

Channel 3 High Priority Clear

Definition at line 547 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 551 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH4PRIC (0x1UL << 4)

Channel 4 High Priority Clear

Definition at line 552 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 556 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH5PRIC (0x1UL << 5)

Channel 5 High Priority Clear

Definition at line 557 of file ezr32hg_dma.h.

#define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHPRIC

Definition at line 561 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH0PRIS (0x1UL << 0)

Channel 0 High Priority Set

Definition at line 498 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 502 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH1PRIS (0x1UL << 1)

Channel 1 High Priority Set

Definition at line 503 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 507 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH2PRIS (0x1UL << 2)

Channel 2 High Priority Set

Definition at line 508 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 512 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH3PRIS (0x1UL << 3)

Channel 3 High Priority Set

Definition at line 513 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 517 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH4PRIS (0x1UL << 4)

Channel 4 High Priority Set

Definition at line 518 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 522 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH5PRIS (0x1UL << 5)

Channel 5 High Priority Set

Definition at line 523 of file ezr32hg_dma.h.

#define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHPRIS

Definition at line 527 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)

Channel 0 Request Mask Clear

Definition at line 328 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 332 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)

Channel 1 Request Mask Clear

Definition at line 333 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 337 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)

Channel 2 Request Mask Clear

Definition at line 338 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 342 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)

Channel 3 Request Mask Clear

Definition at line 343 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 347 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4)

Channel 4 Request Mask Clear

Definition at line 348 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 352 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5)

Channel 5 Request Mask Clear

Definition at line 353 of file ezr32hg_dma.h.

#define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHREQMASKC

Definition at line 357 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)

Channel 0 Request Mask Set

Definition at line 294 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 298 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)

Channel 1 Request Mask Set

Definition at line 299 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 303 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)

Channel 2 Request Mask Set

Definition at line 304 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 308 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)

Channel 3 Request Mask Set

Definition at line 309 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 313 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4)

Channel 4 Request Mask Set

Definition at line 314 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 318 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5)

Channel 5 Request Mask Set

Definition at line 319 of file ezr32hg_dma.h.

#define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHREQMASKS

Definition at line 323 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)

Channel 0 Request Status

Definition at line 575 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 579 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)

Channel 1 Request Status

Definition at line 580 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 584 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)

Channel 2 Request Status

Definition at line 585 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 589 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)

Channel 3 Request Status

Definition at line 590 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 594 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4)

Channel 4 Request Status

Definition at line 595 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 599 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5)

Channel 5 Request Status

Definition at line 600 of file ezr32hg_dma.h.

#define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHREQSTATUS

Definition at line 604 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)

Channel 0 Single Request Status

Definition at line 609 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 613 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)

Channel 1 Single Request Status

Definition at line 614 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 618 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)

Channel 2 Single Request Status

Definition at line 619 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 623 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)

Channel 3 Single Request Status

Definition at line 624 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 628 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4)

Channel 4 Single Request Status

Definition at line 629 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 633 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5)

Channel 5 Single Request Status

Definition at line 634 of file ezr32hg_dma.h.

#define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHSREQSTATUS

Definition at line 638 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)

Channel 0 Software Request

Definition at line 188 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 192 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)

Channel 1 Software Request

Definition at line 193 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 197 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)

Channel 2 Software Request

Definition at line 198 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 202 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)

Channel 3 Software Request

Definition at line 203 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 207 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4)

Channel 4 Software Request

Definition at line 208 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 212 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5)

Channel 5 Software Request

Definition at line 213 of file ezr32hg_dma.h.

#define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHSWREQ

Definition at line 217 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)

Channel 0 Useburst Clear

Definition at line 260 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 264 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)

Channel 1 Useburst Clear

Definition at line 265 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 269 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)

Channel 2 Useburst Clear

Definition at line 270 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 274 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)

Channel 3 Useburst Clear

Definition at line 275 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 279 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4)

Channel 4 Useburst Clear

Definition at line 280 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 284 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5)

Channel 5 Useburst Clear

Definition at line 285 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHUSEBURSTC

Definition at line 289 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)

Channel 0 Useburst Set

Definition at line 222 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)

Shifted mode BURSTONLY for DMA_CHUSEBURSTS

Definition at line 230 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 228 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)

Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS

Definition at line 229 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)

Channel 1 Useburst Set

Definition at line 231 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 235 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)

Channel 2 Useburst Set

Definition at line 236 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 240 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)

Channel 3 Useburst Set

Definition at line 241 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 245 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4)

Channel 4 Useburst Set

Definition at line 246 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 250 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5)

Channel 5 Useburst Set

Definition at line 251 of file ezr32hg_dma.h.

#define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHUSEBURSTS

Definition at line 255 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)

Channel 0 Wait on Request Status

Definition at line 154 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 158 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)

Channel 1 Wait on Request Status

Definition at line 159 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 163 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)

Channel 2 Wait on Request Status

Definition at line 164 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 168 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)

Channel 3 Wait on Request Status

Definition at line 169 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 173 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4)

Channel 4 Wait on Request Status

Definition at line 174 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 178 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5)

Channel 5 Wait on Request Status

Definition at line 179 of file ezr32hg_dma.h.

#define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CHWAITSTATUS

Definition at line 183 of file ezr32hg_dma.h.

#define DMA_CONFIG_CHPROT (0x1UL << 5)

Channel Protection Control

Definition at line 129 of file ezr32hg_dma.h.

#define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)

Shifted mode DEFAULT for DMA_CONFIG

Definition at line 133 of file ezr32hg_dma.h.

#define DMA_CONFIG_EN (0x1UL << 0)

Enable DMA

Definition at line 124 of file ezr32hg_dma.h.

Referenced by DMA_Init().

#define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CONFIG

Definition at line 128 of file ezr32hg_dma.h.

#define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_CTRLBASE

Definition at line 141 of file ezr32hg_dma.h.

#define DMA_ERRORC_ERRORC (0x1UL << 0)

Bus Error Clear

Definition at line 566 of file ezr32hg_dma.h.

Referenced by DMA_Reset().

#define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)

Shifted mode DEFAULT for DMA_ERRORC

Definition at line 570 of file ezr32hg_dma.h.

#define DMA_IEN_CH0DONE (0x1UL << 0)

DMA Channel 0 Complete Interrupt Enable

Definition at line 760 of file ezr32hg_dma.h.

#define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IEN

Definition at line 764 of file ezr32hg_dma.h.

#define DMA_IEN_CH1DONE (0x1UL << 1)

DMA Channel 1 Complete Interrupt Enable

Definition at line 765 of file ezr32hg_dma.h.

#define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IEN

Definition at line 769 of file ezr32hg_dma.h.

#define DMA_IEN_CH2DONE (0x1UL << 2)

DMA Channel 2 Complete Interrupt Enable

Definition at line 770 of file ezr32hg_dma.h.

#define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IEN

Definition at line 774 of file ezr32hg_dma.h.

#define DMA_IEN_CH3DONE (0x1UL << 3)

DMA Channel 3 Complete Interrupt Enable

Definition at line 775 of file ezr32hg_dma.h.

#define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IEN

Definition at line 779 of file ezr32hg_dma.h.

#define DMA_IEN_CH4DONE (0x1UL << 4)

DMA Channel 4 Complete Interrupt Enable

Definition at line 780 of file ezr32hg_dma.h.

#define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IEN

Definition at line 784 of file ezr32hg_dma.h.

#define DMA_IEN_CH5DONE (0x1UL << 5)

DMA Channel 5 Complete Interrupt Enable

Definition at line 785 of file ezr32hg_dma.h.

#define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IEN

Definition at line 789 of file ezr32hg_dma.h.

#define DMA_IEN_ERR (0x1UL << 31)

DMA Error Interrupt Flag Enable

Definition at line 790 of file ezr32hg_dma.h.

Referenced by DMA_Init().

#define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IEN

Definition at line 794 of file ezr32hg_dma.h.

#define DMA_IF_CH0DONE (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag

Definition at line 643 of file ezr32hg_dma.h.

#define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IF

Definition at line 647 of file ezr32hg_dma.h.

#define DMA_IF_CH1DONE (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag

Definition at line 648 of file ezr32hg_dma.h.

#define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IF

Definition at line 652 of file ezr32hg_dma.h.

#define DMA_IF_CH2DONE (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag

Definition at line 653 of file ezr32hg_dma.h.

#define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IF

Definition at line 657 of file ezr32hg_dma.h.

#define DMA_IF_CH3DONE (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag

Definition at line 658 of file ezr32hg_dma.h.

#define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IF

Definition at line 662 of file ezr32hg_dma.h.

#define DMA_IF_CH4DONE (0x1UL << 4)

DMA Channel 4 Complete Interrupt Flag

Definition at line 663 of file ezr32hg_dma.h.

#define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IF

Definition at line 667 of file ezr32hg_dma.h.

#define DMA_IF_CH5DONE (0x1UL << 5)

DMA Channel 5 Complete Interrupt Flag

Definition at line 668 of file ezr32hg_dma.h.

#define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IF

Definition at line 672 of file ezr32hg_dma.h.

#define DMA_IF_ERR (0x1UL << 31)

DMA Error Interrupt Flag

Definition at line 673 of file ezr32hg_dma.h.

Referenced by DMA_IRQHandler().

#define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IF

Definition at line 677 of file ezr32hg_dma.h.

#define DMA_IFC_CH0DONE (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag Clear

Definition at line 721 of file ezr32hg_dma.h.

#define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)

Shifted mode DEFAULT for DMA_IFC

Definition at line 725 of file ezr32hg_dma.h.

#define DMA_IFC_CH1DONE (0x1UL << 1)

DMA Channel 1 Complete Interrupt Flag Clear

Definition at line 726 of file ezr32hg_dma.h.

#define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)

Shifted mode DEFAULT for DMA_IFC

Definition at line 730 of file ezr32hg_dma.h.

#define DMA_IFC_CH2DONE (0x1UL << 2)

DMA Channel 2 Complete Interrupt Flag Clear

Definition at line 731 of file ezr32hg_dma.h.

#define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)

Shifted mode DEFAULT for DMA_IFC

Definition at line 735 of file ezr32hg_dma.h.

#define DMA_IFC_CH3DONE (0x1UL << 3)

DMA Channel 3 Complete Interrupt Flag Clear

Definition at line 736 of file ezr32hg_dma.h.

#define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)

Shifted mode DEFAULT for DMA_IFC

Definition at line 740 of file ezr32hg_dma.h.

#define DMA_IFC_CH4DONE (0x1UL << 4)

DMA Channel 4 Complete Interrupt Flag Clear

Definition at line 741 of file ezr32hg_dma.h.

#define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4)

Shifted mode DEFAULT for DMA_IFC

Definition at line 745 of file ezr32hg_dma.h.

#define DMA_IFC_CH5DONE (0x1UL << 5)

DMA Channel 5 Complete Interrupt Flag Clear

Definition at line 746 of file ezr32hg_dma.h.

#define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5)

Shifted mode DEFAULT for DMA_IFC

Definition at line 750 of file ezr32hg_dma.h.

#define DMA_IFC_ERR (0x1UL << 31)

DMA Error Interrupt Flag Clear

Definition at line 751 of file ezr32hg_dma.h.

#define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)

Shifted mode DEFAULT for DMA_IFC

Definition at line 755 of file ezr32hg_dma.h.

#define DMA_IFS_CH0DONE (0x1UL << 0)

DMA Channel 0 Complete Interrupt Flag Set

Definition at line 682 of file ezr32hg_dma.h.

#define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)