Detailed Description

Modules
	EZR32HG320F64R69 Alternate Function

	EZR32HG320F64R69 Bit Fields

	EZR32HG320F64R69 Core
	Processor and Core Peripheral Section.

	EZR32HG320F64R69 Part

	EZR32HG320F64R69 Peripheral Declarations

	EZR32HG320F64R69 Peripheral Memory Map

	EZR32HG320F64R69 Peripheral TypeDefs
	Device Specific Peripheral Register Structures.

Macros
#define	ARM_MATH_CM0PLUS

#define	SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) \| (((VALUE) << (OFFSET)) & (MASK));
	Set the value of a bit field within a register. More...

Enumerations
enum	IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, ADC0_IRQn = 4, I2C0_IRQn = 5, GPIO_ODD_IRQn = 6, TIMER1_IRQn = 7, USARTRF1_RX_IRQn = 8, USARTRF1_TX_IRQn = 9, LEUART0_IRQn = 10, PCNT0_IRQn = 11, RTC_IRQn = 12, CMU_IRQn = 13, VCMP_IRQn = 14, MSC_IRQn = 15, AES_IRQn = 16, USART0_RX_IRQn = 17, USART0_TX_IRQn = 18, USB_IRQn = 19, TIMER2_IRQn = 20 }

Macro Definition Documentation

#define SET_BIT_FIELD	(	REG,
		MASK,
		VALUE,
		OFFSET
	)	REG = ((REG) &~(MASK)) \| (((VALUE) << (OFFSET)) & (MASK));

Set the value of a bit field within a register.

Parameters

REG	The register to update
MASK	The mask for the bit field to update
VALUE	The value to write to the bit field
OFFSET	The number of bits that the field is offset within the register. 0 (zero) means LSB.

Definition at line 415 of file ezr32hg320f64r69.h.

typedef enum IRQn IRQn_Type

Interrupt Number Definition

enum IRQn

Interrupt Number Definition

Enumerator
NonMaskableInt_IRQn	-14 Cortex-M0+ Non Maskable Interrupt
HardFault_IRQn	-13 Cortex-M0+ Hard Fault Interrupt
SVCall_IRQn	-5 Cortex-M0+ SV Call Interrupt
PendSV_IRQn	-2 Cortex-M0+ Pend SV Interrupt
SysTick_IRQn	-1 Cortex-M0+ System Tick Interrupt
DMA_IRQn	0 EZR32 DMA Interrupt
GPIO_EVEN_IRQn	1 EZR32 GPIO_EVEN Interrupt
TIMER0_IRQn	2 EZR32 TIMER0 Interrupt
ADC0_IRQn	4 EZR32 ADC0 Interrupt
I2C0_IRQn	5 EZR32 I2C0 Interrupt
GPIO_ODD_IRQn	6 EZR32 GPIO_ODD Interrupt
TIMER1_IRQn	7 EZR32 TIMER1 Interrupt
USARTRF1_RX_IRQn	8 EZR32 USARTRF1_RX Interrupt
USARTRF1_TX_IRQn	9 EZR32 USARTRF1_TX Interrupt
LEUART0_IRQn	10 EZR32 LEUART0 Interrupt
PCNT0_IRQn	11 EZR32 PCNT0 Interrupt
RTC_IRQn	12 EZR32 RTC Interrupt
CMU_IRQn	13 EZR32 CMU Interrupt
VCMP_IRQn	14 EZR32 VCMP Interrupt
MSC_IRQn	15 EZR32 MSC Interrupt
AES_IRQn	16 EZR32 AES Interrupt
USART0_RX_IRQn	17 EZR32 USART0_RX Interrupt
USART0_TX_IRQn	18 EZR32 USART0_TX Interrupt
USB_IRQn	19 EZR32 USB Interrupt
TIMER2_IRQn	20 EZR32 TIMER2 Interrupt

Definition at line 52 of file ezr32hg320f64r69.h.