ezr32hg/html/ezr32hg__devinfo_8h_source.html

 /**************************************************************************/

 /**************************************************************************/

 /**************************************************************************/

 typedef struct

 {

   __IM uint32_t RADIO0;

   __IM uint32_t RADIO1;

   __IM uint32_t CAL;

   __IM uint32_t ADC0CAL0;

   __IM uint32_t ADC0CAL1;

   __IM uint32_t ADC0CAL2;

   uint32_t      RESERVED0[2];

   __IM uint32_t IDAC0CAL0;

   __IM uint32_t USHFRCOCAL0;

   uint32_t      RESERVED1[1];

   __IM uint32_t AUXHFRCOCAL0;

   __IM uint32_t AUXHFRCOCAL1;

   __IM uint32_t HFRCOCAL0;

   __IM uint32_t HFRCOCAL1;

   __IM uint32_t MEMINFO;

   uint32_t      RESERVED2;

   __IM uint32_t RADIO2;

   __IM uint32_t UNIQUEL;

   __IM uint32_t UNIQUEH;

   __IM uint32_t MSIZE;

   __IM uint32_t PART;

 } DEVINFO_TypeDef;

 /**************************************************************************/

 /* Bit fields for EZR32HG_DEVINFO */

 #define _DEVINFO_RADIO0_MASK                            0xFFFF0000UL

 #define _DEVINFO_RADIO0_MCMREVMAJ_MASK                  0xFF000000UL

 #define _DEVINFO_RADIO0_MCMREVMAJ_SHIFT                 24

 #define _DEVINFO_RADIO0_MCMREVMIN_MASK                  0x00FF0000UL

 #define _DEVINFO_RADIO0_MCMREVMIN_SHIFT                 16

 #define _DEVINFO_RADIO1_MASK                            0xFFFFFFFFUL

 #define _DEVINFO_RADIO1_RADIOOPN_MASK                   0xFFFF0000UL

 #define _DEVINFO_RADIO1_RADIOOPN_SHIFT                  16

 #define _DEVINFO_RADIO1_RADIOREVMAJ_MASK                0x0000FF00UL

 #define _DEVINFO_RADIO1_RADIOREVMAJ_SHIFT               8

 #define _DEVINFO_RADIO1_RADIOREVMIN_MASK                0x000000FFUL

 #define _DEVINFO_RADIO1_RADIOREVMIN_SHIFT               0

 #define _DEVINFO_CAL_CRC_MASK                           0x0000FFFFUL

 #define _DEVINFO_CAL_CRC_SHIFT                          0

 #define _DEVINFO_CAL_TEMP_MASK                          0x00FF0000UL

 #define _DEVINFO_CAL_TEMP_SHIFT                         16

 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK                0x00007F00UL

 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT               8

 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK              0x0000007FUL

 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT             0

 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK                 0x7F000000UL

 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT                24

 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK               0x007F0000UL

 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT              16

 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK                 0x00007F00UL

 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT                8

 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK               0x0000007FUL

 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT              0

 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK              0x7F000000UL

 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT             24

 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK            0x007F0000UL

 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT           16

 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK          0x0000007FUL

 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT         0

 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK                 0xFFF00000UL

 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT                20

 #define _DEVINFO_IDAC0CAL0_RANGE0_MASK                  0x000000FFUL

 #define _DEVINFO_IDAC0CAL0_RANGE0_SHIFT                 0

 #define _DEVINFO_IDAC0CAL0_RANGE1_MASK                  0x0000FF00UL

 #define _DEVINFO_IDAC0CAL0_RANGE1_SHIFT                 8

 #define _DEVINFO_IDAC0CAL0_RANGE2_MASK                  0x00FF0000UL

 #define _DEVINFO_IDAC0CAL0_RANGE2_SHIFT                 16

 #define _DEVINFO_IDAC0CAL0_RANGE3_MASK                  0xFF000000UL

 #define _DEVINFO_IDAC0CAL0_RANGE3_SHIFT                 24

 #define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK         0x0000007FUL

 #define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT        0

 #define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK     0x00003F00UL

 #define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT    8

 #define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK         0x007F0000UL

 #define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT        16

 #define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK     0x3F000000UL

 #define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT    24

 #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK                0x000000FFUL

 #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT               0

 #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK                0x0000FF00UL

 #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT               8

 #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK               0x00FF0000UL

 #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT              16

 #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK               0xFF000000UL

 #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT              24

 #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK               0x000000FFUL

 #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT              0

 #define _DEVINFO_HFRCOCAL0_BAND1_MASK                   0x000000FFUL

 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT                  0

 #define _DEVINFO_HFRCOCAL0_BAND7_MASK                   0x0000FF00UL

 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT                  8

 #define _DEVINFO_HFRCOCAL0_BAND11_MASK                  0x00FF0000UL

 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT                 16

 #define _DEVINFO_HFRCOCAL0_BAND14_MASK                  0xFF000000UL

 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT                 24

 #define _DEVINFO_HFRCOCAL1_BAND21_MASK                  0x000000FFUL

 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT                 0

 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK           0xFF000000UL

 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT          24

 #define _DEVINFO_RADIO2_MASK                            0xFFFF0000UL

 #define _DEVINFO_RADIO2_RADIOID_MASK                    0xFFFF0000UL

 #define _DEVINFO_RADIO2_RADIOID_SHIFT                   16

 #define _DEVINFO_UNIQUEL_MASK                           0xFFFFFFFFUL

 #define _DEVINFO_UNIQUEL_SHIFT                          0

 #define _DEVINFO_UNIQUEH_MASK                           0xFFFFFFFFUL

 #define _DEVINFO_UNIQUEH_SHIFT                          0

 #define _DEVINFO_MSIZE_SRAM_MASK                        0xFFFF0000UL

 #define _DEVINFO_MSIZE_SRAM_SHIFT                       16

 #define _DEVINFO_MSIZE_FLASH_MASK                       0x0000FFFFUL

 #define _DEVINFO_MSIZE_FLASH_SHIFT                      0

 #define _DEVINFO_PART_PROD_REV_MASK                     0xFF000000UL

 #define _DEVINFO_PART_PROD_REV_SHIFT                    24

 #define _DEVINFO_PART_DEVICE_FAMILY_MASK                0x00FF0000UL

 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT               16

 /* Legacy family #defines */

 #define _DEVINFO_PART_DEVICE_FAMILY_G                   71

 #define _DEVINFO_PART_DEVICE_FAMILY_GG                  72

 #define _DEVINFO_PART_DEVICE_FAMILY_TG                  73

 #define _DEVINFO_PART_DEVICE_FAMILY_LG                  74

 #define _DEVINFO_PART_DEVICE_FAMILY_WG                  75

 #define _DEVINFO_PART_DEVICE_FAMILY_ZG                  76

 #define _DEVINFO_PART_DEVICE_FAMILY_HG                  77

 /* New style family #defines */

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G              71

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG             72

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG             73

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG             74

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG             75

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG             76

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG             77

 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG             120

 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG             121

 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG             122

 #define _DEVINFO_PART_DEVICE_NUMBER_MASK                0x0000FFFFUL

 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT               0

DEVINFO_TypeDef::UNIQUEH
__IM uint32_t UNIQUEH
Definition: ezr32hg_devinfo.h:60

DEVINFO_TypeDef::RADIO2
__IM uint32_t RADIO2
Definition: ezr32hg_devinfo.h:58

DEVINFO_TypeDef::USHFRCOCAL0
__IM uint32_t USHFRCOCAL0
Definition: ezr32hg_devinfo.h:50

DEVINFO_TypeDef::AUXHFRCOCAL0
__IM uint32_t AUXHFRCOCAL0
Definition: ezr32hg_devinfo.h:52

DEVINFO_TypeDef::RADIO1
__IM uint32_t RADIO1
Definition: ezr32hg_devinfo.h:43

DEVINFO_TypeDef::RADIO0
__IM uint32_t RADIO0
Definition: ezr32hg_devinfo.h:42

DEVINFO_TypeDef::AUXHFRCOCAL1
__IM uint32_t AUXHFRCOCAL1
Definition: ezr32hg_devinfo.h:53

DEVINFO_TypeDef::MSIZE
__IM uint32_t MSIZE
Definition: ezr32hg_devinfo.h:61

DEVINFO_TypeDef
Definition: ezr32hg_devinfo.h:40

DEVINFO_TypeDef::ADC0CAL0
__IM uint32_t ADC0CAL0
Definition: ezr32hg_devinfo.h:45

DEVINFO_TypeDef::MEMINFO
__IM uint32_t MEMINFO
Definition: ezr32hg_devinfo.h:56

DEVINFO_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: ezr32hg_devinfo.h:57

DEVINFO_TypeDef::IDAC0CAL0
__IM uint32_t IDAC0CAL0
Definition: ezr32hg_devinfo.h:49

DEVINFO_TypeDef::ADC0CAL1
__IM uint32_t ADC0CAL1
Definition: ezr32hg_devinfo.h:46

DEVINFO_TypeDef::PART
__IM uint32_t PART
Definition: ezr32hg_devinfo.h:62

DEVINFO_TypeDef::UNIQUEL
__IM uint32_t UNIQUEL
Definition: ezr32hg_devinfo.h:59

DEVINFO_TypeDef::HFRCOCAL1
__IM uint32_t HFRCOCAL1
Definition: ezr32hg_devinfo.h:55

DEVINFO_TypeDef::CAL
__IM uint32_t CAL
Definition: ezr32hg_devinfo.h:44

DEVINFO_TypeDef::ADC0CAL2
__IM uint32_t ADC0CAL2
Definition: ezr32hg_devinfo.h:47

DEVINFO_TypeDef::HFRCOCAL0
__IM uint32_t HFRCOCAL0
Definition: ezr32hg_devinfo.h:54