EFR32 Mighty Gecko 13 Software Documentation  efr32mg13-doc-5.1.2
efr32mg13p_smu.h
Go to the documentation of this file.
1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  uint32_t RESERVED0[3];
44  __IM uint32_t IF;
45  __IOM uint32_t IFS;
46  __IOM uint32_t IFC;
47  __IOM uint32_t IEN;
49  uint32_t RESERVED1[9];
50  __IOM uint32_t PPUCTRL;
51  uint32_t RESERVED2[3];
52  __IOM uint32_t PPUPATD0;
53  __IOM uint32_t PPUPATD1;
55  uint32_t RESERVED3[14];
56  __IM uint32_t PPUFS;
57 } SMU_TypeDef;
59 /**************************************************************************/
64 /* Bit fields for SMU IF */
65 #define _SMU_IF_RESETVALUE 0x00000000UL
66 #define _SMU_IF_MASK 0x00000001UL
67 #define SMU_IF_PPUPRIV (0x1UL << 0)
68 #define _SMU_IF_PPUPRIV_SHIFT 0
69 #define _SMU_IF_PPUPRIV_MASK 0x1UL
70 #define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL
71 #define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0)
73 /* Bit fields for SMU IFS */
74 #define _SMU_IFS_RESETVALUE 0x00000000UL
75 #define _SMU_IFS_MASK 0x00000001UL
76 #define SMU_IFS_PPUPRIV (0x1UL << 0)
77 #define _SMU_IFS_PPUPRIV_SHIFT 0
78 #define _SMU_IFS_PPUPRIV_MASK 0x1UL
79 #define _SMU_IFS_PPUPRIV_DEFAULT 0x00000000UL
80 #define SMU_IFS_PPUPRIV_DEFAULT (_SMU_IFS_PPUPRIV_DEFAULT << 0)
82 /* Bit fields for SMU IFC */
83 #define _SMU_IFC_RESETVALUE 0x00000000UL
84 #define _SMU_IFC_MASK 0x00000001UL
85 #define SMU_IFC_PPUPRIV (0x1UL << 0)
86 #define _SMU_IFC_PPUPRIV_SHIFT 0
87 #define _SMU_IFC_PPUPRIV_MASK 0x1UL
88 #define _SMU_IFC_PPUPRIV_DEFAULT 0x00000000UL
89 #define SMU_IFC_PPUPRIV_DEFAULT (_SMU_IFC_PPUPRIV_DEFAULT << 0)
91 /* Bit fields for SMU IEN */
92 #define _SMU_IEN_RESETVALUE 0x00000000UL
93 #define _SMU_IEN_MASK 0x00000001UL
94 #define SMU_IEN_PPUPRIV (0x1UL << 0)
95 #define _SMU_IEN_PPUPRIV_SHIFT 0
96 #define _SMU_IEN_PPUPRIV_MASK 0x1UL
97 #define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL
98 #define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0)
100 /* Bit fields for SMU PPUCTRL */
101 #define _SMU_PPUCTRL_RESETVALUE 0x00000000UL
102 #define _SMU_PPUCTRL_MASK 0x00000001UL
103 #define SMU_PPUCTRL_ENABLE (0x1UL << 0)
104 #define _SMU_PPUCTRL_ENABLE_SHIFT 0
105 #define _SMU_PPUCTRL_ENABLE_MASK 0x1UL
106 #define _SMU_PPUCTRL_ENABLE_DEFAULT 0x00000000UL
107 #define SMU_PPUCTRL_ENABLE_DEFAULT (_SMU_PPUCTRL_ENABLE_DEFAULT << 0)
109 /* Bit fields for SMU PPUPATD0 */
110 #define _SMU_PPUPATD0_RESETVALUE 0x00000000UL
111 #define _SMU_PPUPATD0_MASK 0x0BFF7FA7UL
112 #define SMU_PPUPATD0_ACMP0 (0x1UL << 0)
113 #define _SMU_PPUPATD0_ACMP0_SHIFT 0
114 #define _SMU_PPUPATD0_ACMP0_MASK 0x1UL
115 #define _SMU_PPUPATD0_ACMP0_DEFAULT 0x00000000UL
116 #define SMU_PPUPATD0_ACMP0_DEFAULT (_SMU_PPUPATD0_ACMP0_DEFAULT << 0)
117 #define SMU_PPUPATD0_ACMP1 (0x1UL << 1)
118 #define _SMU_PPUPATD0_ACMP1_SHIFT 1
119 #define _SMU_PPUPATD0_ACMP1_MASK 0x2UL
120 #define _SMU_PPUPATD0_ACMP1_DEFAULT 0x00000000UL
121 #define SMU_PPUPATD0_ACMP1_DEFAULT (_SMU_PPUPATD0_ACMP1_DEFAULT << 1)
122 #define SMU_PPUPATD0_ADC0 (0x1UL << 2)
123 #define _SMU_PPUPATD0_ADC0_SHIFT 2
124 #define _SMU_PPUPATD0_ADC0_MASK 0x4UL
125 #define _SMU_PPUPATD0_ADC0_DEFAULT 0x00000000UL
126 #define SMU_PPUPATD0_ADC0_DEFAULT (_SMU_PPUPATD0_ADC0_DEFAULT << 2)
127 #define SMU_PPUPATD0_CMU (0x1UL << 5)
128 #define _SMU_PPUPATD0_CMU_SHIFT 5
129 #define _SMU_PPUPATD0_CMU_MASK 0x20UL
130 #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL
131 #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5)
132 #define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7)
133 #define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7
134 #define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL
135 #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL
136 #define SMU_PPUPATD0_CRYOTIMER_DEFAULT (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7)
137 #define SMU_PPUPATD0_CRYPTO0 (0x1UL << 8)
138 #define _SMU_PPUPATD0_CRYPTO0_SHIFT 8
139 #define _SMU_PPUPATD0_CRYPTO0_MASK 0x100UL
140 #define _SMU_PPUPATD0_CRYPTO0_DEFAULT 0x00000000UL
141 #define SMU_PPUPATD0_CRYPTO0_DEFAULT (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8)
142 #define SMU_PPUPATD0_CRYPTO1 (0x1UL << 9)
143 #define _SMU_PPUPATD0_CRYPTO1_SHIFT 9
144 #define _SMU_PPUPATD0_CRYPTO1_MASK 0x200UL
145 #define _SMU_PPUPATD0_CRYPTO1_DEFAULT 0x00000000UL
146 #define SMU_PPUPATD0_CRYPTO1_DEFAULT (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9)
147 #define SMU_PPUPATD0_CSEN (0x1UL << 10)
148 #define _SMU_PPUPATD0_CSEN_SHIFT 10
149 #define _SMU_PPUPATD0_CSEN_MASK 0x400UL
150 #define _SMU_PPUPATD0_CSEN_DEFAULT 0x00000000UL
151 #define SMU_PPUPATD0_CSEN_DEFAULT (_SMU_PPUPATD0_CSEN_DEFAULT << 10)
152 #define SMU_PPUPATD0_VDAC0 (0x1UL << 11)
153 #define _SMU_PPUPATD0_VDAC0_SHIFT 11
154 #define _SMU_PPUPATD0_VDAC0_MASK 0x800UL
155 #define _SMU_PPUPATD0_VDAC0_DEFAULT 0x00000000UL
156 #define SMU_PPUPATD0_VDAC0_DEFAULT (_SMU_PPUPATD0_VDAC0_DEFAULT << 11)
157 #define SMU_PPUPATD0_PRS (0x1UL << 12)
158 #define _SMU_PPUPATD0_PRS_SHIFT 12
159 #define _SMU_PPUPATD0_PRS_MASK 0x1000UL
160 #define _SMU_PPUPATD0_PRS_DEFAULT 0x00000000UL
161 #define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12)
162 #define SMU_PPUPATD0_EMU (0x1UL << 13)
163 #define _SMU_PPUPATD0_EMU_SHIFT 13
164 #define _SMU_PPUPATD0_EMU_MASK 0x2000UL
165 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL
166 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13)
167 #define SMU_PPUPATD0_FPUEH (0x1UL << 14)
168 #define _SMU_PPUPATD0_FPUEH_SHIFT 14
169 #define _SMU_PPUPATD0_FPUEH_MASK 0x4000UL
170 #define _SMU_PPUPATD0_FPUEH_DEFAULT 0x00000000UL
171 #define SMU_PPUPATD0_FPUEH_DEFAULT (_SMU_PPUPATD0_FPUEH_DEFAULT << 14)
172 #define SMU_PPUPATD0_GPCRC (0x1UL << 16)
173 #define _SMU_PPUPATD0_GPCRC_SHIFT 16
174 #define _SMU_PPUPATD0_GPCRC_MASK 0x10000UL
175 #define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000000UL
176 #define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 16)
177 #define SMU_PPUPATD0_GPIO (0x1UL << 17)
178 #define _SMU_PPUPATD0_GPIO_SHIFT 17
179 #define _SMU_PPUPATD0_GPIO_MASK 0x20000UL
180 #define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000000UL
181 #define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 17)
182 #define SMU_PPUPATD0_I2C0 (0x1UL << 18)
183 #define _SMU_PPUPATD0_I2C0_SHIFT 18
184 #define _SMU_PPUPATD0_I2C0_MASK 0x40000UL
185 #define _SMU_PPUPATD0_I2C0_DEFAULT 0x00000000UL
186 #define SMU_PPUPATD0_I2C0_DEFAULT (_SMU_PPUPATD0_I2C0_DEFAULT << 18)
187 #define SMU_PPUPATD0_I2C1 (0x1UL << 19)
188 #define _SMU_PPUPATD0_I2C1_SHIFT 19
189 #define _SMU_PPUPATD0_I2C1_MASK 0x80000UL
190 #define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000000UL
191 #define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 19)
192 #define SMU_PPUPATD0_IDAC0 (0x1UL << 20)
193 #define _SMU_PPUPATD0_IDAC0_SHIFT 20
194 #define _SMU_PPUPATD0_IDAC0_MASK 0x100000UL
195 #define _SMU_PPUPATD0_IDAC0_DEFAULT 0x00000000UL
196 #define SMU_PPUPATD0_IDAC0_DEFAULT (_SMU_PPUPATD0_IDAC0_DEFAULT << 20)
197 #define SMU_PPUPATD0_MSC (0x1UL << 21)
198 #define _SMU_PPUPATD0_MSC_SHIFT 21
199 #define _SMU_PPUPATD0_MSC_MASK 0x200000UL
200 #define _SMU_PPUPATD0_MSC_DEFAULT 0x00000000UL
201 #define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 21)
202 #define SMU_PPUPATD0_LDMA (0x1UL << 22)
203 #define _SMU_PPUPATD0_LDMA_SHIFT 22
204 #define _SMU_PPUPATD0_LDMA_MASK 0x400000UL
205 #define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000000UL
206 #define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 22)
207 #define SMU_PPUPATD0_LESENSE (0x1UL << 23)
208 #define _SMU_PPUPATD0_LESENSE_SHIFT 23
209 #define _SMU_PPUPATD0_LESENSE_MASK 0x800000UL
210 #define _SMU_PPUPATD0_LESENSE_DEFAULT 0x00000000UL
211 #define SMU_PPUPATD0_LESENSE_DEFAULT (_SMU_PPUPATD0_LESENSE_DEFAULT << 23)
212 #define SMU_PPUPATD0_LETIMER0 (0x1UL << 24)
213 #define _SMU_PPUPATD0_LETIMER0_SHIFT 24
214 #define _SMU_PPUPATD0_LETIMER0_MASK 0x1000000UL
215 #define _SMU_PPUPATD0_LETIMER0_DEFAULT 0x00000000UL
216 #define SMU_PPUPATD0_LETIMER0_DEFAULT (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24)
217 #define SMU_PPUPATD0_LEUART0 (0x1UL << 25)
218 #define _SMU_PPUPATD0_LEUART0_SHIFT 25
219 #define _SMU_PPUPATD0_LEUART0_MASK 0x2000000UL
220 #define _SMU_PPUPATD0_LEUART0_DEFAULT 0x00000000UL
221 #define SMU_PPUPATD0_LEUART0_DEFAULT (_SMU_PPUPATD0_LEUART0_DEFAULT << 25)
222 #define SMU_PPUPATD0_PCNT0 (0x1UL << 27)
223 #define _SMU_PPUPATD0_PCNT0_SHIFT 27
224 #define _SMU_PPUPATD0_PCNT0_MASK 0x8000000UL
225 #define _SMU_PPUPATD0_PCNT0_DEFAULT 0x00000000UL
226 #define SMU_PPUPATD0_PCNT0_DEFAULT (_SMU_PPUPATD0_PCNT0_DEFAULT << 27)
228 /* Bit fields for SMU PPUPATD1 */
229 #define _SMU_PPUPATD1_RESETVALUE 0x00000000UL
230 #define _SMU_PPUPATD1_MASK 0x00001FF7UL
231 #define SMU_PPUPATD1_RMU (0x1UL << 0)
232 #define _SMU_PPUPATD1_RMU_SHIFT 0
233 #define _SMU_PPUPATD1_RMU_MASK 0x1UL
234 #define _SMU_PPUPATD1_RMU_DEFAULT 0x00000000UL
235 #define SMU_PPUPATD1_RMU_DEFAULT (_SMU_PPUPATD1_RMU_DEFAULT << 0)
236 #define SMU_PPUPATD1_RTCC (0x1UL << 1)
237 #define _SMU_PPUPATD1_RTCC_SHIFT 1
238 #define _SMU_PPUPATD1_RTCC_MASK 0x2UL
239 #define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000000UL
240 #define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 1)
241 #define SMU_PPUPATD1_SMU (0x1UL << 2)
242 #define _SMU_PPUPATD1_SMU_SHIFT 2
243 #define _SMU_PPUPATD1_SMU_MASK 0x4UL
244 #define _SMU_PPUPATD1_SMU_DEFAULT 0x00000000UL
245 #define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 2)
246 #define SMU_PPUPATD1_TIMER0 (0x1UL << 4)
247 #define _SMU_PPUPATD1_TIMER0_SHIFT 4
248 #define _SMU_PPUPATD1_TIMER0_MASK 0x10UL
249 #define _SMU_PPUPATD1_TIMER0_DEFAULT 0x00000000UL
250 #define SMU_PPUPATD1_TIMER0_DEFAULT (_SMU_PPUPATD1_TIMER0_DEFAULT << 4)
251 #define SMU_PPUPATD1_TIMER1 (0x1UL << 5)
252 #define _SMU_PPUPATD1_TIMER1_SHIFT 5
253 #define _SMU_PPUPATD1_TIMER1_MASK 0x20UL
254 #define _SMU_PPUPATD1_TIMER1_DEFAULT 0x00000000UL
255 #define SMU_PPUPATD1_TIMER1_DEFAULT (_SMU_PPUPATD1_TIMER1_DEFAULT << 5)
256 #define SMU_PPUPATD1_TRNG0 (0x1UL << 6)
257 #define _SMU_PPUPATD1_TRNG0_SHIFT 6
258 #define _SMU_PPUPATD1_TRNG0_MASK 0x40UL
259 #define _SMU_PPUPATD1_TRNG0_DEFAULT 0x00000000UL
260 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 6)
261 #define SMU_PPUPATD1_USART0 (0x1UL << 7)
262 #define _SMU_PPUPATD1_USART0_SHIFT 7
263 #define _SMU_PPUPATD1_USART0_MASK 0x80UL
264 #define _SMU_PPUPATD1_USART0_DEFAULT 0x00000000UL
265 #define SMU_PPUPATD1_USART0_DEFAULT (_SMU_PPUPATD1_USART0_DEFAULT << 7)
266 #define SMU_PPUPATD1_USART1 (0x1UL << 8)
267 #define _SMU_PPUPATD1_USART1_SHIFT 8
268 #define _SMU_PPUPATD1_USART1_MASK 0x100UL
269 #define _SMU_PPUPATD1_USART1_DEFAULT 0x00000000UL
270 #define SMU_PPUPATD1_USART1_DEFAULT (_SMU_PPUPATD1_USART1_DEFAULT << 8)
271 #define SMU_PPUPATD1_USART2 (0x1UL << 9)
272 #define _SMU_PPUPATD1_USART2_SHIFT 9
273 #define _SMU_PPUPATD1_USART2_MASK 0x200UL
274 #define _SMU_PPUPATD1_USART2_DEFAULT 0x00000000UL
275 #define SMU_PPUPATD1_USART2_DEFAULT (_SMU_PPUPATD1_USART2_DEFAULT << 9)
276 #define SMU_PPUPATD1_WDOG0 (0x1UL << 10)
277 #define _SMU_PPUPATD1_WDOG0_SHIFT 10
278 #define _SMU_PPUPATD1_WDOG0_MASK 0x400UL
279 #define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000000UL
280 #define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 10)
281 #define SMU_PPUPATD1_WDOG1 (0x1UL << 11)
282 #define _SMU_PPUPATD1_WDOG1_SHIFT 11
283 #define _SMU_PPUPATD1_WDOG1_MASK 0x800UL
284 #define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000000UL
285 #define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 11)
286 #define SMU_PPUPATD1_WTIMER0 (0x1UL << 12)
287 #define _SMU_PPUPATD1_WTIMER0_SHIFT 12
288 #define _SMU_PPUPATD1_WTIMER0_MASK 0x1000UL
289 #define _SMU_PPUPATD1_WTIMER0_DEFAULT 0x00000000UL
290 #define SMU_PPUPATD1_WTIMER0_DEFAULT (_SMU_PPUPATD1_WTIMER0_DEFAULT << 12)
292 /* Bit fields for SMU PPUFS */
293 #define _SMU_PPUFS_RESETVALUE 0x00000000UL
294 #define _SMU_PPUFS_MASK 0x0000007FUL
295 #define _SMU_PPUFS_PERIPHID_SHIFT 0
296 #define _SMU_PPUFS_PERIPHID_MASK 0x7FUL
297 #define _SMU_PPUFS_PERIPHID_DEFAULT 0x00000000UL
298 #define _SMU_PPUFS_PERIPHID_ACMP0 0x00000000UL
299 #define _SMU_PPUFS_PERIPHID_ACMP1 0x00000001UL
300 #define _SMU_PPUFS_PERIPHID_ADC0 0x00000002UL
301 #define _SMU_PPUFS_PERIPHID_CMU 0x00000005UL
302 #define _SMU_PPUFS_PERIPHID_CRYOTIMER 0x00000007UL
303 #define _SMU_PPUFS_PERIPHID_CRYPTO0 0x00000008UL
304 #define _SMU_PPUFS_PERIPHID_CRYPTO1 0x00000009UL
305 #define _SMU_PPUFS_PERIPHID_CSEN 0x0000000AUL
306 #define _SMU_PPUFS_PERIPHID_VDAC0 0x0000000BUL
307 #define _SMU_PPUFS_PERIPHID_PRS 0x0000000CUL
308 #define _SMU_PPUFS_PERIPHID_EMU 0x0000000DUL
309 #define _SMU_PPUFS_PERIPHID_FPUEH 0x0000000EUL
310 #define _SMU_PPUFS_PERIPHID_GPCRC 0x00000010UL
311 #define _SMU_PPUFS_PERIPHID_GPIO 0x00000011UL
312 #define _SMU_PPUFS_PERIPHID_I2C0 0x00000012UL
313 #define _SMU_PPUFS_PERIPHID_I2C1 0x00000013UL
314 #define _SMU_PPUFS_PERIPHID_IDAC0 0x00000014UL
315 #define _SMU_PPUFS_PERIPHID_MSC 0x00000015UL
316 #define _SMU_PPUFS_PERIPHID_LDMA 0x00000016UL
317 #define _SMU_PPUFS_PERIPHID_LESENSE 0x00000017UL
318 #define _SMU_PPUFS_PERIPHID_LETIMER0 0x00000018UL
319 #define _SMU_PPUFS_PERIPHID_LEUART0 0x00000019UL
320 #define _SMU_PPUFS_PERIPHID_PCNT0 0x0000001BUL
321 #define _SMU_PPUFS_PERIPHID_RMU 0x00000020UL
322 #define _SMU_PPUFS_PERIPHID_RTCC 0x00000021UL
323 #define _SMU_PPUFS_PERIPHID_SMU 0x00000022UL
324 #define _SMU_PPUFS_PERIPHID_TIMER0 0x00000024UL
325 #define _SMU_PPUFS_PERIPHID_TIMER1 0x00000025UL
326 #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000026UL
327 #define _SMU_PPUFS_PERIPHID_USART0 0x00000027UL
328 #define _SMU_PPUFS_PERIPHID_USART1 0x00000028UL
329 #define _SMU_PPUFS_PERIPHID_USART2 0x00000029UL
330 #define _SMU_PPUFS_PERIPHID_WDOG0 0x0000002AUL
331 #define _SMU_PPUFS_PERIPHID_WDOG1 0x0000002BUL
332 #define _SMU_PPUFS_PERIPHID_WTIMER0 0x0000002CUL
333 #define SMU_PPUFS_PERIPHID_DEFAULT (_SMU_PPUFS_PERIPHID_DEFAULT << 0)
334 #define SMU_PPUFS_PERIPHID_ACMP0 (_SMU_PPUFS_PERIPHID_ACMP0 << 0)
335 #define SMU_PPUFS_PERIPHID_ACMP1 (_SMU_PPUFS_PERIPHID_ACMP1 << 0)
336 #define SMU_PPUFS_PERIPHID_ADC0 (_SMU_PPUFS_PERIPHID_ADC0 << 0)
337 #define SMU_PPUFS_PERIPHID_CMU (_SMU_PPUFS_PERIPHID_CMU << 0)
338 #define SMU_PPUFS_PERIPHID_CRYOTIMER (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0)
339 #define SMU_PPUFS_PERIPHID_CRYPTO0 (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0)
340 #define SMU_PPUFS_PERIPHID_CRYPTO1 (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0)
341 #define SMU_PPUFS_PERIPHID_CSEN (_SMU_PPUFS_PERIPHID_CSEN << 0)
342 #define SMU_PPUFS_PERIPHID_VDAC0 (_SMU_PPUFS_PERIPHID_VDAC0 << 0)
343 #define SMU_PPUFS_PERIPHID_PRS (_SMU_PPUFS_PERIPHID_PRS << 0)
344 #define SMU_PPUFS_PERIPHID_EMU (_SMU_PPUFS_PERIPHID_EMU << 0)
345 #define SMU_PPUFS_PERIPHID_FPUEH (_SMU_PPUFS_PERIPHID_FPUEH << 0)
346 #define SMU_PPUFS_PERIPHID_GPCRC (_SMU_PPUFS_PERIPHID_GPCRC << 0)
347 #define SMU_PPUFS_PERIPHID_GPIO (_SMU_PPUFS_PERIPHID_GPIO << 0)
348 #define SMU_PPUFS_PERIPHID_I2C0 (_SMU_PPUFS_PERIPHID_I2C0 << 0)
349 #define SMU_PPUFS_PERIPHID_I2C1 (_SMU_PPUFS_PERIPHID_I2C1 << 0)
350 #define SMU_PPUFS_PERIPHID_IDAC0 (_SMU_PPUFS_PERIPHID_IDAC0 << 0)
351 #define SMU_PPUFS_PERIPHID_MSC (_SMU_PPUFS_PERIPHID_MSC << 0)
352 #define SMU_PPUFS_PERIPHID_LDMA (_SMU_PPUFS_PERIPHID_LDMA << 0)
353 #define SMU_PPUFS_PERIPHID_LESENSE (_SMU_PPUFS_PERIPHID_LESENSE << 0)
354 #define SMU_PPUFS_PERIPHID_LETIMER0 (_SMU_PPUFS_PERIPHID_LETIMER0 << 0)
355 #define SMU_PPUFS_PERIPHID_LEUART0 (_SMU_PPUFS_PERIPHID_LEUART0 << 0)
356 #define SMU_PPUFS_PERIPHID_PCNT0 (_SMU_PPUFS_PERIPHID_PCNT0 << 0)
357 #define SMU_PPUFS_PERIPHID_RMU (_SMU_PPUFS_PERIPHID_RMU << 0)
358 #define SMU_PPUFS_PERIPHID_RTCC (_SMU_PPUFS_PERIPHID_RTCC << 0)
359 #define SMU_PPUFS_PERIPHID_SMU (_SMU_PPUFS_PERIPHID_SMU << 0)
360 #define SMU_PPUFS_PERIPHID_TIMER0 (_SMU_PPUFS_PERIPHID_TIMER0 << 0)
361 #define SMU_PPUFS_PERIPHID_TIMER1 (_SMU_PPUFS_PERIPHID_TIMER1 << 0)
362 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0)
363 #define SMU_PPUFS_PERIPHID_USART0 (_SMU_PPUFS_PERIPHID_USART0 << 0)
364 #define SMU_PPUFS_PERIPHID_USART1 (_SMU_PPUFS_PERIPHID_USART1 << 0)
365 #define SMU_PPUFS_PERIPHID_USART2 (_SMU_PPUFS_PERIPHID_USART2 << 0)
366 #define SMU_PPUFS_PERIPHID_WDOG0 (_SMU_PPUFS_PERIPHID_WDOG0 << 0)
367 #define SMU_PPUFS_PERIPHID_WDOG1 (_SMU_PPUFS_PERIPHID_WDOG1 << 0)
368 #define SMU_PPUFS_PERIPHID_WTIMER0 (_SMU_PPUFS_PERIPHID_WTIMER0 << 0)
__IOM uint32_t IFS
__IOM uint32_t PPUPATD1
__IOM uint32_t IFC
__IOM uint32_t PPUCTRL
__IM uint32_t IF
__IOM uint32_t PPUPATD0
__IOM uint32_t IEN
__IM uint32_t PPUFS