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#define | _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL |
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#define | _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL |
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#define | _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL |
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#define | _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 |
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#define | _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL |
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#define | _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL |
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#define | _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL |
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#define | _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL |
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#define | _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 |
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#define | _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL |
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#define | _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL |
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#define | _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL |
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#define | _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 |
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#define | _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL |
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#define | _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL |
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#define | _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 |
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#define | _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL |
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#define | _ETM_ETMCCER_DADDRCMP_SHIFT 12 |
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#define | _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCER_EICEIMP_MASK 0x200000UL |
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#define | _ETM_ETMCCER_EICEIMP_SHIFT 21 |
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#define | _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL |
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#define | _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL |
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#define | _ETM_ETMCCER_EICEWPNT_SHIFT 16 |
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#define | _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL |
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#define | _ETM_ETMCCER_EXTINPBUS_SHIFT 3 |
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#define | _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL |
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#define | _ETM_ETMCCER_EXTINPSEL_SHIFT 0 |
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#define | _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCER_INSTRES_MASK 0xE000UL |
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#define | _ETM_ETMCCER_INSTRES_SHIFT 13 |
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#define | _ETM_ETMCCER_MASK 0x387FFFFBUL |
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#define | _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCER_READREGS_MASK 0x800UL |
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#define | _ETM_ETMCCER_READREGS_SHIFT 11 |
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#define | _ETM_ETMCCER_RESETVALUE 0x18541800UL |
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#define | _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCER_RFCNT_MASK 0x8000000UL |
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#define | _ETM_ETMCCER_RFCNT_SHIFT 27 |
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#define | _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL |
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#define | _ETM_ETMCCER_TEICEWPNT_SHIFT 20 |
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#define | _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCER_TENC_MASK 0x10000000UL |
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#define | _ETM_ETMCCER_TENC_SHIFT 28 |
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#define | _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCER_TIMP_MASK 0x400000UL |
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#define | _ETM_ETMCCER_TIMP_SHIFT 22 |
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#define | _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCER_TSIZE_MASK 0x20000000UL |
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#define | _ETM_ETMCCER_TSIZE_SHIFT 29 |
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#define | _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL |
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#define | _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 |
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#define | _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL |
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#define | _ETM_ETMCCR_COUNTNUM_SHIFT 13 |
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#define | _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL |
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#define | _ETM_ETMCCR_DATACMPNUM_SHIFT 4 |
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#define | _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCR_ETMID_MASK 0x80000000UL |
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#define | _ETM_ETMCCR_ETMID_SHIFT 31 |
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#define | _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL |
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#define | _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL |
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#define | _ETM_ETMCCR_EXTINPNUM_SHIFT 17 |
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#define | _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL |
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#define | _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL |
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#define | _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL |
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#define | _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 |
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#define | _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL |
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#define | _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 |
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#define | _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL |
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#define | _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 |
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#define | _ETM_ETMCCR_MASK 0x8FFFFFFFUL |
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#define | _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL |
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#define | _ETM_ETMCCR_MMACCESS_SHIFT 27 |
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#define | _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL |
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#define | _ETM_ETMCCR_MMDECCNT_SHIFT 8 |
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#define | _ETM_ETMCCR_RESETVALUE 0x8C802000UL |
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#define | _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCCR_SEQPRES_MASK 0x10000UL |
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#define | _ETM_ETMCCR_SEQPRES_SHIFT 16 |
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#define | _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCCR_TRACESS_MASK 0x4000000UL |
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#define | _ETM_ETMCCR_TRACESS_SHIFT 26 |
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#define | _ETM_ETMCIDR0_MASK 0x000000FFUL |
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#define | _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL |
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#define | _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL |
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#define | _ETM_ETMCIDR0_PREAMB_SHIFT 0 |
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#define | _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL |
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#define | _ETM_ETMCIDR1_MASK 0x000000FFUL |
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#define | _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL |
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#define | _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL |
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#define | _ETM_ETMCIDR1_PREAMB_SHIFT 0 |
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#define | _ETM_ETMCIDR1_RESETVALUE 0x00000090UL |
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#define | _ETM_ETMCIDR2_MASK 0x000000FFUL |
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#define | _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL |
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#define | _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL |
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#define | _ETM_ETMCIDR2_PREAMB_SHIFT 0 |
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#define | _ETM_ETMCIDR2_RESETVALUE 0x00000005UL |
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#define | _ETM_ETMCIDR3_MASK 0x000000FFUL |
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#define | _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL |
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#define | _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL |
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#define | _ETM_ETMCIDR3_PREAMB_SHIFT 0 |
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#define | _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL |
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#define | _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL |
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#define | _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 |
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#define | _ETM_ETMCLAIMCLR_MASK 0x00000001UL |
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#define | _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMCLAIMSET_MASK 0x000000FFUL |
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#define | _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL |
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#define | _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL |
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#define | _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL |
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#define | _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 |
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#define | _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL |
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#define | _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 |
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#define | _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL |
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#define | _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL |
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#define | _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 |
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#define | _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL |
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#define | _ETM_ETMCR_DBGREQCTRL_SHIFT 9 |
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#define | _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL |
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#define | _ETM_ETMCR_EPORTSIZE_SHIFT 21 |
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#define | _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL |
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#define | _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL |
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#define | _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL |
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#define | _ETM_ETMCR_ETMPORTSEL_SHIFT 11 |
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#define | _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCR_ETMPROG_MASK 0x400UL |
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#define | _ETM_ETMCR_ETMPROG_SHIFT 10 |
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#define | _ETM_ETMCR_MASK 0x10632FF1UL |
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#define | _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCR_PORTMODE2_MASK 0x2000UL |
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#define | _ETM_ETMCR_PORTMODE2_SHIFT 13 |
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#define | _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCR_PORTMODE_MASK 0x30000UL |
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#define | _ETM_ETMCR_PORTMODE_SHIFT 16 |
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#define | _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCR_PORTSIZE_MASK 0x70UL |
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#define | _ETM_ETMCR_PORTSIZE_SHIFT 4 |
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#define | _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL |
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#define | _ETM_ETMCR_POWERDWN_MASK 0x1UL |
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#define | _ETM_ETMCR_POWERDWN_SHIFT 0 |
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#define | _ETM_ETMCR_RESETVALUE 0x00000411UL |
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#define | _ETM_ETMCR_STALL_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCR_STALL_MASK 0x80UL |
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#define | _ETM_ETMCR_STALL_SHIFT 7 |
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#define | _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL |
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#define | _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL |
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#define | _ETM_ETMCR_TSTAMPEN_SHIFT 28 |
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#define | _ETM_ETMDEVTYPE_MASK 0x000000FFUL |
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#define | _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL |
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#define | _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL |
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#define | _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 |
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#define | _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL |
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#define | _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL |
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#define | _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL |
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#define | _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 |
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#define | _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL |
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#define | _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL |
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#define | _ETM_ETMFFLR_BYTENUM_SHIFT 0 |
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#define | _ETM_ETMFFLR_MASK 0x000000FFUL |
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#define | _ETM_ETMFFLR_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMIDR2_MASK 0x00000003UL |
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#define | _ETM_ETMIDR2_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMIDR2_RFE_CPSR 0x00000001UL |
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#define | _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL |
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#define | _ETM_ETMIDR2_RFE_MASK 0x1UL |
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#define | _ETM_ETMIDR2_RFE_PC 0x00000000UL |
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#define | _ETM_ETMIDR2_RFE_SHIFT 0 |
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#define | _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL |
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#define | _ETM_ETMIDR2_SWP_LOAD 0x00000000UL |
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#define | _ETM_ETMIDR2_SWP_MASK 0x2UL |
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#define | _ETM_ETMIDR2_SWP_SHIFT 1 |
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#define | _ETM_ETMIDR2_SWP_STORE 0x00000001UL |
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#define | _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL |
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#define | _ETM_ETMIDR_BPE_MASK 0x100000UL |
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#define | _ETM_ETMIDR_BPE_SHIFT 20 |
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#define | _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL |
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#define | _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL |
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#define | _ETM_ETMIDR_ETMMAJVER_SHIFT 8 |
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#define | _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL |
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#define | _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL |
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#define | _ETM_ETMIDR_ETMMINVER_SHIFT 4 |
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#define | _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL |
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#define | _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL |
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#define | _ETM_ETMIDR_IMPCODE_SHIFT 24 |
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#define | _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL |
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#define | _ETM_ETMIDR_IMPVER_MASK 0xFUL |
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#define | _ETM_ETMIDR_IMPVER_SHIFT 0 |
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#define | _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL |
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#define | _ETM_ETMIDR_LPCF_MASK 0x10000UL |
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#define | _ETM_ETMIDR_LPCF_SHIFT 16 |
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#define | _ETM_ETMIDR_MASK 0xFF1DFFFFUL |
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#define | _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL |
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#define | _ETM_ETMIDR_PROCFAM_MASK 0xF000UL |
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#define | _ETM_ETMIDR_PROCFAM_SHIFT 12 |
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#define | _ETM_ETMIDR_RESETVALUE 0x4114F253UL |
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#define | _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMIDR_SECEXT_MASK 0x80000UL |
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#define | _ETM_ETMIDR_SECEXT_SHIFT 19 |
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#define | _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL |
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#define | _ETM_ETMIDR_THUMBT_MASK 0x40000UL |
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#define | _ETM_ETMIDR_THUMBT_SHIFT 18 |
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#define | _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMISCIN_COREHALT_MASK 0x10UL |
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#define | _ETM_ETMISCIN_COREHALT_SHIFT 4 |
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#define | _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL |
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#define | _ETM_ETMISCIN_EXTIN_MASK 0x3UL |
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#define | _ETM_ETMISCIN_EXTIN_SHIFT 0 |
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#define | _ETM_ETMISCIN_MASK 0x00000013UL |
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#define | _ETM_ETMISCIN_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL |
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#define | _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL |
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#define | _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 |
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#define | _ETM_ETMITATBCTR0_MASK 0x00000001UL |
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#define | _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL |
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#define | _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL |
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#define | _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 |
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#define | _ETM_ETMITATBCTR2_MASK 0x00000001UL |
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#define | _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL |
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#define | _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL |
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#define | _ETM_ETMITCTRL_ITEN_MASK 0x1UL |
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#define | _ETM_ETMITCTRL_ITEN_SHIFT 0 |
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#define | _ETM_ETMITCTRL_MASK 0x00000001UL |
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#define | _ETM_ETMITCTRL_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL |
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#define | _ETM_ETMLAR_KEY_MASK 0x1UL |
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#define | _ETM_ETMLAR_KEY_SHIFT 0 |
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#define | _ETM_ETMLAR_MASK 0x00000001UL |
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#define | _ETM_ETMLAR_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL |
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#define | _ETM_ETMLSR_LOCKED_MASK 0x2UL |
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#define | _ETM_ETMLSR_LOCKED_SHIFT 1 |
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#define | _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL |
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#define | _ETM_ETMLSR_LOCKIMP_MASK 0x1UL |
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#define | _ETM_ETMLSR_LOCKIMP_SHIFT 0 |
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#define | _ETM_ETMLSR_MASK 0x00000003UL |
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#define | _ETM_ETMLSR_RESETVALUE 0x00000003UL |
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#define | _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL |
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#define | _ETM_ETMPDSR_ETMUP_MASK 0x1UL |
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#define | _ETM_ETMPDSR_ETMUP_SHIFT 0 |
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#define | _ETM_ETMPDSR_MASK 0x00000001UL |
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#define | _ETM_ETMPDSR_RESETVALUE 0x00000001UL |
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#define | _ETM_ETMPIDR0_MASK 0x000000FFUL |
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#define | _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL |
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#define | _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL |
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#define | _ETM_ETMPIDR0_PARTNUM_SHIFT 0 |
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#define | _ETM_ETMPIDR0_RESETVALUE 0x00000025UL |
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#define | _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL |
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#define | _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL |
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#define | _ETM_ETMPIDR1_IDCODE_SHIFT 4 |
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#define | _ETM_ETMPIDR1_MASK 0x000000FFUL |
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#define | _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL |
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#define | _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL |
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#define | _ETM_ETMPIDR1_PARTNUM_SHIFT 0 |
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#define | _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL |
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#define | _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL |
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#define | _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL |
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#define | _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 |
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#define | _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL |
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#define | _ETM_ETMPIDR2_IDCODE_MASK 0x7UL |
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#define | _ETM_ETMPIDR2_IDCODE_SHIFT 0 |
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#define | _ETM_ETMPIDR2_MASK 0x000000FFUL |
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#define | _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL |
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#define | _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL |
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#define | _ETM_ETMPIDR2_REV_MASK 0xF0UL |
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#define | _ETM_ETMPIDR2_REV_SHIFT 4 |
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#define | _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL |
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#define | _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL |
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#define | _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 |
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#define | _ETM_ETMPIDR3_MASK 0x000000FFUL |
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#define | _ETM_ETMPIDR3_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL |
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#define | _ETM_ETMPIDR3_REVAND_MASK 0xF0UL |
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#define | _ETM_ETMPIDR3_REVAND_SHIFT 4 |
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#define | _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL |
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#define | _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL |
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#define | _ETM_ETMPIDR4_CONTCODE_SHIFT 0 |
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#define | _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMPIDR4_COUNT_MASK 0xF0UL |
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#define | _ETM_ETMPIDR4_COUNT_SHIFT 4 |
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#define | _ETM_ETMPIDR4_MASK 0x000000FFUL |
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#define | _ETM_ETMPIDR4_RESETVALUE 0x00000004UL |
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#define | _ETM_ETMPIDR5_MASK 0x00000000UL |
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#define | _ETM_ETMPIDR5_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMPIDR6_MASK 0x00000000UL |
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#define | _ETM_ETMPIDR6_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMPIDR7_MASK 0x00000000UL |
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#define | _ETM_ETMPIDR7_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL |
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#define | _ETM_ETMSCR_FIFOFULL_MASK 0x100UL |
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#define | _ETM_ETMSCR_FIFOFULL_SHIFT 8 |
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#define | _ETM_ETMSCR_MASK 0x00027F0FUL |
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#define | _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL |
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#define | _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL |
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#define | _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 |
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#define | _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL |
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#define | _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL |
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#define | _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 |
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#define | _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL |
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#define | _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL |
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#define | _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 |
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#define | _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL |
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#define | _ETM_ETMSCR_PORTMODE_MASK 0x800UL |
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#define | _ETM_ETMSCR_PORTMODE_SHIFT 11 |
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#define | _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL |
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#define | _ETM_ETMSCR_PORTSIZE_MASK 0x400UL |
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#define | _ETM_ETMSCR_PORTSIZE_SHIFT 10 |
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#define | _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL |
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#define | _ETM_ETMSCR_PROCNUM_MASK 0x7000UL |
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#define | _ETM_ETMSCR_PROCNUM_SHIFT 12 |
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#define | _ETM_ETMSCR_RESETVALUE 0x00020D09UL |
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#define | _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL |
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#define | _ETM_ETMSR_ETHOF_MASK 0x1UL |
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#define | _ETM_ETMSR_ETHOF_SHIFT 0 |
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#define | _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL |
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#define | _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL |
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#define | _ETM_ETMSR_ETMPROGBIT_SHIFT 1 |
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#define | _ETM_ETMSR_MASK 0x0000000FUL |
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#define | _ETM_ETMSR_RESETVALUE 0x00000002UL |
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#define | _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMSR_TRACESTAT_MASK 0x4UL |
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#define | _ETM_ETMSR_TRACESTAT_SHIFT 2 |
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#define | _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMSR_TRIGBIT_MASK 0x8UL |
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#define | _ETM_ETMSR_TRIGBIT_SHIFT 3 |
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#define | _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL |
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#define | _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL |
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#define | _ETM_ETMSYNCFR_FREQ_SHIFT 0 |
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#define | _ETM_ETMSYNCFR_MASK 0x00000FFFUL |
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#define | _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL |
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#define | _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL |
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#define | _ETM_ETMTECR1_ADRCMP_SHIFT 0 |
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#define | _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL |
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#define | _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL |
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#define | _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL |
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#define | _ETM_ETMTECR1_INCEXCTL_SHIFT 24 |
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#define | _ETM_ETMTECR1_MASK 0x03FFFFFFUL |
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#define | _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL |
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#define | _ETM_ETMTECR1_MEMMAP_SHIFT 8 |
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#define | _ETM_ETMTECR1_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTECR1_TCE_DIS 0x00000001UL |
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#define | _ETM_ETMTECR1_TCE_EN 0x00000000UL |
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#define | _ETM_ETMTECR1_TCE_MASK 0x2000000UL |
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#define | _ETM_ETMTECR1_TCE_SHIFT 25 |
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#define | _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL |
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#define | _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 |
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#define | _ETM_ETMTEEVR_MASK 0x0001FFFFUL |
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#define | _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTEEVR_RESA_MASK 0x7FUL |
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#define | _ETM_ETMTEEVR_RESA_SHIFT 0 |
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#define | _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTEEVR_RESB_MASK 0x3F80UL |
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#define | _ETM_ETMTEEVR_RESB_SHIFT 7 |
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#define | _ETM_ETMTEEVR_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMTESSEICR_MASK 0x000F000FUL |
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#define | _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL |
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#define | _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 |
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#define | _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL |
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#define | _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 |
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#define | _ETM_ETMTRACEIDR_MASK 0x0000007FUL |
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#define | _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL |
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#define | _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 |
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#define | _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL |
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#define | _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 |
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#define | _ETM_ETMTRIGGER_MASK 0x0001FFFFUL |
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#define | _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTRIGGER_RESA_MASK 0x7FUL |
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#define | _ETM_ETMTRIGGER_RESA_SHIFT 0 |
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#define | _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL |
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#define | _ETM_ETMTRIGGER_RESB_SHIFT 7 |
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#define | _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL |
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#define | _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL |
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#define | _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 |
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#define | _ETM_ETMTSEVR_MASK 0x0001FFFFUL |
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#define | _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL |
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#define | _ETM_ETMTSEVR_RESAEVT_SHIFT 0 |
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#define | _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL |
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#define | _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL |
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#define | _ETM_ETMTSEVR_RESBEVT_SHIFT 7 |
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#define | _ETM_ETMTSEVR_RESETVALUE 0x00000000UL |
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#define | _ETM_ITTRIGOUT_MASK 0x00000001UL |
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#define | _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL |
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#define | _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL |
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#define | _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL |
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#define | _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 |
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#define | ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) |
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#define | ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) |
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#define | ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) |
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#define | ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) |
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#define | ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) |
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#define | ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) |
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#define | ETM_ETMCCER_DADDRCMP (0x1UL << 12) |
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#define | ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) |
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#define | ETM_ETMCCER_EICEIMP (0x1UL << 21) |
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#define | ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) |
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#define | ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) |
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#define | ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) |
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#define | ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) |
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#define | ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) |
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#define | ETM_ETMCCER_READREGS (0x1UL << 11) |
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#define | ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) |
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#define | ETM_ETMCCER_RFCNT (0x1UL << 27) |
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#define | ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) |
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#define | ETM_ETMCCER_TEICEWPNT (0x1UL << 20) |
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#define | ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) |
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#define | ETM_ETMCCER_TENC (0x1UL << 28) |
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#define | ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) |
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#define | ETM_ETMCCER_TIMP (0x1UL << 22) |
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#define | ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) |
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#define | ETM_ETMCCER_TSIZE (0x1UL << 29) |
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#define | ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) |
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#define | ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) |
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#define | ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) |
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#define | ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) |
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#define | ETM_ETMCCR_ETMID (0x1UL << 31) |
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#define | ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) |
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#define | ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) |
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#define | ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) |
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#define | ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) |
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#define | ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) |
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#define | ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) |
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#define | ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) |
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#define | ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) |
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#define | ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) |
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#define | ETM_ETMCCR_MMACCESS (0x1UL << 27) |
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#define | ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) |
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#define | ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) |
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#define | ETM_ETMCCR_SEQPRES (0x1UL << 16) |
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#define | ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) |
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#define | ETM_ETMCCR_TRACESS (0x1UL << 26) |
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#define | ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) |
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#define | ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) |
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#define | ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) |
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#define | ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) |
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#define | ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) |
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#define | ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) |
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#define | ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) |
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#define | ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) |
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#define | ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) |
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#define | ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) |
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#define | ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) |
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#define | ETM_ETMCR_DBGREQCTRL (0x1UL << 9) |
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#define | ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) |
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#define | ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) |
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#define | ETM_ETMCR_ETMPORTSEL (0x1UL << 11) |
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#define | ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) |
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#define | ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) |
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#define | ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) |
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#define | ETM_ETMCR_ETMPROG (0x1UL << 10) |
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#define | ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) |
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#define | ETM_ETMCR_PORTMODE2 (0x1UL << 13) |
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#define | ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) |
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#define | ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) |
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#define | ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) |
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#define | ETM_ETMCR_POWERDWN (0x1UL << 0) |
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#define | ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) |
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#define | ETM_ETMCR_STALL (0x1UL << 7) |
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#define | ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) |
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#define | ETM_ETMCR_TSTAMPEN (0x1UL << 28) |
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#define | ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) |
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#define | ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) |
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#define | ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) |
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#define | ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) |
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#define | ETM_ETMIDR2_RFE (0x1UL << 0) |
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#define | ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) |
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#define | ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) |
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#define | ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) |
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#define | ETM_ETMIDR2_SWP (0x1UL << 1) |
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#define | ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) |
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#define | ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) |
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#define | ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) |
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#define | ETM_ETMIDR_BPE (0x1UL << 20) |
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#define | ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) |
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#define | ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) |
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#define | ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) |
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#define | ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) |
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#define | ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) |
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#define | ETM_ETMIDR_LPCF (0x1UL << 16) |
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#define | ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) |
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#define | ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) |
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#define | ETM_ETMIDR_SECEXT (0x1UL << 19) |
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#define | ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) |
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#define | ETM_ETMIDR_THUMBT (0x1UL << 18) |
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#define | ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) |
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#define | ETM_ETMISCIN_COREHALT (0x1UL << 4) |
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#define | ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) |
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#define | ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) |
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#define | ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) |
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#define | ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) |
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#define | ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) |
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#define | ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) |
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#define | ETM_ETMITCTRL_ITEN (0x1UL << 0) |
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#define | ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) |
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#define | ETM_ETMLAR_KEY (0x1UL << 0) |
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#define | ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) |
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#define | ETM_ETMLSR_LOCKED (0x1UL << 1) |
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#define | ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) |
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#define | ETM_ETMLSR_LOCKIMP (0x1UL << 0) |
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#define | ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) |
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#define | ETM_ETMPDSR_ETMUP (0x1UL << 0) |
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#define | ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) |
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#define | ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) |
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#define | ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) |
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#define | ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) |
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#define | ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) |
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#define | ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) |
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#define | ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) |
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#define | ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) |
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#define | ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) |
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#define | ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) |
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#define | ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) |
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#define | ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) |
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#define | ETM_ETMSCR_FIFOFULL (0x1UL << 8) |
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#define | ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) |
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#define | ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) |
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#define | ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) |
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#define | ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) |
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#define | ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) |
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#define | ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) |
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#define | ETM_ETMSCR_PORTMODE (0x1UL << 11) |
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#define | ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) |
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#define | ETM_ETMSCR_PORTSIZE (0x1UL << 10) |
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#define | ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) |
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#define | ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) |
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#define | ETM_ETMSR_ETHOF (0x1UL << 0) |
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#define | ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) |
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#define | ETM_ETMSR_ETMPROGBIT (0x1UL << 1) |
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#define | ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) |
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#define | ETM_ETMSR_TRACESTAT (0x1UL << 2) |
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#define | ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) |
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#define | ETM_ETMSR_TRIGBIT (0x1UL << 3) |
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#define | ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) |
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#define | ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) |
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#define | ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) |
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#define | ETM_ETMTECR1_INCEXCTL (0x1UL << 24) |
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#define | ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) |
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#define | ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) |
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#define | ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) |
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#define | ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) |
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#define | ETM_ETMTECR1_TCE (0x1UL << 25) |
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#define | ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) |
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#define | ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) |
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#define | ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) |
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#define | ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) |
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#define | ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) |
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#define | ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) |
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#define | ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) |
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#define | ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) |
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#define | ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) |
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#define | ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) |
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#define | ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) |
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#define | ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) |
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#define | ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) |
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#define | ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) |
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#define | ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) |
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#define | ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) |
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#define | ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) |
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