16 #ifndef __SILICON_LABS_DMADRV_H__
17 #define __SILICON_LABS_DMADRV_H__
22 #if defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
23 #define EMDRV_DMADRV_UDMA
24 #define EMDRV_DMADRV_DMA_PRESENT
26 #elif defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
27 #define EMDRV_DMADRV_LDMA
28 #define EMDRV_DMADRV_DMA_PRESENT
31 #error "No valid DMA engine defined."
34 #include "dmadrv_config.h"
50 #define ECODE_EMDRV_DMADRV_OK ( ECODE_OK )
51 #define ECODE_EMDRV_DMADRV_PARAM_ERROR ( ECODE_EMDRV_DMADRV_BASE | 0x00000001 )
52 #define ECODE_EMDRV_DMADRV_NOT_INITIALIZED ( ECODE_EMDRV_DMADRV_BASE | 0x00000002 )
53 #define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED ( ECODE_EMDRV_DMADRV_BASE | 0x00000003 )
54 #define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED ( ECODE_EMDRV_DMADRV_BASE | 0x00000004 )
55 #define ECODE_EMDRV_DMADRV_IN_USE ( ECODE_EMDRV_DMADRV_BASE | 0x00000005 )
56 #define ECODE_EMDRV_DMADRV_ALREADY_FREED ( ECODE_EMDRV_DMADRV_BASE | 0x00000006 )
57 #define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED ( ECODE_EMDRV_DMADRV_BASE | 0x00000007 )
81 unsigned int sequenceNo,
84 #if defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
87 #define DMADRV_MAX_XFER_COUNT ((int)((_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT) + 1))
93 #if defined( DMAREQ_ADC0_SCAN )
96 #if defined( DMAREQ_ADC0_SINGLE )
99 #if defined( DMAREQ_AES_DATARD )
100 dmadrvPeripheralSignal_AES_DATARD = DMAREQ_AES_DATARD,
102 #if defined( DMAREQ_AES_DATAWR )
103 dmadrvPeripheralSignal_AES_DATAWR = DMAREQ_AES_DATAWR,
105 #if defined( DMAREQ_AES_KEYWR )
106 dmadrvPeripheralSignal_AES_KEYWR = DMAREQ_AES_KEYWR,
108 #if defined( DMAREQ_AES_XORDATAWR )
109 dmadrvPeripheralSignal_AES_XORDATAWR = DMAREQ_AES_XORDATAWR,
111 #if defined( DMAREQ_DAC0_CH0 )
112 dmadrvPeripheralSignal_DAC0_CH0 = DMAREQ_DAC0_CH0,
114 #if defined( DMAREQ_DAC0_CH1 )
115 dmadrvPeripheralSignal_DAC0_CH1 = DMAREQ_DAC0_CH1,
117 #if defined( DMAREQ_EBI_DDEMPTY )
118 dmadrvPeripheralSignal_EBI_DDEMPTY = DMAREQ_EBI_DDEMPTY,
120 #if defined( DMAREQ_EBI_PXL0EMPTY )
121 dmadrvPeripheralSignal_EBI_PXL0EMPTY = DMAREQ_EBI_PXL0EMPTY,
123 #if defined( DMAREQ_EBI_PXL1EMPTY )
124 dmadrvPeripheralSignal_EBI_PXL1EMPTY = DMAREQ_EBI_PXL1EMPTY,
126 #if defined( DMAREQ_EBI_PXLFULL )
127 dmadrvPeripheralSignal_EBI_PXLFULL = DMAREQ_EBI_PXLFULL,
129 #if defined( DMAREQ_I2C0_RXDATAV )
132 #if defined( DMAREQ_I2C0_TXBL )
135 #if defined( DMAREQ_I2C1_RXDATAV )
138 #if defined( DMAREQ_I2C1_TXBL )
141 #if defined( DMAREQ_LESENSE_BUFDATAV )
144 #if defined( DMAREQ_LEUART0_RXDATAV )
147 #if defined( DMAREQ_LEUART0_TXBL )
150 #if defined( DMAREQ_LEUART0_TXEMPTY )
153 #if defined( DMAREQ_LEUART1_RXDATAV )
154 dmadrvPeripheralSignal_LEUART1_RXDATAV = DMAREQ_LEUART1_RXDATAV,
156 #if defined( DMAREQ_LEUART1_TXBL )
157 dmadrvPeripheralSignal_LEUART1_TXBL = DMAREQ_LEUART1_TXBL,
159 #if defined( DMAREQ_LEUART1_TXEMPTY )
160 dmadrvPeripheralSignal_LEUART1_TXEMPTY = DMAREQ_LEUART1_TXEMPTY,
162 #if defined( DMAREQ_MSC_WDATA )
165 #if defined( DMAREQ_TIMER0_CC0 )
168 #if defined( DMAREQ_TIMER0_CC1 )
171 #if defined( DMAREQ_TIMER0_CC2 )
174 #if defined( DMAREQ_TIMER0_UFOF )
177 #if defined( DMAREQ_TIMER1_CC0 )
180 #if defined( DMAREQ_TIMER1_CC1 )
183 #if defined( DMAREQ_TIMER1_CC2 )
186 #if defined( DMAREQ_TIMER1_UFOF )
189 #if defined( DMAREQ_TIMER2_CC0 )
190 dmadrvPeripheralSignal_TIMER2_CC0 = DMAREQ_TIMER2_CC0,
192 #if defined( DMAREQ_TIMER2_CC1 )
193 dmadrvPeripheralSignal_TIMER2_CC1 = DMAREQ_TIMER2_CC1,
195 #if defined( DMAREQ_TIMER2_CC2 )
196 dmadrvPeripheralSignal_TIMER2_CC2 = DMAREQ_TIMER2_CC2,
198 #if defined( DMAREQ_TIMER2_UFOF )
199 dmadrvPeripheralSignal_TIMER2_UFOF = DMAREQ_TIMER2_UFOF,
201 #if defined( DMAREQ_TIMER3_CC0 )
202 dmadrvPeripheralSignal_TIMER3_CC0 = DMAREQ_TIMER3_CC0,
204 #if defined( DMAREQ_TIMER3_CC1 )
205 dmadrvPeripheralSignal_TIMER3_CC1 = DMAREQ_TIMER3_CC1,
207 #if defined( DMAREQ_TIMER3_CC2 )
208 dmadrvPeripheralSignal_TIMER3_CC2 = DMAREQ_TIMER3_CC2,
210 #if defined( DMAREQ_TIMER3_UFOF )
211 dmadrvPeripheralSignal_TIMER3_UFOF = DMAREQ_TIMER3_UFOF,
213 #if defined( DMAREQ_UART0_RXDATAV )
214 dmadrvPeripheralSignal_UART0_RXDATAV = DMAREQ_UART0_RXDATAV,
216 #if defined( DMAREQ_UART0_TXBL )
217 dmadrvPeripheralSignal_UART0_TXBL = DMAREQ_UART0_TXBL,
219 #if defined( DMAREQ_UART0_TXEMPTY )
220 dmadrvPeripheralSignal_UART0_TXEMPTY = DMAREQ_UART0_TXEMPTY,
222 #if defined( DMAREQ_UART1_RXDATAV )
223 dmadrvPeripheralSignal_UART1_RXDATAV = DMAREQ_UART1_RXDATAV,
225 #if defined( DMAREQ_UART1_TXBL )
226 dmadrvPeripheralSignal_UART1_TXBL = DMAREQ_UART1_TXBL,
228 #if defined( DMAREQ_UART1_TXEMPTY )
229 dmadrvPeripheralSignal_UART1_TXEMPTY = DMAREQ_UART1_TXEMPTY,
231 #if defined( DMAREQ_USART0_RXDATAV )
234 #if defined( DMAREQ_USART0_TXBL )
237 #if defined( DMAREQ_USART0_TXEMPTY )
240 #if defined( DMAREQ_USARTRF0_RXDATAV )
241 dmadrvPeripheralSignal_USARTRF0_RXDATAV = DMAREQ_USARTRF0_RXDATAV,
243 #if defined( DMAREQ_USARTRF0_TXBL )
244 dmadrvPeripheralSignal_USARTRF0_TXBL = DMAREQ_USARTRF0_TXBL,
246 #if defined( DMAREQ_USARTRF0_TXEMPTY )
247 dmadrvPeripheralSignal_USARTRF0_TXEMPTY = DMAREQ_USARTRF0_TXEMPTY,
249 #if defined( DMAREQ_USARTRF1_RXDATAV )
250 dmadrvPeripheralSignal_USARTRF1_RXDATAV = DMAREQ_USARTRF1_RXDATAV,
252 #if defined( DMAREQ_USARTRF1_TXBL )
253 dmadrvPeripheralSignal_USARTRF1_TXBL = DMAREQ_USARTRF1_TXBL,
255 #if defined( DMAREQ_USARTRF1_TXEMPTY )
256 dmadrvPeripheralSignal_USARTRF1_TXEMPTY = DMAREQ_USARTRF1_TXEMPTY,
258 #if defined( DMAREQ_USART1_RXDATAV )
261 #if defined( DMAREQ_USART1_RXDATAVRIGHT )
264 #if defined( DMAREQ_USART1_TXBL )
267 #if defined( DMAREQ_USART1_TXBLRIGHT )
270 #if defined( DMAREQ_USART1_TXEMPTY )
273 #if defined( DMAREQ_USART2_RXDATAV )
276 #if defined( DMAREQ_USART2_RXDATAVRIGHT )
277 dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = DMAREQ_USART2_RXDATAVRIGHT,
279 #if defined( DMAREQ_USART2_TXBL )
282 #if defined( DMAREQ_USART2_TXBLRIGHT )
283 dmadrvPeripheralSignal_USART2_TXBLRIGHT = DMAREQ_USART2_TXBLRIGHT,
285 #if defined( DMAREQ_USART2_TXEMPTY )
289 } DMADRV_Peripheralsignal_t;
306 #endif // defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
308 #if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
311 #define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1))
317 #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN )
320 #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE )
323 #if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI )
324 dmadrvPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC,
326 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD )
327 dmadrvPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
329 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR )
330 dmadrvPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
332 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR )
333 dmadrvPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
335 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD )
336 dmadrvPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
338 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR )
339 dmadrvPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
341 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD )
344 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR )
347 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR )
350 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD )
353 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR )
356 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD )
359 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR )
362 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR )
365 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD )
368 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR )
371 #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV )
374 #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL )
377 #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV )
380 #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL )
383 #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY )
386 #if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG )
387 dmadrvPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM,
389 #if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA )
392 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF )
393 dmadrvPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
395 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 )
396 dmadrvPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
398 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 )
399 dmadrvPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
401 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 )
402 dmadrvPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
404 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 )
405 dmadrvPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
407 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 )
408 dmadrvPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
410 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF )
411 dmadrvPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
413 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF )
414 dmadrvPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
416 #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 )
419 #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 )
422 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 )
425 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 )
428 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 )
431 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF )
434 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 )
437 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 )
440 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 )
443 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 )
446 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF )
449 #if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV )
452 #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL )
455 #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY )
458 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV )
461 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT )
464 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL )
467 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT )
470 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY )
473 #if defined( LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV )
476 #if defined( LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT )
479 #if defined( LDMA_CH_REQSEL_SIGSEL_USART2TXBL )
482 #if defined( LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT )
485 #if defined( LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY )
488 #if defined( LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV )
489 dmadrvPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3,
491 #if defined( LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT )
492 dmadrvPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3,
494 #if defined( LDMA_CH_REQSEL_SIGSEL_USART3TXBL )
495 dmadrvPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3,
497 #if defined( LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT )
498 dmadrvPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3,
500 #if defined( LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY )
501 dmadrvPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3
522 #if !defined( EMDRV_DMADRV_USE_NATIVE_API ) || defined( DOXY_DOC_ONLY )
544 unsigned int channelId,
556 unsigned int channelId,
569 #if defined( EMDRV_DMADRV_LDMA ) && defined( EMDRV_DMADRV_USE_NATIVE_API )
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR
DMA transfer configuration structure.
#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2
#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2
#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0
#define DMAREQ_ADC0_SINGLE
#define LDMA_CH_REQSEL_SOURCESEL_TIMER1
#define DMAREQ_USART1_TXBL
Trig on CRYPTO0_DATA0XWR.
#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0
#define DMAREQ_USART1_RXDATAV
#define DMAREQ_LEUART0_TXBL
Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a peripheral to memory DMA transfer.
#define DMAREQ_TIMER0_UFOF
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD
Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active)
Check if a transfer is running.
Energy Aware drivers error code definitions.
#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV
#define LDMA_CH_REQSEL_SOURCESEL_LEUART0
#define DMAREQ_USART0_TXEMPTY
bool(* DMADRV_Callback_t)(unsigned int channel, unsigned int sequenceNo, void *userParam)
DMADRV transfer completion callback function.
#define DMAREQ_USART0_RXDATAV
#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF
#define DMAREQ_USART0_TXBL
Ecode_t DMADRV_StopTransfer(unsigned int channelId)
Stop an ongoing DMA transfer.
#define DMAREQ_I2C0_RXDATAV
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
DMADRV_DataSize_t
Data size of one LDMA transfer item.
#define DMAREQ_USART1_RXDATAVRIGHT
#define DMAREQ_TIMER1_CC2
#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL
#define DMAREQ_LEUART0_RXDATAV
#define DMAREQ_USART2_RXDATAV
Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done)
Check if a transfer has completed.
#define LDMA_CH_REQSEL_SOURCESEL_USART2
#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY
#define DMAREQ_TIMER0_CC1
#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV
#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR
Trig on USART1_TXBLRIGHT.
Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, int *remaining)
Get number of items remaining in a transfer.
Ecode_t DMADRV_ResumeTransfer(unsigned int channelId)
Resume an ongoing DMA transfer.
#define DMAREQ_TIMER1_UFOF
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR
Ecode_t DMADRV_LdmaStartTransfer(int channelId, LDMA_TransferCfg_t *transfer, LDMA_Descriptor_t *descriptor, DMADRV_Callback_t callback, void *cbUserParam)
Start a LDMA transfer.
#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL
#define DMAREQ_I2C1_RXDATAV
#define DMAREQ_USART2_TXEMPTY
Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src0, void *src1, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a memory to peripheral ping-pong DMA transfer.
#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO1
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD
uint32_t Ecode_t
Typedef for API function error code return values.
No peripheral selected for DMA triggering.
Trig on USART1_RXDATAVRIGHT.
#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3
#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY
#define LDMA_CH_REQSEL_SOURCESEL_NONE
Ecode_t DMADRV_Init(void)
Initialize DMADRV.
Trig on CRYPTO1_DATA0XWR.
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0
#define LDMA_CH_REQSEL_SOURCESEL_MSC
#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF
#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR
Direct memory access (LDMA) API.
#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA
#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV
#define DMAREQ_USART2_TXBL
Ecode_t DMADRV_DeInit(void)
Deinitialize DMADRV.
#define DMAREQ_LESENSE_BUFDATAV
#define LDMA_CH_REQSEL_SOURCESEL_USART0
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR
#define LDMA_CH_REQSEL_SOURCESEL_PRS
#define DMAREQ_USART1_TXEMPTY
#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN
Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities)
Allocate (reserve) a DMA channel.
#define DMAREQ_LEUART0_TXEMPTY
#define DMAREQ_USART1_TXBLRIGHT
#define DMAREQ_TIMER0_CC0
Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a memory to peripheral DMA transfer.
#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY
#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT
DMADRV_PeripheralSignal_t
Peripherals that can trigger LDMA transfers.
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD
#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL
#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL
Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending)
Check if a transfer complete is pending.
#define DMAREQ_TIMER1_CC0
#define DMAREQ_TIMER1_CC1
#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT
#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0
Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst0, void *dst1, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a peripheral to memory ping-pong DMA transfer.
#define LDMA_CH_REQSEL_SOURCESEL_USART1
Direct memory access (DMA) API.
#define LDMA_CH_REQSEL_SOURCESEL_ADC0
Ecode_t DMADRV_PauseTransfer(unsigned int channelId)
Pause an ongoing DMA transfer.
Ecode_t DMADRV_FreeChannel(unsigned int channelId)
Free an allocate (reserved) DMA channel.
#define DMAREQ_TIMER0_CC2
#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY
#define LDMA_CH_REQSEL_SOURCESEL_TIMER0
#define LDMA_CH_REQSEL_SOURCESEL_I2C0
#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1
#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE