EFR32 Mighty Gecko 12 Software Documentation  efr32mg12-doc-5.1.2
em_smu.h
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1 /***************************************************************************/
33 #ifndef EM_SMU_H
34 #define EM_SMU_H
35 
36 #include "em_device.h"
37 #if defined(SMU_COUNT) && (SMU_COUNT > 0)
38 
39 #include "em_assert.h"
40 #include "em_bus.h"
41 
42 #include <stdint.h>
43 #include <stdbool.h>
44 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
49 /***************************************************************************/
54 /***************************************************************************/
74 /*******************************************************************************
75  ******************************** ENUMS ************************************
76  ******************************************************************************/
77 
79 typedef enum {
80 
81 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
82  smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT,
83  smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT,
84  smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT,
85  smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT,
86  smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT,
87  smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT,
88  smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT,
89  smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT,
90  smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT,
91  smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT,
92  smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT,
93  smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT,
94  smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT,
95  smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT,
96  smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT,
97  smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT,
98  smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT,
99  smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT,
100  smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT,
101  smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT,
102  smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT,
103  smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT,
104  smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT,
105  smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT,
106  smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT,
107  smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT,
108  smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT,
109  smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT,
110  smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT,
111  smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT,
112  smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT,
113  smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT,
114  smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT,
115  smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT,
116  smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT,
117  smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT,
118  smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT,
119  smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT,
120  smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT,
122 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
123  smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT,
124  smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT,
125  smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT,
126  smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT,
127  smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT,
128  smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT,
129  smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT,
130  smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT,
131  smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT,
132  smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT,
133  smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT,
134  smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT,
135  smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT,
136  smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT,
137  smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT,
138  smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT,
139  smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT,
140  smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT,
141  smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT,
142  smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT,
143  smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT,
144  smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT,
145  smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT,
146  smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT,
147  smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT,
148  smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT,
149  smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT,
150  smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT,
151  smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT,
152  smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT,
153  smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT,
154  smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT,
155  smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT,
156  smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT,
157  smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT,
159 #else
160 #error "No peripherals defined for SMU for this device configuration."
161 #endif
162  smuPeripheralEnd
163 } SMU_Peripheral_TypeDef;
164 
166 typedef struct {
167 
168 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
169  bool privilegedACMP0 : 1;
170  bool privilegedACMP1 : 1;
171  bool privilegedADC0 : 1;
172  bool privilegedReserved0 : 1;
173  bool privilegedReserved1 : 1;
174  bool privilegedCMU : 1;
175  bool privilegedReserved2 : 1;
176  bool privilegedCRYOTIMER : 1;
177  bool privilegedCRYPTO0 : 1;
178  bool privilegedCRYPTO1 : 1;
179  bool privilegedCSEN : 1;
180  bool privilegedVDAC0 : 1;
181  bool privilegedPRS : 1;
182  bool privilegedEMU : 1;
183  bool privilegedFPUEH : 1;
184  bool privilegedReserved3 : 1;
185  bool privilegedGPCRC : 1;
186  bool privilegedGPIO : 1;
187  bool privilegedI2C0 : 1;
188  bool privilegedI2C1 : 1;
189  bool privilegedIDAC0 : 1;
190  bool privilegedMSC : 1;
191  bool privilegedLDMA : 1;
192  bool privilegedLESENSE : 1;
193  bool privilegedLETIMER0 : 1;
194  bool privilegedLEUART0 : 1;
195  bool privilegedReserved4 : 1;
196  bool privilegedPCNT0 : 1;
197  bool privilegedPCNT1 : 1;
198  bool privilegedPCNT2 : 1;
199  bool privilegedReserved5 : 1;
200  bool privilegedReserved6 : 1;
201  bool privilegedReserved7 : 1;
202  bool privilegedRMU : 1;
203  bool privilegedRTCC : 1;
204  bool privilegedSMU : 1;
205  bool privilegedReserved8 : 1;
206  bool privilegedTIMER0 : 1;
207  bool privilegedTIMER1 : 1;
208  bool privilegedTRNG0 : 1;
209  bool privilegedUSART0 : 1;
210  bool privilegedUSART1 : 1;
211  bool privilegedUSART2 : 1;
212  bool privilegedUSART3 : 1;
213  bool privilegedWDOG0 : 1;
214  bool privilegedWDOG1 : 1;
215  bool privilegedWTIMER0 : 1;
216  bool privilegedWTIMER1 : 1;
218 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
219  bool privilegedACMP0 : 1;
220  bool privilegedACMP1 : 1;
221  bool privilegedADC0 : 1;
222  bool privilegedReserved0 : 1;
223  bool privilegedReserved1 : 1;
224  bool privilegedCMU : 1;
225  bool privilegedReserved2 : 1;
226  bool privilegedCRYOTIMER : 1;
227  bool privilegedCRYPTO0 : 1;
228  bool privilegedCRYPTO1 : 1;
229  bool privilegedCSEN : 1;
230  bool privilegedVDAC0 : 1;
231  bool privilegedPRS : 1;
232  bool privilegedEMU : 1;
233  bool privilegedFPUEH : 1;
234  bool privilegedReserved3 : 1;
235  bool privilegedGPCRC : 1;
236  bool privilegedGPIO : 1;
237  bool privilegedI2C0 : 1;
238  bool privilegedI2C1 : 1;
239  bool privilegedIDAC0 : 1;
240  bool privilegedMSC : 1;
241  bool privilegedLDMA : 1;
242  bool privilegedLESENSE : 1;
243  bool privilegedLETIMER0 : 1;
244  bool privilegedLEUART0 : 1;
245  bool privilegedReserved4 : 1;
246  bool privilegedPCNT0 : 1;
247  bool privilegedReserved5 : 1;
248  bool privilegedReserved6 : 1;
249  bool privilegedReserved7 : 1;
250  bool privilegedReserved8 : 1;
251  bool privilegedRMU : 1;
252  bool privilegedRTCC : 1;
253  bool privilegedSMU : 1;
254  bool privilegedReserved9 : 1;
255  bool privilegedTIMER0 : 1;
256  bool privilegedTIMER1 : 1;
257  bool privilegedTRNG0 : 1;
258  bool privilegedUSART0 : 1;
259  bool privilegedUSART1 : 1;
260  bool privilegedUSART2 : 1;
261  bool privilegedWDOG0 : 1;
262  bool privilegedWDOG1 : 1;
263  bool privilegedWTIMER0 : 1;
265 #else
266 #error "No peripherals defined for SMU for this device configuration"
267 #endif
268 } SMU_PrivilegedAccess_TypeDef;
269 
270 /*******************************************************************************
271  ****************************** STRUCTS ************************************
272  ******************************************************************************/
273 
275 typedef struct {
276  union {
277  uint32_t reg[2];
278  SMU_PrivilegedAccess_TypeDef access;
279  } ppu;
280  bool enable;
281 } SMU_Init_TypeDef;
282 
283 #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80)
284 
285 #define SMU_INIT_DEFAULT { \
286  {{0}}, /* No peripherals acsess protected. */ \
287  true /* Enable SMU.*/ \
288 }
289 #endif
290 
291 /*******************************************************************************
292  ***************************** PROTOTYPES **********************************
293  ******************************************************************************/
294 
295 /***************************************************************************/
302 __STATIC_INLINE void SMU_EnablePPU(bool enable)
303 {
304  BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable);
305 }
306 
307 /***************************************************************************/
315 __STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init)
316 {
317  SMU->PPUPATD0 = init->ppu.reg[0];
318  SMU->PPUPATD1 = init->ppu.reg[1];
319 
320  SMU_EnablePPU(init->enable);
321 }
322 
323 /***************************************************************************/
338 __STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral,
339  bool privileged)
340 {
341  EFM_ASSERT(peripheral < smuPeripheralEnd);
342 
343  if (peripheral < 32) {
344  BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged);
345  } else {
346  BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged);
347  }
348 }
349 
350 /***************************************************************************/
361 __STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void)
362 {
363  return (SMU_Peripheral_TypeDef)SMU->PPUFS;
364 }
365 
366 /***************************************************************************/
373 __STATIC_INLINE void SMU_IntClear(uint32_t flags)
374 {
375  SMU->IFC = flags;
376 }
377 
378 /***************************************************************************/
385 __STATIC_INLINE void SMU_IntDisable(uint32_t flags)
386 {
387  SMU->IEN &= ~flags;
388 }
389 
390 /***************************************************************************/
402 __STATIC_INLINE void SMU_IntEnable(uint32_t flags)
403 {
404  SMU->IEN |= flags;
405 }
406 
407 /***************************************************************************/
414 __STATIC_INLINE uint32_t SMU_IntGet(void)
415 {
416  return SMU->IF;
417 }
418 
419 /***************************************************************************/
434 __STATIC_INLINE uint32_t SMU_IntGetEnabled(void)
435 {
436  uint32_t tmp;
437 
438  // Store SMU->IEN in temporary variable in order to define explicit order
439  // of volatile accesses.
440  tmp = SMU->IEN;
441 
442  // Bitwise AND of pending and enabled interrupts
443  return SMU->IF & tmp;
444 }
445 
446 /************************************************************************Æ**/
453 __STATIC_INLINE void SMU_IntSet(uint32_t flags)
454 {
455  SMU->IFS = flags;
456 }
457 
461 #ifdef __cplusplus
462 }
463 #endif
464 
465 #endif // defined(SMU_COUNT) && (SMU_COUNT > 0)
466 #endif // EM_SMU_H
_SMU_PPUPATD0_LDMA_SHIFT
#define _SMU_PPUPATD0_LDMA_SHIFT
Definition: efr32mg12p_smu.h:203
_SMU_PPUPATD0_VDAC0_SHIFT
#define _SMU_PPUPATD0_VDAC0_SHIFT
Definition: efr32mg12p_smu.h:153
SMU_Init_TypeDef::enable
bool enable
Definition: em_smu.h:280
_SMU_PPUPATD1_SMU_SHIFT
#define _SMU_PPUPATD1_SMU_SHIFT
Definition: efr32mg12p_smu.h:252
_SMU_PPUPATD0_GPIO_SHIFT
#define _SMU_PPUPATD0_GPIO_SHIFT
Definition: efr32mg12p_smu.h:178
_SMU_PPUPATD0_MSC_SHIFT
#define _SMU_PPUPATD0_MSC_SHIFT
Definition: efr32mg12p_smu.h:198
smuPeripheralCRYPTO1
Definition: em_smu.h:88
smuPeripheralADC0
Definition: em_smu.h:84
_SMU_PPUPATD1_TIMER1_SHIFT
#define _SMU_PPUPATD1_TIMER1_SHIFT
Definition: efr32mg12p_smu.h:262
smuPeripheralPRS
Definition: em_smu.h:91
SMU_SetPrivilegedAccess
__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, bool privileged)
Change the access settings for a peripheral.
Definition: em_smu.h:338
smuPeripheralIDAC0
Definition: em_smu.h:98
_SMU_PPUPATD1_WDOG0_SHIFT
#define _SMU_PPUPATD1_WDOG0_SHIFT
Definition: efr32mg12p_smu.h:292
em_assert.h
Emlib peripheral API "assert" implementation.
smuPeripheralVDAC0
Definition: em_smu.h:90
_SMU_PPUPATD0_EMU_SHIFT
#define _SMU_PPUPATD0_EMU_SHIFT
Definition: efr32mg12p_smu.h:163
em_bus.h
RAM and peripheral bit-field set and clear API.
smuPeripheralMSC
Definition: em_smu.h:99
smuPeripheralTIMER0
Definition: em_smu.h:110
_SMU_PPUPATD0_CRYOTIMER_SHIFT
#define _SMU_PPUPATD0_CRYOTIMER_SHIFT
Definition: efr32mg12p_smu.h:133
_SMU_PPUPATD0_LEUART0_SHIFT
#define _SMU_PPUPATD0_LEUART0_SHIFT
Definition: efr32mg12p_smu.h:218
_SMU_PPUPATD1_USART0_SHIFT
#define _SMU_PPUPATD1_USART0_SHIFT
Definition: efr32mg12p_smu.h:272
smuPeripheralPCNT1
Definition: em_smu.h:105
smuPeripheralCSEN
Definition: em_smu.h:89
smuPeripheralTRNG0
Definition: em_smu.h:112
SMU_GetFaultingPeripheral
__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void)
Get the ID of the peripheral that caused an access fault.
Definition: em_smu.h:361
_SMU_PPUPATD0_LESENSE_SHIFT
#define _SMU_PPUPATD0_LESENSE_SHIFT
Definition: efr32mg12p_smu.h:208
smuPeripheralUSART0
Definition: em_smu.h:113
_SMU_PPUPATD1_RMU_SHIFT
#define _SMU_PPUPATD1_RMU_SHIFT
Definition: efr32mg12p_smu.h:242
smuPeripheralWDOG1
Definition: em_smu.h:118
em_device.h
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
SMU_Init_TypeDef::reg
uint32_t reg[2]
Definition: em_smu.h:277
smuPeripheralWTIMER0
Definition: em_smu.h:119
_SMU_PPUPATD1_TRNG0_SHIFT
#define _SMU_PPUPATD1_TRNG0_SHIFT
Definition: efr32mg12p_smu.h:267
_SMU_PPUPATD1_RTCC_SHIFT
#define _SMU_PPUPATD1_RTCC_SHIFT
Definition: efr32mg12p_smu.h:247
SMU_Peripheral_TypeDef
SMU_Peripheral_TypeDef
Definition: em_smu.h:79
_SMU_PPUPATD0_PRS_SHIFT
#define _SMU_PPUPATD0_PRS_SHIFT
Definition: efr32mg12p_smu.h:158
smuPeripheralUSART2
Definition: em_smu.h:115
_SMU_PPUPATD1_USART1_SHIFT
#define _SMU_PPUPATD1_USART1_SHIFT
Definition: efr32mg12p_smu.h:277
_SMU_PPUPATD1_WTIMER0_SHIFT
#define _SMU_PPUPATD1_WTIMER0_SHIFT
Definition: efr32mg12p_smu.h:302
smuPeripheralGPCRC
Definition: em_smu.h:94
SMU_EnablePPU
__STATIC_INLINE void SMU_EnablePPU(bool enable)
Enable or disable the Peripheral Protection Unit of the SMU.
Definition: em_smu.h:302
smuPeripheralI2C0
Definition: em_smu.h:96
smuPeripheralLESENSE
Definition: em_smu.h:101
smuPeripheralRMU
Definition: em_smu.h:107
smuPeripheralPCNT0
Definition: em_smu.h:104
_SMU_PPUPATD1_WDOG1_SHIFT
#define _SMU_PPUPATD1_WDOG1_SHIFT
Definition: efr32mg12p_smu.h:297
SMU_IntDisable
__STATIC_INLINE void SMU_IntDisable(uint32_t flags)
Disable one or more SMU interrupts.
Definition: em_smu.h:385
_SMU_PPUPATD1_TIMER0_SHIFT
#define _SMU_PPUPATD1_TIMER0_SHIFT
Definition: efr32mg12p_smu.h:257
SMU_PrivilegedAccess_TypeDef
Definition: em_smu.h:166
_SMU_PPUPATD0_ACMP1_SHIFT
#define _SMU_PPUPATD0_ACMP1_SHIFT
Definition: efr32mg12p_smu.h:118
_SMU_PPUPATD0_CMU_SHIFT
#define _SMU_PPUPATD0_CMU_SHIFT
Definition: efr32mg12p_smu.h:128
smuPeripheralLEUART0
Definition: em_smu.h:103
SMU_Init
__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init)
Initialize the Peripheral Protection Unit of the SMU.
Definition: em_smu.h:315
_SMU_PPUPATD0_CSEN_SHIFT
#define _SMU_PPUPATD0_CSEN_SHIFT
Definition: efr32mg12p_smu.h:148
smuPeripheralGPIO
Definition: em_smu.h:95
SMU
#define SMU
Definition: efr32mg12p433f1024gl125.h:472
_SMU_PPUPATD0_FPUEH_SHIFT
#define _SMU_PPUPATD0_FPUEH_SHIFT
Definition: efr32mg12p_smu.h:168
SMU_IntGetEnabled
__STATIC_INLINE uint32_t SMU_IntGetEnabled(void)
Get enabled and pending SMU interrupt flags. Useful for handling more interrupt sources in the same i...
Definition: em_smu.h:434
_SMU_PPUPATD0_CRYPTO0_SHIFT
#define _SMU_PPUPATD0_CRYPTO0_SHIFT
Definition: efr32mg12p_smu.h:138
smuPeripheralUSART3
Definition: em_smu.h:116
SMU_IntGet
__STATIC_INLINE uint32_t SMU_IntGet(void)
Get pending SMU interrupts.
Definition: em_smu.h:414
smuPeripheralRTCC
Definition: em_smu.h:108
_SMU_PPUPATD0_CRYPTO1_SHIFT
#define _SMU_PPUPATD0_CRYPTO1_SHIFT
Definition: efr32mg12p_smu.h:143
_SMU_PPUPATD0_I2C0_SHIFT
#define _SMU_PPUPATD0_I2C0_SHIFT
Definition: efr32mg12p_smu.h:183
smuPeripheralEMU
Definition: em_smu.h:92
_SMU_PPUPATD0_PCNT2_SHIFT
#define _SMU_PPUPATD0_PCNT2_SHIFT
Definition: efr32mg12p_smu.h:233
_SMU_PPUPATD0_ADC0_SHIFT
#define _SMU_PPUPATD0_ADC0_SHIFT
Definition: efr32mg12p_smu.h:123
SMU_IntEnable
__STATIC_INLINE void SMU_IntEnable(uint32_t flags)
Enable one or more SMU interrupts.
Definition: em_smu.h:402
smuPeripheralLDMA
Definition: em_smu.h:100
smuPeripheralCRYOTIMER
Definition: em_smu.h:86
smuPeripheralSMU
Definition: em_smu.h:109
SMU_IntSet
__STATIC_INLINE void SMU_IntSet(uint32_t flags)
Set one or more pending SMU interrupts from SW.
Definition: em_smu.h:453
_SMU_PPUPATD0_I2C1_SHIFT
#define _SMU_PPUPATD0_I2C1_SHIFT
Definition: efr32mg12p_smu.h:188
_SMU_PPUPATD0_PCNT1_SHIFT
#define _SMU_PPUPATD0_PCNT1_SHIFT
Definition: efr32mg12p_smu.h:228
_SMU_PPUPATD0_GPCRC_SHIFT
#define _SMU_PPUPATD0_GPCRC_SHIFT
Definition: efr32mg12p_smu.h:173
SMU_Init_TypeDef::access
SMU_PrivilegedAccess_TypeDef access
Definition: em_smu.h:278
smuPeripheralPCNT2
Definition: em_smu.h:106
smuPeripheralI2C1
Definition: em_smu.h:97
smuPeripheralACMP0
Definition: em_smu.h:82
_SMU_PPUPATD1_USART3_SHIFT
#define _SMU_PPUPATD1_USART3_SHIFT
Definition: efr32mg12p_smu.h:287
_SMU_PPUPATD1_WTIMER1_SHIFT
#define _SMU_PPUPATD1_WTIMER1_SHIFT
Definition: efr32mg12p_smu.h:307
smuPeripheralWDOG0
Definition: em_smu.h:117
_SMU_PPUPATD0_ACMP0_SHIFT
#define _SMU_PPUPATD0_ACMP0_SHIFT
Definition: efr32mg12p_smu.h:113
_SMU_PPUPATD1_USART2_SHIFT
#define _SMU_PPUPATD1_USART2_SHIFT
Definition: efr32mg12p_smu.h:282
smuPeripheralTIMER1
Definition: em_smu.h:111
SMU_IntClear
__STATIC_INLINE void SMU_IntClear(uint32_t flags)
Clear one or more pending SMU interrupts.
Definition: em_smu.h:373
smuPeripheralWTIMER1
Definition: em_smu.h:120
smuPeripheralLETIMER0
Definition: em_smu.h:102
smuPeripheralUSART1
Definition: em_smu.h:114
BUS_RegBitWrite
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148
smuPeripheralCMU
Definition: em_smu.h:85
smuPeripheralACMP1
Definition: em_smu.h:83
smuPeripheralCRYPTO0
Definition: em_smu.h:87
_SMU_PPUCTRL_ENABLE_SHIFT
#define _SMU_PPUCTRL_ENABLE_SHIFT
Definition: efr32mg12p_smu.h:104
_SMU_PPUPATD0_IDAC0_SHIFT
#define _SMU_PPUPATD0_IDAC0_SHIFT
Definition: efr32mg12p_smu.h:193
SMU_Init_TypeDef
Definition: em_smu.h:275
smuPeripheralFPUEH
Definition: em_smu.h:93
_SMU_PPUPATD0_PCNT0_SHIFT
#define _SMU_PPUPATD0_PCNT0_SHIFT
Definition: efr32mg12p_smu.h:223
_SMU_PPUPATD0_LETIMER0_SHIFT
#define _SMU_PPUPATD0_LETIMER0_SHIFT
Definition: efr32mg12p_smu.h:213