Detailed Description

EFR32MG12P_EMU register and bit field definitions.

Version: 5.1.2

License

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Definition in file efr32mg12p_emu.h.

Go to the source code of this file.

Data Structures
struct	EMU_TypeDef

Macros
#define	_EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL

#define	_EMU_CMD_EM01VSCALE0_MASK 0x10UL

#define	_EMU_CMD_EM01VSCALE0_SHIFT 4

#define	_EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL

#define	_EMU_CMD_EM01VSCALE2_MASK 0x40UL

#define	_EMU_CMD_EM01VSCALE2_SHIFT 6

#define	_EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL

#define	_EMU_CMD_EM4UNLATCH_MASK 0x1UL

#define	_EMU_CMD_EM4UNLATCH_SHIFT 0

#define	_EMU_CMD_MASK 0x00000051UL

#define	_EMU_CMD_RESETVALUE 0x00000000UL

#define	_EMU_CTRL_EM01LD_DEFAULT 0x00000000UL

#define	_EMU_CTRL_EM01LD_MASK 0x8UL

#define	_EMU_CTRL_EM01LD_SHIFT 3

#define	_EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL

#define	_EMU_CTRL_EM23VSCALE_MASK 0x300UL

#define	_EMU_CTRL_EM23VSCALE_RESV 0x00000003UL

#define	_EMU_CTRL_EM23VSCALE_SHIFT 8

#define	_EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL

#define	_EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL

#define	_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL

#define	_EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL

#define	_EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4

#define	_EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL

#define	_EMU_CTRL_EM2BLOCK_MASK 0x2UL

#define	_EMU_CTRL_EM2BLOCK_SHIFT 1

#define	_EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL

#define	_EMU_CTRL_EM2BODDIS_MASK 0x4UL

#define	_EMU_CTRL_EM2BODDIS_SHIFT 2

#define	_EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL

#define	_EMU_CTRL_EM4HVSCALE_MASK 0x30000UL

#define	_EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL

#define	_EMU_CTRL_EM4HVSCALE_SHIFT 16

#define	_EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL

#define	_EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL

#define	_EMU_CTRL_MASK 0x0003031EUL

#define	_EMU_CTRL_RESETVALUE 0x00000000UL

#define	_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL

#define	_EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL

#define	_EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13

#define	_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL

#define	_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL

#define	_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8

#define	_EMU_DCDCCLIMCTRL_MASK 0x00002300UL

#define	_EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL

#define	_EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL

#define	_EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL

#define	_EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL

#define	_EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL

#define	_EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL

#define	_EMU_DCDCCTRL_DCDCMODE_SHIFT 0

#define	_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL

#define	_EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL

#define	_EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4

#define	_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL

#define	_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL

#define	_EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL

#define	_EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5

#define	_EMU_DCDCCTRL_MASK 0x00000033UL

#define	_EMU_DCDCCTRL_RESETVALUE 0x00000033UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20

#define	_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24

#define	_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28

#define	_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0

#define	_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4

#define	_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL

#define	_EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12

#define	_EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL

#define	_EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL

#define	_EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL

#define	_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL

#define	_EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL

#define	_EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0

#define	_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL

#define	_EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL

#define	_EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24

#define	_EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL

#define	_EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL

#define	_EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL

#define	_EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL

#define	_EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL

#define	_EMU_DCDCLNVCTRL_LNATT_SHIFT 1

#define	_EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL

#define	_EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL

#define	_EMU_DCDCLNVCTRL_LNVREF_SHIFT 8

#define	_EMU_DCDCLNVCTRL_MASK 0x00007F02UL

#define	_EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL

#define	_EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL

#define	_EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL

#define	_EMU_DCDCLPCTRL_LPBLANK_SHIFT 25

#define	_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL

#define	_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL

#define	_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12

#define	_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL

#define	_EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL

#define	_EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24

#define	_EMU_DCDCLPCTRL_MASK 0x0700F000UL

#define	_EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL

#define	_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL

#define	_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL

#define	_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL

#define	_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL

#define	_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL

#define	_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL

#define	_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8

#define	_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL

#define	_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL

#define	_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12

#define	_EMU_DCDCLPEM01CFG_MASK 0x0000F300UL

#define	_EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL

#define	_EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL

#define	_EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL

#define	_EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL

#define	_EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL

#define	_EMU_DCDCLPVCTRL_LPATT_SHIFT 0

#define	_EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL

#define	_EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL

#define	_EMU_DCDCLPVCTRL_LPVREF_SHIFT 1

#define	_EMU_DCDCLPVCTRL_MASK 0x000001FFUL

#define	_EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL

#define	_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL

#define	_EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL

#define	_EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16

#define	_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL

#define	_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL

#define	_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24

#define	_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL

#define	_EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL

#define	_EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0

#define	_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL

#define	_EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL

#define	_EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5

#define	_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL

#define	_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL

#define	_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20

#define	_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL

#define	_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28

#define	_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL

#define	_EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL

#define	_EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1

#define	_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL

#define	_EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL

#define	_EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2

#define	_EMU_DCDCMISCCTRL_MASK 0x377FFF27UL

#define	_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL

#define	_EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL

#define	_EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12

#define	_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL

#define	_EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL

#define	_EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8

#define	_EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL

#define	_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL

#define	_EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL

#define	_EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0

#define	_EMU_DCDCSYNC_MASK 0x00000001UL

#define	_EMU_DCDCSYNC_RESETVALUE 0x00000000UL

#define	_EMU_DCDCZDETCTRL_MASK 0x00000370UL

#define	_EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL

#define	_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL

#define	_EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL

#define	_EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8

#define	_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL

#define	_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL

#define	_EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4

#define	_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL

#define	_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0

#define	_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL

#define	_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1

#define	_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL

#define	_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9

#define	_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL

#define	_EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14

#define	_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL

#define	_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7

#define	_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL

#define	_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5

#define	_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL

#define	_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6

#define	_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL

#define	_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8

#define	_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL

#define	_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13

#define	_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL

#define	_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10

#define	_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL

#define	_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15

#define	_EMU_EM23PERNORETAINCMD_MASK 0x0000FFFFUL

#define	_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL

#define	_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2

#define	_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL

#define	_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3

#define	_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL

#define	_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4

#define	_EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL

#define	_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11

#define	_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL

#define	_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12

#define	_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL

#define	_EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0

#define	_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL

#define	_EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1

#define	_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL

#define	_EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9

#define	_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL

#define	_EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14

#define	_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL

#define	_EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7

#define	_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL

#define	_EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5

#define	_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL

#define	_EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6

#define	_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL

#define	_EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8

#define	_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL

#define	_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13

#define	_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL

#define	_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10

#define	_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL

#define	_EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15

#define	_EMU_EM23PERNORETAINCTRL_MASK 0x0000FFFFUL

#define	_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL

#define	_EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2

#define	_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL

#define	_EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3

#define	_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL

#define	_EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4

#define	_EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL

#define	_EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11

#define	_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL

#define	_EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12

#define	_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL

#define	_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0

#define	_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL

#define	_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1

#define	_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL

#define	_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9

#define	_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL

#define	_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14

#define	_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL

#define	_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7

#define	_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL

#define	_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5

#define	_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL

#define	_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6

#define	_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL

#define	_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8

#define	_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL

#define	_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13

#define	_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL

#define	_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10

#define	_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL

#define	_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15

#define	_EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFFFUL

#define	_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL

#define	_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2

#define	_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL

#define	_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3

#define	_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL

#define	_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4

#define	_EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL

#define	_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11

#define	_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL

#define	_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL

#define	_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12

#define	_EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL

#define	_EMU_EM4CTRL_EM4ENTRY_SHIFT 16

#define	_EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL

#define	_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL

#define	_EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL

#define	_EMU_EM4CTRL_EM4IORETMODE_SHIFT 4

#define	_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL

#define	_EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL

#define	_EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL

#define	_EMU_EM4CTRL_EM4STATE_MASK 0x1UL

#define	_EMU_EM4CTRL_EM4STATE_SHIFT 0

#define	_EMU_EM4CTRL_MASK 0x0003003FUL

#define	_EMU_EM4CTRL_RESETVALUE 0x00000000UL

#define	_EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL

#define	_EMU_EM4CTRL_RETAINLFRCO_SHIFT 1

#define	_EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL

#define	_EMU_EM4CTRL_RETAINLFXO_SHIFT 2

#define	_EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL

#define	_EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL

#define	_EMU_EM4CTRL_RETAINULFRCO_SHIFT 3

#define	_EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL

#define	_EMU_IEN_DCDCINBYPASS_MASK 0x100000UL

#define	_EMU_IEN_DCDCINBYPASS_SHIFT 20

#define	_EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL

#define	_EMU_IEN_DCDCLNRUNNING_SHIFT 19

#define	_EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL

#define	_EMU_IEN_DCDCLPRUNNING_SHIFT 18

#define	_EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IEN_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IEN_EM23WAKEUP_SHIFT 24

#define	_EMU_IEN_MASK 0xE31FC0FFUL

#define	_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL

#define	_EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17

#define	_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL

#define	_EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16

#define	_EMU_IEN_RESETVALUE 0x00000000UL

#define	_EMU_IEN_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IEN_TEMP_MASK 0x20000000UL

#define	_EMU_IEN_TEMP_SHIFT 29

#define	_EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IEN_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IEN_TEMPHIGH_SHIFT 31

#define	_EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IEN_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IEN_TEMPLOW_SHIFT 30

#define	_EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL

#define	_EMU_IEN_VMONALTAVDDFALL_SHIFT 2

#define	_EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL

#define	_EMU_IEN_VMONALTAVDDRISE_SHIFT 3

#define	_EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONAVDDFALL_MASK 0x1UL

#define	_EMU_IEN_VMONAVDDFALL_SHIFT 0

#define	_EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONAVDDRISE_MASK 0x2UL

#define	_EMU_IEN_VMONAVDDRISE_SHIFT 1

#define	_EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONDVDDFALL_MASK 0x10UL

#define	_EMU_IEN_VMONDVDDFALL_SHIFT 4

#define	_EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONDVDDRISE_MASK 0x20UL

#define	_EMU_IEN_VMONDVDDRISE_SHIFT 5

#define	_EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONFVDDFALL_MASK 0x4000UL

#define	_EMU_IEN_VMONFVDDFALL_SHIFT 14

#define	_EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONFVDDRISE_MASK 0x8000UL

#define	_EMU_IEN_VMONFVDDRISE_SHIFT 15

#define	_EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONIO0FALL_MASK 0x40UL

#define	_EMU_IEN_VMONIO0FALL_SHIFT 6

#define	_EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VMONIO0RISE_MASK 0x80UL

#define	_EMU_IEN_VMONIO0RISE_SHIFT 7

#define	_EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL

#define	_EMU_IEN_VSCALEDONE_MASK 0x2000000UL

#define	_EMU_IEN_VSCALEDONE_SHIFT 25

#define	_EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL

#define	_EMU_IF_DCDCINBYPASS_MASK 0x100000UL

#define	_EMU_IF_DCDCINBYPASS_SHIFT 20

#define	_EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IF_DCDCLNRUNNING_MASK 0x80000UL

#define	_EMU_IF_DCDCLNRUNNING_SHIFT 19

#define	_EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IF_DCDCLPRUNNING_MASK 0x40000UL

#define	_EMU_IF_DCDCLPRUNNING_SHIFT 18

#define	_EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IF_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IF_EM23WAKEUP_SHIFT 24

#define	_EMU_IF_MASK 0xE31FC0FFUL

#define	_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL

#define	_EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17

#define	_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL

#define	_EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16

#define	_EMU_IF_RESETVALUE 0x00000000UL

#define	_EMU_IF_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IF_TEMP_MASK 0x20000000UL

#define	_EMU_IF_TEMP_SHIFT 29

#define	_EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IF_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IF_TEMPHIGH_SHIFT 31

#define	_EMU_IF_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IF_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IF_TEMPLOW_SHIFT 30

#define	_EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONALTAVDDFALL_MASK 0x4UL

#define	_EMU_IF_VMONALTAVDDFALL_SHIFT 2

#define	_EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONALTAVDDRISE_MASK 0x8UL

#define	_EMU_IF_VMONALTAVDDRISE_SHIFT 3

#define	_EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONAVDDFALL_MASK 0x1UL

#define	_EMU_IF_VMONAVDDFALL_SHIFT 0

#define	_EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONAVDDRISE_MASK 0x2UL

#define	_EMU_IF_VMONAVDDRISE_SHIFT 1

#define	_EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONDVDDFALL_MASK 0x10UL

#define	_EMU_IF_VMONDVDDFALL_SHIFT 4

#define	_EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONDVDDRISE_MASK 0x20UL

#define	_EMU_IF_VMONDVDDRISE_SHIFT 5

#define	_EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONFVDDFALL_MASK 0x4000UL

#define	_EMU_IF_VMONFVDDFALL_SHIFT 14

#define	_EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONFVDDRISE_MASK 0x8000UL

#define	_EMU_IF_VMONFVDDRISE_SHIFT 15

#define	_EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONIO0FALL_MASK 0x40UL

#define	_EMU_IF_VMONIO0FALL_SHIFT 6

#define	_EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL

#define	_EMU_IF_VMONIO0RISE_MASK 0x80UL

#define	_EMU_IF_VMONIO0RISE_SHIFT 7

#define	_EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL

#define	_EMU_IF_VSCALEDONE_MASK 0x2000000UL

#define	_EMU_IF_VSCALEDONE_SHIFT 25

#define	_EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL

#define	_EMU_IFC_DCDCINBYPASS_MASK 0x100000UL

#define	_EMU_IFC_DCDCINBYPASS_SHIFT 20

#define	_EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL

#define	_EMU_IFC_DCDCLNRUNNING_SHIFT 19

#define	_EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL

#define	_EMU_IFC_DCDCLPRUNNING_SHIFT 18

#define	_EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IFC_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IFC_EM23WAKEUP_SHIFT 24

#define	_EMU_IFC_MASK 0xE31FC0FFUL

#define	_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL

#define	_EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17

#define	_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL

#define	_EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16

#define	_EMU_IFC_RESETVALUE 0x00000000UL

#define	_EMU_IFC_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IFC_TEMP_MASK 0x20000000UL

#define	_EMU_IFC_TEMP_SHIFT 29

#define	_EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IFC_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IFC_TEMPHIGH_SHIFT 31

#define	_EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IFC_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IFC_TEMPLOW_SHIFT 30

#define	_EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL

#define	_EMU_IFC_VMONALTAVDDFALL_SHIFT 2

#define	_EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL

#define	_EMU_IFC_VMONALTAVDDRISE_SHIFT 3

#define	_EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONAVDDFALL_MASK 0x1UL

#define	_EMU_IFC_VMONAVDDFALL_SHIFT 0

#define	_EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONAVDDRISE_MASK 0x2UL

#define	_EMU_IFC_VMONAVDDRISE_SHIFT 1

#define	_EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONDVDDFALL_MASK 0x10UL

#define	_EMU_IFC_VMONDVDDFALL_SHIFT 4

#define	_EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONDVDDRISE_MASK 0x20UL

#define	_EMU_IFC_VMONDVDDRISE_SHIFT 5

#define	_EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONFVDDFALL_MASK 0x4000UL

#define	_EMU_IFC_VMONFVDDFALL_SHIFT 14

#define	_EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONFVDDRISE_MASK 0x8000UL

#define	_EMU_IFC_VMONFVDDRISE_SHIFT 15

#define	_EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONIO0FALL_MASK 0x40UL

#define	_EMU_IFC_VMONIO0FALL_SHIFT 6

#define	_EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VMONIO0RISE_MASK 0x80UL

#define	_EMU_IFC_VMONIO0RISE_SHIFT 7

#define	_EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL

#define	_EMU_IFC_VSCALEDONE_MASK 0x2000000UL

#define	_EMU_IFC_VSCALEDONE_SHIFT 25

#define	_EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL

#define	_EMU_IFS_DCDCINBYPASS_MASK 0x100000UL

#define	_EMU_IFS_DCDCINBYPASS_SHIFT 20

#define	_EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL

#define	_EMU_IFS_DCDCLNRUNNING_SHIFT 19

#define	_EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL

#define	_EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL

#define	_EMU_IFS_DCDCLPRUNNING_SHIFT 18

#define	_EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL

#define	_EMU_IFS_EM23WAKEUP_MASK 0x1000000UL

#define	_EMU_IFS_EM23WAKEUP_SHIFT 24

#define	_EMU_IFS_MASK 0xE31FC0FFUL

#define	_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL

#define	_EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17

#define	_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL

#define	_EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL

#define	_EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16

#define	_EMU_IFS_RESETVALUE 0x00000000UL

#define	_EMU_IFS_TEMP_DEFAULT 0x00000000UL

#define	_EMU_IFS_TEMP_MASK 0x20000000UL

#define	_EMU_IFS_TEMP_SHIFT 29

#define	_EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL

#define	_EMU_IFS_TEMPHIGH_MASK 0x80000000UL

#define	_EMU_IFS_TEMPHIGH_SHIFT 31

#define	_EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_IFS_TEMPLOW_MASK 0x40000000UL

#define	_EMU_IFS_TEMPLOW_SHIFT 30

#define	_EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL

#define	_EMU_IFS_VMONALTAVDDFALL_SHIFT 2

#define	_EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL

#define	_EMU_IFS_VMONALTAVDDRISE_SHIFT 3

#define	_EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONAVDDFALL_MASK 0x1UL

#define	_EMU_IFS_VMONAVDDFALL_SHIFT 0

#define	_EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONAVDDRISE_MASK 0x2UL

#define	_EMU_IFS_VMONAVDDRISE_SHIFT 1

#define	_EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONDVDDFALL_MASK 0x10UL

#define	_EMU_IFS_VMONDVDDFALL_SHIFT 4

#define	_EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONDVDDRISE_MASK 0x20UL

#define	_EMU_IFS_VMONDVDDRISE_SHIFT 5

#define	_EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONFVDDFALL_MASK 0x4000UL

#define	_EMU_IFS_VMONFVDDFALL_SHIFT 14

#define	_EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONFVDDRISE_MASK 0x8000UL

#define	_EMU_IFS_VMONFVDDRISE_SHIFT 15

#define	_EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONIO0FALL_MASK 0x40UL

#define	_EMU_IFS_VMONIO0FALL_SHIFT 6

#define	_EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VMONIO0RISE_MASK 0x80UL

#define	_EMU_IFS_VMONIO0RISE_SHIFT 7

#define	_EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL

#define	_EMU_IFS_VSCALEDONE_MASK 0x2000000UL

#define	_EMU_IFS_VSCALEDONE_SHIFT 25

#define	_EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL

#define	_EMU_LOCK_LOCKKEY_LOCK 0x00000000UL

#define	_EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL

#define	_EMU_LOCK_LOCKKEY_MASK 0xFFFFUL

#define	_EMU_LOCK_LOCKKEY_SHIFT 0

#define	_EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL

#define	_EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL

#define	_EMU_LOCK_MASK 0x0000FFFFUL

#define	_EMU_LOCK_RESETVALUE 0x00000000UL

#define	_EMU_PWRCFG_MASK 0x0000000FUL

#define	_EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL

#define	_EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL

#define	_EMU_PWRCFG_PWRCFG_MASK 0xFUL

#define	_EMU_PWRCFG_PWRCFG_SHIFT 0

#define	_EMU_PWRCFG_PWRCFG_UNCONFIGURED 0x00000000UL

#define	_EMU_PWRCFG_RESETVALUE 0x00000000UL

#define	_EMU_PWRCTRL_ANASW_AVDD 0x00000000UL

#define	_EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL

#define	_EMU_PWRCTRL_ANASW_DVDD 0x00000001UL

#define	_EMU_PWRCTRL_ANASW_MASK 0x20UL

#define	_EMU_PWRCTRL_ANASW_SHIFT 5

#define	_EMU_PWRCTRL_DVDDBODDIS_DEFAULT 0x00000000UL

#define	_EMU_PWRCTRL_DVDDBODDIS_MASK 0x1000UL

#define	_EMU_PWRCTRL_DVDDBODDIS_SHIFT 12

#define	_EMU_PWRCTRL_MASK 0x00001420UL

#define	_EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL

#define	_EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL

#define	_EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL

#define	_EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL

#define	_EMU_PWRCTRL_REGPWRSEL_SHIFT 10

#define	_EMU_PWRCTRL_RESETVALUE 0x00000000UL

#define	_EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL

#define	_EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL

#define	_EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL

#define	_EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL

#define	_EMU_PWRLOCK_LOCKKEY_SHIFT 0

#define	_EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL

#define	_EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL

#define	_EMU_PWRLOCK_MASK 0x0000FFFFUL

#define	_EMU_PWRLOCK_RESETVALUE 0x00000000UL

#define	_EMU_RAM0CTRL_MASK 0x0000000FUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL

#define	_EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0

#define	_EMU_RAM0CTRL_RESETVALUE 0x00000000UL

#define	_EMU_RAM1CTRL_MASK 0x00000003UL

#define	_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 0x00000003UL

#define	_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 0x00000002UL

#define	_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL

#define	_EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0x3UL

#define	_EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL

#define	_EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0

#define	_EMU_RAM1CTRL_RESETVALUE 0x00000000UL

#define	_EMU_RAM2CTRL_MASK 0x00000001UL

#define	_EMU_RAM2CTRL_RAMPOWERDOWN_BLK 0x00000001UL

#define	_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL

#define	_EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0x1UL

#define	_EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL

#define	_EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0

#define	_EMU_RAM2CTRL_RESETVALUE 0x00000000UL

#define	_EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL

#define	_EMU_STATUS_EM4IORET_DISABLED 0x00000000UL

#define	_EMU_STATUS_EM4IORET_ENABLED 0x00000001UL

#define	_EMU_STATUS_EM4IORET_MASK 0x100000UL

#define	_EMU_STATUS_EM4IORET_SHIFT 20

#define	_EMU_STATUS_MASK 0x0417011FUL

#define	_EMU_STATUS_RESETVALUE 0x00000000UL

#define	_EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL

#define	_EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL

#define	_EMU_STATUS_TEMPACTIVE_SHIFT 26

#define	_EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONALTAVDD_MASK 0x4UL

#define	_EMU_STATUS_VMONALTAVDD_SHIFT 2

#define	_EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONAVDD_MASK 0x2UL

#define	_EMU_STATUS_VMONAVDD_SHIFT 1

#define	_EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONDVDD_MASK 0x8UL

#define	_EMU_STATUS_VMONDVDD_SHIFT 3

#define	_EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONFVDD_MASK 0x100UL

#define	_EMU_STATUS_VMONFVDD_SHIFT 8

#define	_EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONIO0_MASK 0x10UL

#define	_EMU_STATUS_VMONIO0_SHIFT 4

#define	_EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VMONRDY_MASK 0x1UL

#define	_EMU_STATUS_VMONRDY_SHIFT 0

#define	_EMU_STATUS_VSCALE_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VSCALE_MASK 0x30000UL

#define	_EMU_STATUS_VSCALE_RESV 0x00000003UL

#define	_EMU_STATUS_VSCALE_SHIFT 16

#define	_EMU_STATUS_VSCALE_VSCALE0 0x00000002UL

#define	_EMU_STATUS_VSCALE_VSCALE2 0x00000000UL

#define	_EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL

#define	_EMU_STATUS_VSCALEBUSY_MASK 0x40000UL

#define	_EMU_STATUS_VSCALEBUSY_SHIFT 18

#define	_EMU_TEMP_MASK 0x000000FFUL

#define	_EMU_TEMP_RESETVALUE 0x00000000UL

#define	_EMU_TEMP_TEMP_DEFAULT 0x00000000UL

#define	_EMU_TEMP_TEMP_MASK 0xFFUL

#define	_EMU_TEMP_TEMP_SHIFT 0

#define	_EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL

#define	_EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL

#define	_EMU_TEMPLIMITS_EM4WUEN_SHIFT 16

#define	_EMU_TEMPLIMITS_MASK 0x0001FFFFUL

#define	_EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL

#define	_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL

#define	_EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL

#define	_EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8

#define	_EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL

#define	_EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL

#define	_EMU_TEMPLIMITS_TEMPLOW_SHIFT 0

#define	_EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL

#define	_EMU_VMONALTAVDDCTRL_EN_SHIFT 0

#define	_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL

#define	_EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3

#define	_EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL

#define	_EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL

#define	_EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2

#define	_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL

#define	_EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12

#define	_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL

#define	_EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8

#define	_EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_EN_MASK 0x1UL

#define	_EMU_VMONAVDDCTRL_EN_SHIFT 0

#define	_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL

#define	_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12

#define	_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL

#define	_EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8

#define	_EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL

#define	_EMU_VMONAVDDCTRL_FALLWU_SHIFT 3

#define	_EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL

#define	_EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20

#define	_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL

#define	_EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16

#define	_EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL

#define	_EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL

#define	_EMU_VMONAVDDCTRL_RISEWU_SHIFT 2

#define	_EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_EN_MASK 0x1UL

#define	_EMU_VMONDVDDCTRL_EN_SHIFT 0

#define	_EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL

#define	_EMU_VMONDVDDCTRL_FALLWU_SHIFT 3

#define	_EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL

#define	_EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL

#define	_EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL

#define	_EMU_VMONDVDDCTRL_RISEWU_SHIFT 2

#define	_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL

#define	_EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12

#define	_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL

#define	_EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8

#define	_EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_EN_MASK 0x1UL

#define	_EMU_VMONIO0CTRL_EN_SHIFT 0

#define	_EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL

#define	_EMU_VMONIO0CTRL_FALLWU_SHIFT 3

#define	_EMU_VMONIO0CTRL_MASK 0x0000FF1DUL

#define	_EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL

#define	_EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL

#define	_EMU_VMONIO0CTRL_RETDIS_SHIFT 4

#define	_EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL

#define	_EMU_VMONIO0CTRL_RISEWU_SHIFT 2

#define	_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL

#define	_EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12

#define	_EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL

#define	_EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL

#define	_EMU_VMONIO0CTRL_THRESFINE_SHIFT 8

#define	EMU_CMD_EM01VSCALE0 (0x1UL << 4)

#define	EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4)

#define	EMU_CMD_EM01VSCALE2 (0x1UL << 6)

#define	EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6)

#define	EMU_CMD_EM4UNLATCH (0x1UL << 0)

#define	EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0)

#define	EMU_CTRL_EM01LD (0x1UL << 3)

#define	EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3)

#define	EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8)

#define	EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8)

#define	EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8)

#define	EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8)

#define	EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4)

#define	EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4)

#define	EMU_CTRL_EM2BLOCK (0x1UL << 1)

#define	EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)

#define	EMU_CTRL_EM2BODDIS (0x1UL << 2)

#define	EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2)

#define	EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16)

#define	EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16)

#define	EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16)

#define	EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16)

#define	EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13)

#define	EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13)

#define	EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8)

#define	EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0)

#define	EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0)

#define	EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0)

#define	EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0)

#define	EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0)

#define	EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4)

#define	EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4)

#define	EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4)

#define	EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4)

#define	EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5)

#define	EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5)

#define	EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5)

#define	EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5)

#define	EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20)

#define	EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24)

#define	EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28)

#define	EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0)

#define	EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4)

#define	EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12)

#define	EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0)

#define	EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24)

#define	EMU_DCDCLNVCTRL_LNATT (0x1UL << 1)

#define	EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1)

#define	EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1)

#define	EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1)

#define	EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8)

#define	EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25)

#define	EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12)

#define	EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24)

#define	EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24)

#define	EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8)

#define	EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8)

#define	EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8)

#define	EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8)

#define	EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8)

#define	EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12)

#define	EMU_DCDCLPVCTRL_LPATT (0x1UL << 0)

#define	EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0)

#define	EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0)

#define	EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0)

#define	EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1)

#define	EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16)

#define	EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24)

#define	EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0)

#define	EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0)

#define	EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5)

#define	EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5)

#define	EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20)

#define	EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28)

#define	EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28)

#define	EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28)

#define	EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28)

#define	EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28)

#define	EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1)

#define	EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1)

#define	EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2)

#define	EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2)

#define	EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12)

#define	EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8)

#define	EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0)

#define	EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0)

#define	EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8)

#define	EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4)

#define	EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0)

#define	EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0)

#define	EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1)

#define	EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1)

#define	EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9)

#define	EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9)

#define	EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14)

#define	EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14)

#define	EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7)

#define	EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7)

#define	EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5)

#define	EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5)

#define	EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6)

#define	EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6)

#define	EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8)

#define	EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8)

#define	EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13)

#define	EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13)

#define	EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10)

#define	EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10)

#define	EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15)

#define	EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15)

#define	EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2)

#define	EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2)

#define	EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3)

#define	EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3)

#define	EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4)

#define	EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4)

#define	EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11)

#define	EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11)

#define	EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12)

#define	EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12)

#define	EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0)

#define	EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0)

#define	EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1)

#define	EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1)

#define	EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9)

#define	EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9)

#define	EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14)

#define	EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14)

#define	EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7)

#define	EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7)

#define	EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5)

#define	EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5)

#define	EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6)

#define	EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6)

#define	EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8)

#define	EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8)

#define	EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13)

#define	EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13)

#define	EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10)

#define	EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10)

#define	EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15)

#define	EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15)

#define	EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2)

#define	EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2)

#define	EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3)

#define	EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3)

#define	EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4)

#define	EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4)

#define	EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11)

#define	EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11)

#define	EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12)

#define	EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12)

#define	EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0)

#define	EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0)

#define	EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1)

#define	EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1)

#define	EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9)

#define	EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9)

#define	EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14)

#define	EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14)

#define	EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7)

#define	EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7)

#define	EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5)

#define	EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5)

#define	EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6)

#define	EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6)

#define	EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8)

#define	EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8)

#define	EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13)

#define	EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13)

#define	EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10)

#define	EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10)

#define	EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15)

#define	EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15)

#define	EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2)

#define	EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2)

#define	EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3)

#define	EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3)

#define	EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4)

#define	EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4)

#define	EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11)

#define	EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11)

#define	EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12)

#define	EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12)

#define	EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16)

#define	EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)

#define	EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)

#define	EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)

#define	EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4)

#define	EMU_EM4CTRL_EM4STATE (0x1UL << 0)

#define	EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0)

#define	EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0)

#define	EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0)

#define	EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1)

#define	EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1)

#define	EMU_EM4CTRL_RETAINLFXO (0x1UL << 2)

#define	EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2)

#define	EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3)

#define	EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3)

#define	EMU_IEN_DCDCINBYPASS (0x1UL << 20)

#define	EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20)

#define	EMU_IEN_DCDCLNRUNNING (0x1UL << 19)

#define	EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19)

#define	EMU_IEN_DCDCLPRUNNING (0x1UL << 18)

#define	EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18)

#define	EMU_IEN_EM23WAKEUP (0x1UL << 24)

#define	EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17)

#define	EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17)

#define	EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16)

#define	EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16)

#define	EMU_IEN_TEMP (0x1UL << 29)

#define	EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29)

#define	EMU_IEN_TEMPHIGH (0x1UL << 31)

#define	EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31)

#define	EMU_IEN_TEMPLOW (0x1UL << 30)

#define	EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30)

#define	EMU_IEN_VMONALTAVDDFALL (0x1UL << 2)

#define	EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2)

#define	EMU_IEN_VMONALTAVDDRISE (0x1UL << 3)

#define	EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3)

#define	EMU_IEN_VMONAVDDFALL (0x1UL << 0)

#define	EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0)

#define	EMU_IEN_VMONAVDDRISE (0x1UL << 1)

#define	EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1)

#define	EMU_IEN_VMONDVDDFALL (0x1UL << 4)

#define	EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4)

#define	EMU_IEN_VMONDVDDRISE (0x1UL << 5)

#define	EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5)

#define	EMU_IEN_VMONFVDDFALL (0x1UL << 14)

#define	EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14)

#define	EMU_IEN_VMONFVDDRISE (0x1UL << 15)

#define	EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15)

#define	EMU_IEN_VMONIO0FALL (0x1UL << 6)

#define	EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6)

#define	EMU_IEN_VMONIO0RISE (0x1UL << 7)

#define	EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7)

#define	EMU_IEN_VSCALEDONE (0x1UL << 25)

#define	EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25)

#define	EMU_IF_DCDCINBYPASS (0x1UL << 20)

#define	EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20)

#define	EMU_IF_DCDCLNRUNNING (0x1UL << 19)

#define	EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19)

#define	EMU_IF_DCDCLPRUNNING (0x1UL << 18)

#define	EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18)

#define	EMU_IF_EM23WAKEUP (0x1UL << 24)

#define	EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17)

#define	EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17)

#define	EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16)

#define	EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16)

#define	EMU_IF_TEMP (0x1UL << 29)

#define	EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29)

#define	EMU_IF_TEMPHIGH (0x1UL << 31)

#define	EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31)

#define	EMU_IF_TEMPLOW (0x1UL << 30)

#define	EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30)

#define	EMU_IF_VMONALTAVDDFALL (0x1UL << 2)

#define	EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2)

#define	EMU_IF_VMONALTAVDDRISE (0x1UL << 3)

#define	EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3)

#define	EMU_IF_VMONAVDDFALL (0x1UL << 0)

#define	EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0)

#define	EMU_IF_VMONAVDDRISE (0x1UL << 1)

#define	EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1)

#define	EMU_IF_VMONDVDDFALL (0x1UL << 4)

#define	EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4)

#define	EMU_IF_VMONDVDDRISE (0x1UL << 5)

#define	EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5)

#define	EMU_IF_VMONFVDDFALL (0x1UL << 14)

#define	EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14)

#define	EMU_IF_VMONFVDDRISE (0x1UL << 15)

#define	EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15)

#define	EMU_IF_VMONIO0FALL (0x1UL << 6)

#define	EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6)

#define	EMU_IF_VMONIO0RISE (0x1UL << 7)

#define	EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7)

#define	EMU_IF_VSCALEDONE (0x1UL << 25)

#define	EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25)

#define	EMU_IFC_DCDCINBYPASS (0x1UL << 20)

#define	EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20)

#define	EMU_IFC_DCDCLNRUNNING (0x1UL << 19)

#define	EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19)

#define	EMU_IFC_DCDCLPRUNNING (0x1UL << 18)

#define	EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18)

#define	EMU_IFC_EM23WAKEUP (0x1UL << 24)

#define	EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17)

#define	EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17)

#define	EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16)

#define	EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16)

#define	EMU_IFC_TEMP (0x1UL << 29)

#define	EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29)

#define	EMU_IFC_TEMPHIGH (0x1UL << 31)

#define	EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31)

#define	EMU_IFC_TEMPLOW (0x1UL << 30)

#define	EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30)

#define	EMU_IFC_VMONALTAVDDFALL (0x1UL << 2)

#define	EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2)

#define	EMU_IFC_VMONALTAVDDRISE (0x1UL << 3)

#define	EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3)

#define	EMU_IFC_VMONAVDDFALL (0x1UL << 0)

#define	EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0)

#define	EMU_IFC_VMONAVDDRISE (0x1UL << 1)

#define	EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1)

#define	EMU_IFC_VMONDVDDFALL (0x1UL << 4)

#define	EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4)

#define	EMU_IFC_VMONDVDDRISE (0x1UL << 5)

#define	EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5)

#define	EMU_IFC_VMONFVDDFALL (0x1UL << 14)

#define	EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14)

#define	EMU_IFC_VMONFVDDRISE (0x1UL << 15)

#define	EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15)

#define	EMU_IFC_VMONIO0FALL (0x1UL << 6)

#define	EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6)

#define	EMU_IFC_VMONIO0RISE (0x1UL << 7)

#define	EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7)

#define	EMU_IFC_VSCALEDONE (0x1UL << 25)

#define	EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25)

#define	EMU_IFS_DCDCINBYPASS (0x1UL << 20)

#define	EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20)

#define	EMU_IFS_DCDCLNRUNNING (0x1UL << 19)

#define	EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19)

#define	EMU_IFS_DCDCLPRUNNING (0x1UL << 18)

#define	EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18)

#define	EMU_IFS_EM23WAKEUP (0x1UL << 24)

#define	EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24)

#define	EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17)

#define	EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17)

#define	EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16)

#define	EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16)

#define	EMU_IFS_TEMP (0x1UL << 29)

#define	EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29)

#define	EMU_IFS_TEMPHIGH (0x1UL << 31)

#define	EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31)

#define	EMU_IFS_TEMPLOW (0x1UL << 30)

#define	EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30)

#define	EMU_IFS_VMONALTAVDDFALL (0x1UL << 2)

#define	EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2)

#define	EMU_IFS_VMONALTAVDDRISE (0x1UL << 3)

#define	EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3)

#define	EMU_IFS_VMONAVDDFALL (0x1UL << 0)

#define	EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0)

#define	EMU_IFS_VMONAVDDRISE (0x1UL << 1)

#define	EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1)

#define	EMU_IFS_VMONDVDDFALL (0x1UL << 4)

#define	EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4)

#define	EMU_IFS_VMONDVDDRISE (0x1UL << 5)

#define	EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5)

#define	EMU_IFS_VMONFVDDFALL (0x1UL << 14)

#define	EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14)

#define	EMU_IFS_VMONFVDDRISE (0x1UL << 15)

#define	EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15)

#define	EMU_IFS_VMONIO0FALL (0x1UL << 6)

#define	EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6)

#define	EMU_IFS_VMONIO0RISE (0x1UL << 7)

#define	EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7)

#define	EMU_IFS_VSCALEDONE (0x1UL << 25)

#define	EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25)

#define	EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0)

#define	EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0)

#define	EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0)

#define	EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0)

#define	EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0)

#define	EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0)

#define	EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0)

#define	EMU_PWRCFG_PWRCFG_UNCONFIGURED (_EMU_PWRCFG_PWRCFG_UNCONFIGURED << 0)

#define	EMU_PWRCTRL_ANASW (0x1UL << 5)

#define	EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5)

#define	EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5)

#define	EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5)

#define	EMU_PWRCTRL_DVDDBODDIS (0x1UL << 12)

#define	EMU_PWRCTRL_DVDDBODDIS_DEFAULT (_EMU_PWRCTRL_DVDDBODDIS_DEFAULT << 12)

#define	EMU_PWRCTRL_REGPWRSEL (0x1UL << 10)

#define	EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10)

#define	EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10)

#define	EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10)

#define	EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0)

#define	EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0)

#define	EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0)

#define	EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0)

#define	EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0)

#define	EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0)

#define	EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 << 0)

#define	EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 << 0)

#define	EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0)

#define	EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0)

#define	EMU_RAM2CTRL_RAMPOWERDOWN_BLK (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0)

#define	EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0)

#define	EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0)

#define	EMU_STATUS_EM4IORET (0x1UL << 20)

#define	EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20)

#define	EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20)

#define	EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20)

#define	EMU_STATUS_TEMPACTIVE (0x1UL << 26)

#define	EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26)

#define	EMU_STATUS_VMONALTAVDD (0x1UL << 2)

#define	EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2)

#define	EMU_STATUS_VMONAVDD (0x1UL << 1)

#define	EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1)

#define	EMU_STATUS_VMONDVDD (0x1UL << 3)

#define	EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3)

#define	EMU_STATUS_VMONFVDD (0x1UL << 8)

#define	EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8)

#define	EMU_STATUS_VMONIO0 (0x1UL << 4)

#define	EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4)

#define	EMU_STATUS_VMONRDY (0x1UL << 0)

#define	EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0)

#define	EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16)

#define	EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16)

#define	EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16)

#define	EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16)

#define	EMU_STATUS_VSCALEBUSY (0x1UL << 18)

#define	EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18)

#define	EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0)

#define	EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16)

#define	EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16)

#define	EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8)

#define	EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0)

#define	EMU_VMONALTAVDDCTRL_EN (0x1UL << 0)

#define	EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0)

#define	EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3)

#define	EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3)

#define	EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2)

#define	EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2)

#define	EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12)

#define	EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8)

#define	EMU_VMONAVDDCTRL_EN (0x1UL << 0)

#define	EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0)

#define	EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12)

#define	EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8)

#define	EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3)

#define	EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3)

#define	EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20)

#define	EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16)

#define	EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2)

#define	EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2)

#define	EMU_VMONDVDDCTRL_EN (0x1UL << 0)

#define	EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0)

#define	EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3)

#define	EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3)

#define	EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2)

#define	EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2)

#define	EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12)

#define	EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8)

#define	EMU_VMONIO0CTRL_EN (0x1UL << 0)

#define	EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0)

#define	EMU_VMONIO0CTRL_FALLWU (0x1UL << 3)

#define	EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3)

#define	EMU_VMONIO0CTRL_RETDIS (0x1UL << 4)

#define	EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4)

#define	EMU_VMONIO0CTRL_RISEWU (0x1UL << 2)

#define	EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2)

#define	EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12)

#define	EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8)

Detailed Description

License

Data Structures

Macros