EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
mx25flash_spi.h
1 /*
2  * COPYRIGHT (c) 2010-2015 MACRONIX INTERNATIONAL CO., LTD
3  * SPI Flash Low Level Driver (LLD) Sample Code
4  *
5  * Flash device information define
6  *
7  * $Id: MX25_DEF.h,v 1.420 2015/04/09 03:26:05 mxclldb1 Exp $
8  */
9 
10 #ifndef __MX25_DEF_H__
11 #define __MX25_DEF_H__
12 
13 #include <stdbool.h>
14 #include <stdint.h>
15 #include "mx25flash_config.h"
16 
17 #define MX25R8035F
18 
19 /* Note:
20  Synchronous IO : MCU will polling WIP bit after
21  sending prgram/erase command
22  Non-synchronous IO : MCU can do other operation after
23  sending prgram/erase command
24  Default is synchronous IO
25 */
26 //#define NON_SYNCHRONOUS_IO
27 
28 // variable
29 #define TRUE 1
30 #define FALSE 0
31 #define BYTE_LEN 8
32 #define IO_MASK 0x80
33 #define HALF_WORD_MASK 0x0000ffff
34 
35 /*
36  Flash Related Parameter Define
37 */
38 
39 #define Block_Offset 0x10000 // 64K Block size
40 #define Block32K_Offset 0x8000 // 32K Block size
41 #define Sector_Offset 0x1000 // 4K Sector size
42 #define Page_Offset 0x0100 // 256 Byte Page size
43 #define Page32_Offset 0x0020 // 32 Byte Page size (some products have smaller page size)
44 #define Block_Num (FlashSize / Block_Offset)
45 
46 // Flash control register mask define
47 // status register
48 #define FLASH_WIP_MASK 0x01
49 #define FLASH_LDSO_MASK 0x02
50 #define FLASH_QE_MASK 0x40
51 // security register
52 #define FLASH_OTPLOCK_MASK 0x03
53 #define FLASH_4BYTE_MASK 0x04
54 #define FLASH_WPSEL_MASK 0x80
55 // configuration reigster
56 #define FLASH_DC_MASK 0x80
57 #define FLASH_DC_2BIT_MASK 0xC0
58 // other
59 #define BLOCK_PROTECT_MASK 0xff
60 #define BLOCK_LOCK_MASK 0x01
61 
62 /*
63  System Information Define
64 */
65 #define CLK_PERIOD 26 // unit: ns
66 #define Min_Cycle_Per_Inst 1 // cycle count of one instruction
67 #define One_Loop_Inst 10 // instruction count of one loop (estimate)
68 
69 /*
70  Flash ID, Timing Information Define
71  (The following information could get from device specification)
72 */
73 
74 #ifdef MX25R8035F
75 #define FlashID 0xc22814
76 #define ElectronicID 0x14
77 #define RESID0 0xc214
78 #define RESID1 0x14c2
79 #define FlashSize 0x100000 // 1 MB
80 #define CE_period 15625000 // tCE / ( CLK_PERIOD * Min_Cycle_Per_Inst *One_Loop_Inst)
81 #define tW 40000000 // 40ms
82 #define tDP 10000 // 10us
83 #define tBP 100000 // 100us
84 #define tPP 10000000 // 10ms
85 #define tSE 240000000 // 240ms
86 #define tBE32 1750000000 // 1.75s
87 #define tBE 3500000000 // 3.5s
88 #define tPUW 10000000 // 10ms
89 #define tWSR tBP
90 // Support I/O mode
91 #define SIO 0
92 #define DIO 1
93 #define QIO 2
94 #endif
95 
96 // dummy cycle configration
97 #ifdef DUMMY_CONF_2
98 
99 #define DUMMY_CONF_2READ 0x08040804
100 #define DUMMY_CONF_4READ 0x0A080406
101 #define DUMMY_CONF_FASTREAD 0x08080808
102 #define DUMMY_CONF_DREAD 0x08080808
103 #define DUMMY_CONF_QREAD 0x08080808
104 
105 #else
106 
107 #define DUMMY_CONF_2READ 0x0A080604
108 #define DUMMY_CONF_4READ 0x0A080406
109 #define DUMMY_CONF_FASTREAD 0x0A080608
110 #define DUMMY_CONF_DREAD 0x0A080608
111 #define DUMMY_CONF_QREAD 0x0A080608
112 
113 #endif
114 
115 // Flash information define
116 #define WriteStatusRegCycleTime tW / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst)
117 #define PageProgramCycleTime tPP / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst)
118 #define SectorEraseCycleTime tSE / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst)
119 #define BlockEraseCycleTime tBE / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst)
120 #define ChipEraseCycleTime CE_period
121 #define FlashFullAccessTime tPUW / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst)
122 
123 #ifdef tBP
124 #define ByteProgramCycleTime tBP / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst)
125 #endif
126 #ifdef tWSR
127 #define WriteSecuRegCycleTime tWSR / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst)
128 #endif
129 #ifdef tBE32
130 #define BlockErase32KCycleTime tBE32 / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst)
131 #endif
132 #ifdef tWREAW
133 #define WriteExtRegCycleTime tWREAW / (CLK_PERIOD * Min_Cycle_Per_Inst * One_Loop_Inst)
134 #endif
135 
136 /*** MX25 series command hex code definition ***/
137 //ID comands
138 #define FLASH_CMD_RDID 0x9F //RDID (Read Identification)
139 #define FLASH_CMD_RES 0xAB //RES (Read Electronic ID)
140 #define FLASH_CMD_REMS 0x90 //REMS (Read Electronic & Device ID)
141 
142 //Register comands
143 #define FLASH_CMD_WRSR 0x01 //WRSR (Write Status Register)
144 #define FLASH_CMD_RDSR 0x05 //RDSR (Read Status Register)
145 #define FLASH_CMD_WRSCUR 0x2F //WRSCUR (Write Security Register)
146 #define FLASH_CMD_RDSCUR 0x2B //RDSCUR (Read Security Register)
147 #define FLASH_CMD_RDCR 0x15 //RDCR (Read Configuration Register)
148 
149 //READ comands
150 #define FLASH_CMD_READ 0x03 //READ (1 x I/O)
151 #define FLASH_CMD_2READ 0xBB //2READ (2 x I/O)
152 #define FLASH_CMD_4READ 0xEB //4READ (4 x I/O)
153 #define FLASH_CMD_FASTREAD 0x0B //FAST READ (Fast read data)
154 #define FLASH_CMD_DREAD 0x3B //DREAD (1In/2 Out fast read)
155 #define FLASH_CMD_QREAD 0x6B //QREAD (1In/4 Out fast read)
156 #define FLASH_CMD_RDSFDP 0x5A //RDSFDP (Read SFDP)
157 
158 //Program comands
159 #define FLASH_CMD_WREN 0x06 //WREN (Write Enable)
160 #define FLASH_CMD_WRDI 0x04 //WRDI (Write Disable)
161 #define FLASH_CMD_PP 0x02 //PP (page program)
162 #define FLASH_CMD_4PP 0x38 //4PP (Quad page program)
163 
164 //Erase comands
165 #define FLASH_CMD_SE 0x20 //SE (Sector Erase)
166 #define FLASH_CMD_BE32K 0x52 //BE32K (Block Erase 32kb)
167 #define FLASH_CMD_BE 0xD8 //BE (Block Erase)
168 #define FLASH_CMD_CE 0x60 //CE (Chip Erase) hex code: 60 or C7
169 
170 //Mode setting comands
171 #define FLASH_CMD_DP 0xB9 //DP (Deep Power Down)
172 #define FLASH_CMD_ENSO 0xB1 //ENSO (Enter Secured OTP)
173 #define FLASH_CMD_EXSO 0xC1 //EXSO (Exit Secured OTP)
174 #ifdef SBL_CMD_0x77
175 #define FLASH_CMD_SBL 0x77 //SBL (Set Burst Length) new: 0x77
176 #else
177 #define FLASH_CMD_SBL 0xC0 //SBL (Set Burst Length) Old: 0xC0
178 #endif
179 
180 //Reset comands
181 #define FLASH_CMD_RSTEN 0x66 //RSTEN (Reset Enable)
182 #define FLASH_CMD_RST 0x99 //RST (Reset Memory)
183 
184 //Security comands
185 #ifdef LCR_CMD_0xDD_0xD5
186 #else
187 #endif
188 
189 //Suspend/Resume comands
190 #define FLASH_CMD_PGM_ERS_S 0xB0 //PGM/ERS Suspend (Suspends Program/Erase)
191 #define FLASH_CMD_PGM_ERS_R 0x30 //PGM/ERS Erase (Resumes Program/Erase)
192 #define FLASH_CMD_NOP 0x00 //NOP (No Operation)
193 
194 // Return Message
195 typedef enum {
196  FlashOperationSuccess,
197  FlashWriteRegFailed,
198  FlashTimeOut,
199  FlashIsBusy,
200  FlashQuadNotEnable,
201  FlashAddressInvalid
202 }ReturnMsg;
203 
204 // Flash status structure define
205 struct sFlashStatus{
206  /* Mode Register:
207  * Bit Description
208  * -------------------------
209  * 7 RYBY enable
210  * 6 Reserved
211  * 5 Reserved
212  * 4 Reserved
213  * 3 Reserved
214  * 2 Reserved
215  * 1 Parallel mode enable
216  * 0 QPI mode enable
217  */
218  uint8_t ModeReg;
219  bool ArrangeOpt;
220 };
221 
222 typedef struct sFlashStatus FlashStatus;
223 
224 void MX25_init( void );
225 
226 /* Flash commands */
227 ReturnMsg MX25_RDID( uint32_t *Identification );
228 ReturnMsg MX25_RES( uint8_t *ElectricIdentification );
229 ReturnMsg MX25_REMS( uint16_t *REMS_Identification, FlashStatus *fsptr );
230 
231 ReturnMsg MX25_RDSR( uint8_t *StatusReg );
232 #ifdef SUPPORT_WRSR_CR
233  ReturnMsg MX25_WRSR( uint16_t UpdateValue );
234 #else
235  ReturnMsg MX25_WRSR( uint8_t UpdateValue );
236 #endif
237 ReturnMsg MX25_RDSCUR( uint8_t *SecurityReg );
238 ReturnMsg MX25_WRSCUR( void );
239 ReturnMsg MX25_RDCR( uint8_t *ConfigReg );
240 
241 ReturnMsg MX25_READ( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length );
242 ReturnMsg MX25_2READ( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length );
243 ReturnMsg MX25_4READ( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length );
244 ReturnMsg MX25_FASTREAD( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length );
245 ReturnMsg MX25_DREAD( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length );
246 ReturnMsg MX25_QREAD( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length );
247 ReturnMsg MX25_RDSFDP( uint32_t flash_address, uint8_t *target_address, uint32_t byte_length );
248 
249 ReturnMsg MX25_WREN( void );
250 ReturnMsg MX25_WRDI( void );
251 ReturnMsg MX25_PP( uint32_t flash_address, uint8_t *source_address, uint32_t byte_length );
252 ReturnMsg MX25_4PP( uint32_t flash_address, uint8_t *source_address, uint32_t byte_length );
253 
254 ReturnMsg MX25_SE( uint32_t flash_address );
255 ReturnMsg MX25_BE32K( uint32_t flash_address );
256 ReturnMsg MX25_BE( uint32_t flash_address );
257 ReturnMsg MX25_CE( void );
258 
259 ReturnMsg MX25_DP( void );
260 ReturnMsg MX25_ENSO( void );
261 ReturnMsg MX25_EXSO( void );
262 ReturnMsg MX25_SBL( uint8_t burstconfig );
263 
264 ReturnMsg MX25_RSTEN( void );
265 ReturnMsg MX25_RST( FlashStatus *fsptr );
266 
267 ReturnMsg MX25_PGM_ERS_S( void );
268 ReturnMsg MX25_PGM_ERS_R( void );
269 ReturnMsg MX25_NOP( void );
270 
271 
272 
273 
274 #endif /* end of __MX25_DEF_H__ */
275