bsp_dk_bcreg_3201.h

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/**************************************************************************/
#ifndef __BSP_DK_BCREG_3201_H
#define __BSP_DK_BCREG_3201_H

#include <stdint.h>

/***************************************************************************/
/***************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif

/**************************************************************************/
#define BC_REGISTER_BASE    0x80000000  
#define BC_SSD2119_BASE     0x84000000  
#define BC_PSRAM_BASE       0x88000000  
#define BC_FLASH_BASE       0x8C000000  
/**************************************************************************/
/* Define registers in a similar manner to CMSIS standards */

#define __IO    volatile

typedef struct
{
  __IO uint16_t RESERVERD0;        
  __IO uint16_t EM;                
  __IO uint16_t MAGIC;             
  __IO uint16_t UIF_LEDS;          
  __IO uint16_t UIF_PB;            
  __IO uint16_t UIF_DIP;           
  __IO uint16_t UIF_JOYSTICK;      
  __IO uint16_t UIF_AEM;           
  __IO uint16_t UIF_CTRL;          
  __IO uint16_t DISPLAY_CTRL;      
  __IO uint16_t EBI_CTRL;          
  __IO uint16_t ARB_CTRL;          
  __IO uint16_t PERICON;           
  __IO uint16_t SPI_DEMUX;         
  __IO uint16_t RESERVERD1[0x02];  
  __IO uint16_t ADC_WRITE;         
  __IO uint16_t ADC_STATUS;        
  __IO uint16_t ADC_READ;          
  __IO uint16_t CLKRST;            
  __IO uint16_t HW_VERSION;        
  __IO uint16_t FW_BUILDNO;        
  __IO uint16_t FW_VERSION;        
  __IO uint16_t SCRATCH_COMMON;    
  __IO uint16_t SCRATCH_EFM0;      
  __IO uint16_t SCRATCH_EFM1;      
  __IO uint16_t SCRATCH_EFM2;      
  __IO uint16_t SCRATCH_EFM3;      
  __IO uint16_t SCRATCH_BC0;       
  __IO uint16_t SCRATCH_BC1;       
  __IO uint16_t SCRATCH_BC2;       
  __IO uint16_t SCRATCH_BC3;       
  __IO uint16_t INTFLAG;           
  __IO uint16_t INTEN;             
  __IO uint16_t INTCLEAR;          
  __IO uint16_t INTSET;            
  __IO uint16_t INTPCTRL;          
  __IO uint16_t INTPLOW;           
  __IO uint16_t INTPHIGH;          
  __IO uint16_t RESERVERD3[0x19];  
  __IO uint16_t BC_MBOX_TXCTRL;    
  __IO uint16_t BC_MBOX_TXDATA;    
  __IO uint16_t BC_MBOX_TXSTATUS0; 
  __IO uint16_t BC_MBOX_TXSTATUS1; 
  __IO uint16_t RESERVED4[0x0d];   
  __IO uint16_t MBOX_TXCTRL;       
  __IO uint16_t MBOX_TXDATA;       
  __IO uint16_t MBOX_TXSTATUS0;    
  __IO uint16_t MBOX_TXSTATUS1;    
  __IO uint16_t RESERVED5[0x0b];   
  __IO uint16_t BUF_CTRL;          
} BC_TypeDef;

/* Cast into register structure */
#define BC_REGISTER                         ((BC_TypeDef *) BC_REGISTER_BASE) 
/* Energy Mode indicator */
#define BC_EM_EM0                           (0)  
#define BC_EM_EM1                           (1)  
#define BC_EM_EM2                           (2)  
#define BC_EM_EM3                           (3)  
#define BC_EM_EM4                           (4)  
/* Magic value */
#define BC_MAGIC_VALUE                      (0xef32)  
/* Push buttons, PB1-PB4 */
#define BC_UIF_PB_MASK                      (0x000f) 
#define BC_UIF_PB1                          (1 << 0) 
#define BC_UIF_PB2                          (1 << 1) 
#define BC_UIF_PB3                          (1 << 2) 
#define BC_UIF_PB4                          (1 << 3) 
/* Dip switch */
#define BC_DIPSWITCH_MASK                   (0x000f)  
/* Joystick directions */
#define BC_UIF_JOYSTICK_MASK                (0x001f)      
#define BC_UIF_JOYSTICK_DOWN                (1 << 0)      
#define BC_UIF_JOYSTICK_RIGHT               (1 << 1)      
#define BC_UIF_JOYSTICK_UP                  (1 << 2)      
#define BC_UIF_JOYSTICK_LEFT                (1 << 3)      
#define BC_UIF_JOYSTICK_CENTER              (1 << 4)      
/* AEM state */
#define BC_UIF_AEM_BC                       (0) 
#define BC_UIF_AEM_EFM                      (1) 
/* Display control */
#define BC_DISPLAY_CTRL_RESET               (1 << 1)                          
#define BC_DISPLAY_CTRL_POWER_ENABLE        (1 << 0)                          
#define BC_DISPLAY_CTRL_MODE_SHIFT          2                                 
#define BC_DISPLAY_CTRL_MODE_8080           (0 << BC_DISPLAY_CTRL_MODE_SHIFT) 
#define BC_DISPLAY_CTRL_MODE_GENERIC        (1 << BC_DISPLAY_CTRL_MODE_SHIFT) 
/* EBI control - extended address range enable bit  */
#define BC_EBI_CTRL_EXTADDR_MASK            (0x0001) 
/* Arbiter control - directs access to display controller  */
#define BC_ARB_CTRL_SHIFT                   0                        
#define BC_ARB_CTRL_BC                      (0 << BC_ARB_CTRL_SHIFT) 
#define BC_ARB_CTRL_EBI                     (1 << BC_ARB_CTRL_SHIFT) 
#define BC_ARB_CTRL_SPI                     (2 << BC_ARB_CTRL_SHIFT) 
/* Interrupt flag registers, INTEN and INTFLAG */
#define BC_INTEN_MASK                       (0x001f)  
#define BC_INTEN_PB                         (1 << 0)  
#define BC_INTEN_DIP                        (1 << 1)  
#define BC_INTEN_JOYSTICK                   (1 << 2)  
#define BC_INTEN_AEM                        (1 << 3)  
#define BC_INTEN_ETH                        (1 << 4)  
#define BC_INTFLAG_MASK                     (0x001f)  
#define BC_INTFLAG_PB                       (1 << 0)  
#define BC_INTFLAG_DIP                      (1 << 1)  
#define BC_INTFLAG_JOYSTICK                 (1 << 2)  
#define BC_INTFLAG_AEM                      (1 << 3)  
#define BC_INTFLAG_ETH                      (1 << 4)  
/* Peripheral control registers */
#define BC_PERICON_RS232_SHUTDOWN_SHIFT     13 
#define BC_PERICON_RS232_UART_SHIFT         12 
#define BC_PERICON_RS232_LEUART_SHIFT       11 
#define BC_PERICON_I2C_SHIFT                10 
#define BC_PERICON_I2S_ETH_SEL_SHIFT        9  
#define BC_PERICON_I2S_ETH_SHIFT            8  
#define BC_PERICON_TRACE_SHIFT              7  
#define BC_PERICON_TOUCH_SHIFT              6  
#define BC_PERICON_AUDIO_IN_SHIFT           5  
#define BC_PERICON_AUDIO_OUT_SEL_SHIFT      4  
#define BC_PERICON_AUDIO_OUT_SHIFT          3  
#define BC_PERICON_ANALOG_DIFF_SHIFT        2  
#define BC_PERICON_ANALOG_SE_SHIFT          1  
#define BC_PERICON_SPI_SHIFT                0  
/* SPI DEMUX control */
#define BC_SPI_DEMUX_SLAVE_MASK             (0x0003) 
#define BC_SPI_DEMUX_SLAVE_AUDIO            (0)      
#define BC_SPI_DEMUX_SLAVE_ETHERNET         (1)      
#define BC_SPI_DEMUX_SLAVE_DISPLAY          (2)      
/* ADC */
#define BC_ADC_STATUS_DONE                  (0)  
#define BC_ADC_STATUS_BUSY                  (1)  
/* Clock and Reset Control */
#define BC_CLKRST_FLASH_SHIFT               (1 << 1) 
#define BC_CLKRST_ETH_SHIFT                 (1 << 2) 
/* Hardware version information */
#define BC_HW_VERSION_PCB_MASK              (0x07f0)  
#define BC_HW_VERSION_PCB_SHIFT             (4)       
#define BC_HW_VERSION_BOARD_MASK            (0x000f)  
#define BC_HW_VERSION_BOARD_SHIFT           (0)       
/* Firmware version information */
#define BC_FW_VERSION_MAJOR_MASK            (0xf000) 
#define BC_FW_VERSION_MAJOR_SHIFT           (12)     
#define BC_FW_VERSION_MINOR_MASK            (0x0f00) 
#define BC_FW_VERSION_MINOR_SHIFT           (8)      
#define BC_FW_VERSION_PATCHLEVEL_MASK       (0x00ff) 
#define BC_FW_VERSION_PATCHLEVEL_SHIFT      (0)      
/* MBOX - BC <-> EFM32 communication */
#define BC_MBOX_TXSTATUS0_FIFOEMPTY         (1 << 0) 
#define BC_MBOX_TXSTATUS0_FIFOFULL          (1 << 1) 
#define BC_MBOX_TXSTATUS0_FIFOUNDERFLOW     (1 << 4) 
#define BC_MBOX_TXSTATUS0_FIFOOVERFLOW      (1 << 5) 
#define BC_MBOX_TXSTATUS1_WORDCOUNT_MASK    (0x07FF) 
/* Buffer Controller */
#define BC_BUF_CTRL_CS_ENABLE               (1 << 0) 
#ifdef __cplusplus
}
#endif

#endif  /* __BSP_DK_BCREG_3201_H */