EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
bsp_dk_bcreg_3201.h
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1 /**************************************************************************/
18 #ifndef __BSP_DK_BCREG_3201_H
19 #define __BSP_DK_BCREG_3201_H
20 
21 #include <stdint.h>
22 
23 /***************************************************************************/
28 /***************************************************************************/
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 /**************************************************************************/
41 #define BC_REGISTER_BASE 0x80000000
42 #define BC_SSD2119_BASE 0x84000000
43 #define BC_PSRAM_BASE 0x88000000
44 #define BC_FLASH_BASE 0x8C000000
47 /**************************************************************************/
51 /* Define registers in a similar manner to CMSIS standards */
52 
53 #define __IO volatile
54 
56 typedef struct
57 {
58  __IO uint16_t RESERVERD0;
59  __IO uint16_t EM;
60  __IO uint16_t MAGIC;
62  __IO uint16_t UIF_LEDS;
63  __IO uint16_t UIF_PB;
64  __IO uint16_t UIF_DIP;
65  __IO uint16_t UIF_JOYSTICK;
66  __IO uint16_t UIF_AEM;
67  __IO uint16_t UIF_CTRL;
68  __IO uint16_t DISPLAY_CTRL;
69  __IO uint16_t EBI_CTRL;
70  __IO uint16_t ARB_CTRL;
71  __IO uint16_t PERICON;
72  __IO uint16_t SPI_DEMUX;
73  __IO uint16_t RESERVERD1[0x02];
75  __IO uint16_t ADC_WRITE;
76  __IO uint16_t ADC_STATUS;
77  __IO uint16_t ADC_READ;
79  __IO uint16_t CLKRST;
81  __IO uint16_t HW_VERSION;
82  __IO uint16_t FW_BUILDNO;
83  __IO uint16_t FW_VERSION;
85  __IO uint16_t SCRATCH_COMMON;
87  __IO uint16_t SCRATCH_EFM0;
88  __IO uint16_t SCRATCH_EFM1;
89  __IO uint16_t SCRATCH_EFM2;
90  __IO uint16_t SCRATCH_EFM3;
92  __IO uint16_t SCRATCH_BC0;
93  __IO uint16_t SCRATCH_BC1;
94  __IO uint16_t SCRATCH_BC2;
95  __IO uint16_t SCRATCH_BC3;
97  __IO uint16_t INTFLAG;
98  __IO uint16_t INTEN;
99  __IO uint16_t INTCLEAR;
100  __IO uint16_t INTSET;
101  __IO uint16_t INTPCTRL;
102  __IO uint16_t INTPLOW;
103  __IO uint16_t INTPHIGH;
105  __IO uint16_t RESERVERD3[0x19];
107  __IO uint16_t BC_MBOX_TXCTRL;
108  __IO uint16_t BC_MBOX_TXDATA;
112  __IO uint16_t RESERVED4[0x0d];
114  __IO uint16_t MBOX_TXCTRL;
115  __IO uint16_t MBOX_TXDATA;
116  __IO uint16_t MBOX_TXSTATUS0;
117  __IO uint16_t MBOX_TXSTATUS1;
119  __IO uint16_t RESERVED5[0x0b];
121  __IO uint16_t BUF_CTRL;
122 } BC_TypeDef;
123 
124 /* Cast into register structure */
125 #define BC_REGISTER ((BC_TypeDef *) BC_REGISTER_BASE)
127 /* Energy Mode indicator */
128 #define BC_EM_EM0 (0)
129 #define BC_EM_EM1 (1)
130 #define BC_EM_EM2 (2)
131 #define BC_EM_EM3 (3)
132 #define BC_EM_EM4 (4)
134 /* Magic value */
135 #define BC_MAGIC_VALUE (0xef32)
137 /* Push buttons, PB1-PB4 */
138 #define BC_UIF_PB_MASK (0x000f)
139 #define BC_UIF_PB1 (1 << 0)
140 #define BC_UIF_PB2 (1 << 1)
141 #define BC_UIF_PB3 (1 << 2)
142 #define BC_UIF_PB4 (1 << 3)
144 /* Dip switch */
145 #define BC_DIPSWITCH_MASK (0x000f)
147 /* Joystick directions */
148 #define BC_UIF_JOYSTICK_MASK (0x001f)
149 #define BC_UIF_JOYSTICK_DOWN (1 << 0)
150 #define BC_UIF_JOYSTICK_RIGHT (1 << 1)
151 #define BC_UIF_JOYSTICK_UP (1 << 2)
152 #define BC_UIF_JOYSTICK_LEFT (1 << 3)
153 #define BC_UIF_JOYSTICK_CENTER (1 << 4)
155 /* AEM state */
156 #define BC_UIF_AEM_BC (0)
157 #define BC_UIF_AEM_EFM (1)
159 /* Display control */
160 #define BC_DISPLAY_CTRL_RESET (1 << 1)
161 #define BC_DISPLAY_CTRL_POWER_ENABLE (1 << 0)
162 #define BC_DISPLAY_CTRL_MODE_SHIFT 2
163 #define BC_DISPLAY_CTRL_MODE_8080 (0 << BC_DISPLAY_CTRL_MODE_SHIFT)
164 #define BC_DISPLAY_CTRL_MODE_GENERIC (1 << BC_DISPLAY_CTRL_MODE_SHIFT)
166 /* EBI control - extended address range enable bit */
167 #define BC_EBI_CTRL_EXTADDR_MASK (0x0001)
169 /* Arbiter control - directs access to display controller */
170 #define BC_ARB_CTRL_SHIFT 0
171 #define BC_ARB_CTRL_BC (0 << BC_ARB_CTRL_SHIFT)
172 #define BC_ARB_CTRL_EBI (1 << BC_ARB_CTRL_SHIFT)
173 #define BC_ARB_CTRL_SPI (2 << BC_ARB_CTRL_SHIFT)
175 /* Interrupt flag registers, INTEN and INTFLAG */
176 #define BC_INTEN_MASK (0x001f)
177 #define BC_INTEN_PB (1 << 0)
178 #define BC_INTEN_DIP (1 << 1)
179 #define BC_INTEN_JOYSTICK (1 << 2)
180 #define BC_INTEN_AEM (1 << 3)
181 #define BC_INTEN_ETH (1 << 4)
183 #define BC_INTFLAG_MASK (0x001f)
184 #define BC_INTFLAG_PB (1 << 0)
185 #define BC_INTFLAG_DIP (1 << 1)
186 #define BC_INTFLAG_JOYSTICK (1 << 2)
187 #define BC_INTFLAG_AEM (1 << 3)
188 #define BC_INTFLAG_ETH (1 << 4)
190 /* Peripheral control registers */
191 #define BC_PERICON_RS232_SHUTDOWN_SHIFT 13
192 #define BC_PERICON_RS232_UART_SHIFT 12
193 #define BC_PERICON_RS232_LEUART_SHIFT 11
194 #define BC_PERICON_I2C_SHIFT 10
195 #define BC_PERICON_I2S_ETH_SEL_SHIFT 9
196 #define BC_PERICON_I2S_ETH_SHIFT 8
197 #define BC_PERICON_TRACE_SHIFT 7
198 #define BC_PERICON_TOUCH_SHIFT 6
199 #define BC_PERICON_AUDIO_IN_SHIFT 5
200 #define BC_PERICON_AUDIO_OUT_SEL_SHIFT 4
201 #define BC_PERICON_AUDIO_OUT_SHIFT 3
202 #define BC_PERICON_ANALOG_DIFF_SHIFT 2
203 #define BC_PERICON_ANALOG_SE_SHIFT 1
204 #define BC_PERICON_SPI_SHIFT 0
206 /* SPI DEMUX control */
207 #define BC_SPI_DEMUX_SLAVE_MASK (0x0003)
208 #define BC_SPI_DEMUX_SLAVE_AUDIO (0)
209 #define BC_SPI_DEMUX_SLAVE_ETHERNET (1)
210 #define BC_SPI_DEMUX_SLAVE_DISPLAY (2)
212 /* ADC */
213 #define BC_ADC_STATUS_DONE (0)
214 #define BC_ADC_STATUS_BUSY (1)
216 /* Clock and Reset Control */
217 #define BC_CLKRST_FLASH_SHIFT (1 << 1)
218 #define BC_CLKRST_ETH_SHIFT (1 << 2)
220 /* Hardware version information */
221 #define BC_HW_VERSION_PCB_MASK (0x07f0)
222 #define BC_HW_VERSION_PCB_SHIFT (4)
223 #define BC_HW_VERSION_BOARD_MASK (0x000f)
224 #define BC_HW_VERSION_BOARD_SHIFT (0)
226 /* Firmware version information */
227 #define BC_FW_VERSION_MAJOR_MASK (0xf000)
228 #define BC_FW_VERSION_MAJOR_SHIFT (12)
229 #define BC_FW_VERSION_MINOR_MASK (0x0f00)
230 #define BC_FW_VERSION_MINOR_SHIFT (8)
231 #define BC_FW_VERSION_PATCHLEVEL_MASK (0x00ff)
232 #define BC_FW_VERSION_PATCHLEVEL_SHIFT (0)
234 /* MBOX - BC <-> EFM32 communication */
235 #define BC_MBOX_TXSTATUS0_FIFOEMPTY (1 << 0)
236 #define BC_MBOX_TXSTATUS0_FIFOFULL (1 << 1)
237 #define BC_MBOX_TXSTATUS0_FIFOUNDERFLOW (1 << 4)
238 #define BC_MBOX_TXSTATUS0_FIFOOVERFLOW (1 << 5)
240 #define BC_MBOX_TXSTATUS1_WORDCOUNT_MASK (0x07FF)
242 /* Buffer Controller */
243 #define BC_BUF_CTRL_CS_ENABLE (1 << 0)
245 #ifdef __cplusplus
246 }
247 #endif
248 
252 #endif /* __BSP_DK_BCREG_3201_H */
__IO uint16_t SCRATCH_BC0
#define __IO
__IO uint16_t INTPHIGH
__IO uint16_t INTEN
__IO uint16_t INTCLEAR
__IO uint16_t SCRATCH_COMMON
__IO uint16_t SCRATCH_BC1
__IO uint16_t EBI_CTRL
__IO uint16_t MBOX_TXSTATUS0
__IO uint16_t SCRATCH_EFM1
__IO uint16_t SCRATCH_BC2
__IO uint16_t UIF_DIP
__IO uint16_t UIF_CTRL
__IO uint16_t ADC_WRITE
__IO uint16_t UIF_PB
__IO uint16_t ADC_STATUS
__IO uint16_t HW_VERSION
__IO uint16_t SCRATCH_EFM3
__IO uint16_t MBOX_TXSTATUS1
__IO uint16_t BC_MBOX_TXCTRL
__IO uint16_t INTPCTRL
__IO uint16_t FW_BUILDNO
__IO uint16_t BC_MBOX_TXSTATUS1
__IO uint16_t BUF_CTRL
__IO uint16_t UIF_LEDS
__IO uint16_t SCRATCH_EFM0
__IO uint16_t MAGIC
__IO uint16_t RESERVERD0
__IO uint16_t INTSET
__IO uint16_t INTFLAG
__IO uint16_t MBOX_TXDATA
__IO uint16_t ADC_READ
__IO uint16_t UIF_JOYSTICK
__IO uint16_t MBOX_TXCTRL
__IO uint16_t SPI_DEMUX
__IO uint16_t PERICON
__IO uint16_t INTPLOW
__IO uint16_t CLKRST
__IO uint16_t DISPLAY_CTRL
__IO uint16_t ARB_CTRL
__IO uint16_t SCRATCH_EFM2
__IO uint16_t BC_MBOX_TXSTATUS0
__IO uint16_t UIF_AEM
__IO uint16_t BC_MBOX_TXDATA
__IO uint16_t EM
__IO uint16_t SCRATCH_BC3
__IO uint16_t FW_VERSION