em_csen.h

Go to the documentation of this file.

/***************************************************************************/
#ifndef EM_CSEN_H
#define EM_CSEN_H

#include "em_device.h"
#if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 )

#include <stdbool.h>
#include "em_bus.h"

#ifdef __cplusplus
extern "C" {
#endif

/***************************************************************************/
/***************************************************************************/
/*******************************************************************************
 ********************************   ENUMS   ************************************
 ******************************************************************************/

typedef enum
{
  csenCmpModeDisabled    = 0,

  csenCmpModeGreater     = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_GT,

  csenCmpModeLessOrEqual = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_LTE,

  csenCmpModeEMAWindow   = CSEN_CTRL_EMACMPEN,
} CSEN_CmpMode_TypeDef;


typedef enum
{
  csenConvSelSAR     = CSEN_CTRL_CONVSEL_SAR,

  csenConvSelSARChop = CSEN_CTRL_CONVSEL_SAR | CSEN_CTRL_CHOPEN_ENABLE,

  csenConvSelDM      = CSEN_CTRL_CONVSEL_DM,

  csenConvSelDMChop  = CSEN_CTRL_CONVSEL_DM | CSEN_CTRL_CHOPEN_ENABLE,
} CSEN_ConvSel_TypeDef;


typedef enum
{
  csenSampleModeBonded     = CSEN_CTRL_CM_SGL | CSEN_CTRL_MCEN_ENABLE,

  csenSampleModeSingle     = CSEN_CTRL_CM_SGL,

  csenSampleModeScan       = CSEN_CTRL_CM_SCAN,

  csenSampleModeContBonded = CSEN_CTRL_CM_CONTSGL | CSEN_CTRL_MCEN_ENABLE,

  csenSampleModeContSingle = CSEN_CTRL_CM_CONTSGL,

  csenSampleModeContScan   = CSEN_CTRL_CM_CONTSCAN,
} CSEN_SampleMode_TypeDef;


typedef enum
{
  csenTrigSelPRS   = _CSEN_CTRL_STM_PRS,   
  csenTrigSelTimer = _CSEN_CTRL_STM_TIMER, 
  csenTrigSelStart = _CSEN_CTRL_STM_START, 
} CSEN_TrigSel_TypeDef;


typedef enum
{
  csenAccMode1  = _CSEN_CTRL_ACU_ACC1,  
  csenAccMode2  = _CSEN_CTRL_ACU_ACC2,  
  csenAccMode4  = _CSEN_CTRL_ACU_ACC4,  
  csenAccMode8  = _CSEN_CTRL_ACU_ACC8,  
  csenAccMode16 = _CSEN_CTRL_ACU_ACC16, 
  csenAccMode32 = _CSEN_CTRL_ACU_ACC32, 
  csenAccMode64 = _CSEN_CTRL_ACU_ACC64, 
} CSEN_AccMode_TypeDef;


typedef enum
{
  csenSARRes10 = _CSEN_CTRL_SARCR_CLK10, 
  csenSARRes12 = _CSEN_CTRL_SARCR_CLK12, 
  csenSARRes14 = _CSEN_CTRL_SARCR_CLK14, 
  csenSARRes16 = _CSEN_CTRL_SARCR_CLK16, 
} CSEN_SARRes_TypeDef;


typedef enum
{
  csenDMRes10 = _CSEN_DMCFG_CRMODE_DM10, 
  csenDMRes12 = _CSEN_DMCFG_CRMODE_DM12, 
  csenDMRes14 = _CSEN_DMCFG_CRMODE_DM14, 
  csenDMRes16 = _CSEN_DMCFG_CRMODE_DM16, 
} CSEN_DMRes_TypeDef;


typedef enum
{
  csenPCPrescaleDiv1   = _CSEN_TIMCTRL_PCPRESC_DIV1,   
  csenPCPrescaleDiv2   = _CSEN_TIMCTRL_PCPRESC_DIV2,   
  csenPCPrescaleDiv4   = _CSEN_TIMCTRL_PCPRESC_DIV4,   
  csenPCPrescaleDiv8   = _CSEN_TIMCTRL_PCPRESC_DIV8,   
  csenPCPrescaleDiv16  = _CSEN_TIMCTRL_PCPRESC_DIV16,  
  csenPCPrescaleDiv32  = _CSEN_TIMCTRL_PCPRESC_DIV32,  
  csenPCPrescaleDiv64  = _CSEN_TIMCTRL_PCPRESC_DIV64,  
  csenPCPrescaleDiv128 = _CSEN_TIMCTRL_PCPRESC_DIV128, 
} CSEN_PCPrescale_TypeDef;


typedef enum
{
  csenEMASampleW1  = _CSEN_EMACTRL_EMASAMPLE_W1,  
  csenEMASampleW2  = _CSEN_EMACTRL_EMASAMPLE_W2,  
  csenEMASampleW4  = _CSEN_EMACTRL_EMASAMPLE_W4,  
  csenEMASampleW8  = _CSEN_EMACTRL_EMASAMPLE_W8,  
  csenEMASampleW16 = _CSEN_EMACTRL_EMASAMPLE_W16, 
  csenEMASampleW32 = _CSEN_EMACTRL_EMASAMPLE_W32, 
  csenEMASampleW64 = _CSEN_EMACTRL_EMASAMPLE_W64, 
} CSEN_EMASample_TypeDef;


typedef enum
{
  csenResetPhaseSel0 = 0,  
  csenResetPhaseSel1 = 1,  
  csenResetPhaseSel2 = 2,  
  csenResetPhaseSel3 = 3,  
  csenResetPhaseSel4 = 4,  
  csenResetPhaseSel5 = 5,  
  csenResetPhaseSel6 = 6,  
  csenResetPhaseSel7 = 7,  
} CSEN_ResetPhaseSel_TypeDef;


typedef enum
{
  csenDriveSelFull = 0,  
  csenDriveSel1 = 1,     
  csenDriveSel2 = 2,     
  csenDriveSel3 = 3,     
  csenDriveSel4 = 4,     
  csenDriveSel5 = 5,     
  csenDriveSel6 = 6,     
  csenDriveSel7 = 7,     
} CSEN_DriveSel_TypeDef;


typedef enum
{
  csenGainSel1X = 0,  
  csenGainSel2X = 1,  
  csenGainSel3X = 2,  
  csenGainSel4X = 3,  
  csenGainSel5X = 4,  
  csenGainSel6X = 5,  
  csenGainSel7X = 6,  
  csenGainSel8X = 7,  
} CSEN_GainSel_TypeDef;


typedef enum
{
  csenPRSSELCh0  = _CSEN_PRSSEL_PRSSEL_PRSCH0,  
  csenPRSSELCh1  = _CSEN_PRSSEL_PRSSEL_PRSCH1,  
  csenPRSSELCh2  = _CSEN_PRSSEL_PRSSEL_PRSCH2,  
  csenPRSSELCh3  = _CSEN_PRSSEL_PRSSEL_PRSCH3,  
  csenPRSSELCh4  = _CSEN_PRSSEL_PRSSEL_PRSCH4,  
  csenPRSSELCh5  = _CSEN_PRSSEL_PRSSEL_PRSCH5,  
  csenPRSSELCh6  = _CSEN_PRSSEL_PRSSEL_PRSCH6,  
  csenPRSSELCh7  = _CSEN_PRSSEL_PRSSEL_PRSCH7,  
  csenPRSSELCh8  = _CSEN_PRSSEL_PRSSEL_PRSCH8,  
  csenPRSSELCh9  = _CSEN_PRSSEL_PRSSEL_PRSCH9,  
  csenPRSSELCh10 = _CSEN_PRSSEL_PRSSEL_PRSCH10, 
  csenPRSSELCh11 = _CSEN_PRSSEL_PRSSEL_PRSCH11, 
} CSEN_PRSSel_TypeDef;


typedef enum
{
  csenInputSelDefault        = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT,
  csenInputSelAPORT1CH0TO7   = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7,
  csenInputSelAPORT1CH8TO15  = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15,
  csenInputSelAPORT1CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23,
  csenInputSelAPORT1CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31,
  csenInputSelAPORT3CH0TO7   = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7,
  csenInputSelAPORT3CH8TO15  = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15,
  csenInputSelAPORT3CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23,
  csenInputSelAPORT3CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31,
} CSEN_InputSel_TypeDef;


typedef enum
{
  csenSingleSelDefault     = _CSEN_SINGLECTRL_SINGLESEL_DEFAULT,
  csenSingleSelAPORT1XCH0  = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0,
  csenSingleSelAPORT1YCH1  = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1,
  csenSingleSelAPORT1XCH2  = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2,
  csenSingleSelAPORT1YCH3  = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3,
  csenSingleSelAPORT1XCH4  = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4,
  csenSingleSelAPORT1YCH5  = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5,
  csenSingleSelAPORT1XCH6  = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6,
  csenSingleSelAPORT1YCH7  = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7,
  csenSingleSelAPORT1XCH8  = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8,
  csenSingleSelAPORT1YCH9  = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9,
  csenSingleSelAPORT1XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10,
  csenSingleSelAPORT1YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11,
  csenSingleSelAPORT1XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12,
  csenSingleSelAPORT1YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13,
  csenSingleSelAPORT1XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14,
  csenSingleSelAPORT1YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15,
  csenSingleSelAPORT1XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16,
  csenSingleSelAPORT1YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17,
  csenSingleSelAPORT1XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18,
  csenSingleSelAPORT1YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19,
  csenSingleSelAPORT1XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20,
  csenSingleSelAPORT1YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21,
  csenSingleSelAPORT1XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22,
  csenSingleSelAPORT1YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23,
  csenSingleSelAPORT1XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24,
  csenSingleSelAPORT1YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25,
  csenSingleSelAPORT1XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26,
  csenSingleSelAPORT1YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27,
  csenSingleSelAPORT1XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28,
  csenSingleSelAPORT1YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29,
  csenSingleSelAPORT1XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30,
  csenSingleSelAPORT1YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31,
  csenSingleSelAPORT3XCH0  = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0,
  csenSingleSelAPORT3YCH1  = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1,
  csenSingleSelAPORT3XCH2  = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2,
  csenSingleSelAPORT3YCH3  = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3,
  csenSingleSelAPORT3XCH4  = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4,
  csenSingleSelAPORT3YCH5  = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5,
  csenSingleSelAPORT3XCH6  = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6,
  csenSingleSelAPORT3YCH7  = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7,
  csenSingleSelAPORT3XCH8  = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8,
  csenSingleSelAPORT3YCH9  = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9,
  csenSingleSelAPORT3XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10,
  csenSingleSelAPORT3YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11,
  csenSingleSelAPORT3XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12,
  csenSingleSelAPORT3YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13,
  csenSingleSelAPORT3XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14,
  csenSingleSelAPORT3YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15,
  csenSingleSelAPORT3XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16,
  csenSingleSelAPORT3YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17,
  csenSingleSelAPORT3XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18,
  csenSingleSelAPORT3YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19,
  csenSingleSelAPORT3XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20,
  csenSingleSelAPORT3YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21,
  csenSingleSelAPORT3XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22,
  csenSingleSelAPORT3YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23,
  csenSingleSelAPORT3XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24,
  csenSingleSelAPORT3YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25,
  csenSingleSelAPORT3XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26,
  csenSingleSelAPORT3YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27,
  csenSingleSelAPORT3XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28,
  csenSingleSelAPORT3YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29,
  csenSingleSelAPORT3XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30,
  csenSingleSelAPORT3YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31,
} CSEN_SingleSel_TypeDef;


/*******************************************************************************
 *******************************   STRUCTS   ***********************************
 ******************************************************************************/

typedef struct
{
  bool                          cpAccuracyHi;

  bool                          localSense;

  bool                          keepWarm;

  uint8_t                       warmUpCount;

  uint8_t                       pcReload;

  CSEN_PCPrescale_TypeDef       pcPrescale;

  CSEN_PRSSel_TypeDef           prsSel;

  CSEN_InputSel_TypeDef         input0To7;
  CSEN_InputSel_TypeDef         input8To15;
  CSEN_InputSel_TypeDef         input16To23;
  CSEN_InputSel_TypeDef         input24To31;
  CSEN_InputSel_TypeDef         input32To39;
  CSEN_InputSel_TypeDef         input40To47;
  CSEN_InputSel_TypeDef         input48To55;
  CSEN_InputSel_TypeDef         input56To63;
} CSEN_Init_TypeDef;

#define CSEN_INIT_DEFAULT                                               \
{                                                                       \
  false,                        /* Charge pump low accuracy mode. */    \
  false,                        /* Use external kelvin connection. */   \
  false,                        /* Disable keep warm. */                \
  0,                            /* 0+3 cycle warmup time. */            \
  0,                            /* Period counter reload. */            \
  csenPCPrescaleDiv1,           /* Period counter prescale. */          \
  csenPRSSELCh0,                /* PRS channel 0. */                    \
  csenInputSelAPORT1CH0TO7,     /* input0To7   -> aport1ch0to7 */       \
  csenInputSelAPORT1CH8TO15,    /* input8To15  -> aport1ch8to15 */      \
  csenInputSelAPORT1CH16TO23,   /* input16To23 -> aport1ch16to23 */     \
  csenInputSelAPORT1CH24TO31,   /* input24To31 -> aport1ch24to31 */     \
  csenInputSelAPORT3CH0TO7,     /* input32To39 -> aport3ch0to7 */       \
  csenInputSelAPORT3CH8TO15,    /* input40To47 -> aport3ch8to15 */      \
  csenInputSelAPORT3CH16TO23,   /* input48To55 -> aport3ch16to23 */     \
  csenInputSelAPORT3CH24TO31,   /* input56To63 -> aport3ch24to31 */     \
}


typedef struct
{
  CSEN_SampleMode_TypeDef       sampleMode;

  CSEN_TrigSel_TypeDef          trigSel;

  bool                          enableDma;

  bool                          sumOnly;

  CSEN_AccMode_TypeDef          accMode;

  CSEN_EMASample_TypeDef        emaSample;

  CSEN_CmpMode_TypeDef          cmpMode;

  uint16_t                      cmpThr;

  CSEN_SingleSel_TypeDef        singleSel;

  uint32_t                      inputMask0;

  uint32_t                      inputMask1;

  bool                          autoGnd;

  CSEN_ConvSel_TypeDef          convSel;

  CSEN_SARRes_TypeDef           sarRes;

  CSEN_DMRes_TypeDef            dmRes;
  
  uint8_t                       dmIterPerCycle;
  
  uint8_t                       dmCycles;

  uint8_t                       dmDelta;

  bool                          dmFixedDelta;

  CSEN_ResetPhaseSel_TypeDef    resetPhase;

  CSEN_DriveSel_TypeDef         driveSel;

  CSEN_GainSel_TypeDef          gainSel;
} CSEN_InitMode_TypeDef;

#define CSEN_INITMODE_DEFAULT                                           \
{                                                                       \
  csenSampleModeSingle,         /* Sample one input and stop. */        \
  csenTrigSelStart,             /* Use start bit to trigger. */         \
  false,                        /* Disable DMA. */                      \
  false,                        /* Average the accumulated result. */   \
  csenAccMode1,                 /* Accumulate 1 sample. */              \
  csenEMASampleW1,              /* Disable the EMA. */                  \
  csenCmpModeDisabled,          /* Disable the comparator. */           \
  0,                            /* Comparator threshold not used. */    \
  csenSingleSelDefault,         /* Disconnect the single input. */      \
  0,                            /* Disable inputs 0 to 31. */           \
  0,                            /* Disable inputs 32 to 63. */          \
  false,                        /* Do not ground inactive inputs. */    \
  csenConvSelSAR,               /* Use the SAR converter. */            \
  csenSARRes10,                 /* Set SAR resolution to 10 bits. */    \
  csenDMRes10,                  /* Set DM resolution to 10 bits. */     \
  0,                            /* Set DM conv/cycle to default. */     \
  0,                            /* Set DM cycles to default. */         \
  0,                            /* Set DM initial delta to default. */  \
  false,                        /* Use DM auto delta reduction. */      \
  csenResetPhaseSel0,           /* Use shortest reset phase time. */    \
  csenDriveSelFull,             /* Use full output current. */          \
  csenGainSel8X,                /* Use highest converter gain. */       \
}


/*******************************************************************************
 *****************************   PROTOTYPES   **********************************
 ******************************************************************************/

/***************************************************************************/
__STATIC_INLINE uint32_t CSEN_DataGet(CSEN_TypeDef *csen)
{
  return csen->DATA;
}

/***************************************************************************/
__STATIC_INLINE uint32_t CSEN_EMAGet(CSEN_TypeDef *csen)
{
  return (csen->EMA & _CSEN_EMA_EMA_MASK);
}

/***************************************************************************/
__STATIC_INLINE void CSEN_EMASet(CSEN_TypeDef *csen, uint32_t ema)
{
  csen->EMA = ema & _CSEN_EMA_EMA_MASK;
}

/***************************************************************************/
__STATIC_INLINE void CSEN_Disable(CSEN_TypeDef *csen)
{
  BUS_RegBitWrite(&csen->CTRL, _CSEN_CTRL_EN_SHIFT, 0);
}

/***************************************************************************/
__STATIC_INLINE void CSEN_Enable(CSEN_TypeDef *csen)
{
  BUS_RegBitWrite(&csen->CTRL, _CSEN_CTRL_EN_SHIFT, 1);
}

void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down);
void CSEN_Init(CSEN_TypeDef *csen, const CSEN_Init_TypeDef *init);
void CSEN_InitMode(CSEN_TypeDef *csen, const CSEN_InitMode_TypeDef *init);
void CSEN_Reset(CSEN_TypeDef *csen);


/***************************************************************************/
__STATIC_INLINE void CSEN_IntClear(CSEN_TypeDef *csen, uint32_t flags)
{
  csen->IFC = flags;
}


/***************************************************************************/
__STATIC_INLINE void CSEN_IntDisable(CSEN_TypeDef *csen, uint32_t flags)
{
  csen->IEN &= ~flags;
}


/***************************************************************************/
__STATIC_INLINE void CSEN_IntEnable(CSEN_TypeDef *csen, uint32_t flags)
{
  csen->IEN |= flags;
}


/***************************************************************************/
__STATIC_INLINE uint32_t CSEN_IntGet(CSEN_TypeDef *csen)
{
  return csen->IF;
}


/***************************************************************************/
__STATIC_INLINE uint32_t CSEN_IntGetEnabled(CSEN_TypeDef *csen)
{
  uint32_t ien;

  /* Store CSENx->IEN in temporary variable in order to define explicit order
   * of volatile accesses. */
  ien = csen->IEN;

  /* Bitwise AND of pending and enabled interrupts */
  return csen->IF & ien;
}


/***************************************************************************/
__STATIC_INLINE void CSEN_IntSet(CSEN_TypeDef *csen, uint32_t flags)
{
  csen->IFS = flags;
}


/***************************************************************************/
__STATIC_INLINE bool CSEN_IsBusy(CSEN_TypeDef *csen)
{
  return (bool)(csen->STATUS & _CSEN_STATUS_CSENBUSY_MASK);
}


/***************************************************************************/
__STATIC_INLINE void CSEN_Start(CSEN_TypeDef *csen)
{
  csen->CMD = CSEN_CMD_START;
}


#ifdef __cplusplus
}
#endif

#endif /* defined(CSEN_COUNT) && (CSEN_COUNT > 0) */
#endif /* EM_CSEN_H */