EFR32 Blue Gecko 13 Software Documentation  efr32bg13-doc-5.1.2
efr32bg13p_smu.h File Reference

Detailed Description

EFR32BG13P_SMU register and bit field definitions.

Version
5.1.2

License

Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com

Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:

  1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
  2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
  3. This notice may not be removed or altered from any source distribution.

DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.

Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.

Definition in file efr32bg13p_smu.h.

Go to the source code of this file.

Data Structures

struct  SMU_TypeDef
 

Macros

#define _SMU_IEN_MASK   0x00000001UL
 
#define _SMU_IEN_PPUPRIV_DEFAULT   0x00000000UL
 
#define _SMU_IEN_PPUPRIV_MASK   0x1UL
 
#define _SMU_IEN_PPUPRIV_SHIFT   0
 
#define _SMU_IEN_RESETVALUE   0x00000000UL
 
#define _SMU_IF_MASK   0x00000001UL
 
#define _SMU_IF_PPUPRIV_DEFAULT   0x00000000UL
 
#define _SMU_IF_PPUPRIV_MASK   0x1UL
 
#define _SMU_IF_PPUPRIV_SHIFT   0
 
#define _SMU_IF_RESETVALUE   0x00000000UL
 
#define _SMU_IFC_MASK   0x00000001UL
 
#define _SMU_IFC_PPUPRIV_DEFAULT   0x00000000UL
 
#define _SMU_IFC_PPUPRIV_MASK   0x1UL
 
#define _SMU_IFC_PPUPRIV_SHIFT   0
 
#define _SMU_IFC_RESETVALUE   0x00000000UL
 
#define _SMU_IFS_MASK   0x00000001UL
 
#define _SMU_IFS_PPUPRIV_DEFAULT   0x00000000UL
 
#define _SMU_IFS_PPUPRIV_MASK   0x1UL
 
#define _SMU_IFS_PPUPRIV_SHIFT   0
 
#define _SMU_IFS_RESETVALUE   0x00000000UL
 
#define _SMU_PPUCTRL_ENABLE_DEFAULT   0x00000000UL
 
#define _SMU_PPUCTRL_ENABLE_MASK   0x1UL
 
#define _SMU_PPUCTRL_ENABLE_SHIFT   0
 
#define _SMU_PPUCTRL_MASK   0x00000001UL
 
#define _SMU_PPUCTRL_RESETVALUE   0x00000000UL
 
#define _SMU_PPUFS_MASK   0x0000007FUL
 
#define _SMU_PPUFS_PERIPHID_ACMP0   0x00000000UL
 
#define _SMU_PPUFS_PERIPHID_ACMP1   0x00000001UL
 
#define _SMU_PPUFS_PERIPHID_ADC0   0x00000002UL
 
#define _SMU_PPUFS_PERIPHID_CMU   0x00000005UL
 
#define _SMU_PPUFS_PERIPHID_CRYOTIMER   0x00000007UL
 
#define _SMU_PPUFS_PERIPHID_CRYPTO0   0x00000008UL
 
#define _SMU_PPUFS_PERIPHID_CRYPTO1   0x00000009UL
 
#define _SMU_PPUFS_PERIPHID_CSEN   0x0000000AUL
 
#define _SMU_PPUFS_PERIPHID_DEFAULT   0x00000000UL
 
#define _SMU_PPUFS_PERIPHID_EMU   0x0000000DUL
 
#define _SMU_PPUFS_PERIPHID_FPUEH   0x0000000EUL
 
#define _SMU_PPUFS_PERIPHID_GPCRC   0x00000010UL
 
#define _SMU_PPUFS_PERIPHID_GPIO   0x00000011UL
 
#define _SMU_PPUFS_PERIPHID_I2C0   0x00000012UL
 
#define _SMU_PPUFS_PERIPHID_I2C1   0x00000013UL
 
#define _SMU_PPUFS_PERIPHID_IDAC0   0x00000014UL
 
#define _SMU_PPUFS_PERIPHID_LDMA   0x00000016UL
 
#define _SMU_PPUFS_PERIPHID_LESENSE   0x00000017UL
 
#define _SMU_PPUFS_PERIPHID_LETIMER0   0x00000018UL
 
#define _SMU_PPUFS_PERIPHID_LEUART0   0x00000019UL
 
#define _SMU_PPUFS_PERIPHID_MASK   0x7FUL
 
#define _SMU_PPUFS_PERIPHID_MSC   0x00000015UL
 
#define _SMU_PPUFS_PERIPHID_PCNT0   0x0000001BUL
 
#define _SMU_PPUFS_PERIPHID_PRS   0x0000000CUL
 
#define _SMU_PPUFS_PERIPHID_RMU   0x00000020UL
 
#define _SMU_PPUFS_PERIPHID_RTCC   0x00000021UL
 
#define _SMU_PPUFS_PERIPHID_SHIFT   0
 
#define _SMU_PPUFS_PERIPHID_SMU   0x00000022UL
 
#define _SMU_PPUFS_PERIPHID_TIMER0   0x00000024UL
 
#define _SMU_PPUFS_PERIPHID_TIMER1   0x00000025UL
 
#define _SMU_PPUFS_PERIPHID_TRNG0   0x00000026UL
 
#define _SMU_PPUFS_PERIPHID_USART0   0x00000027UL
 
#define _SMU_PPUFS_PERIPHID_USART1   0x00000028UL
 
#define _SMU_PPUFS_PERIPHID_USART2   0x00000029UL
 
#define _SMU_PPUFS_PERIPHID_VDAC0   0x0000000BUL
 
#define _SMU_PPUFS_PERIPHID_WDOG0   0x0000002AUL
 
#define _SMU_PPUFS_PERIPHID_WDOG1   0x0000002BUL
 
#define _SMU_PPUFS_PERIPHID_WTIMER0   0x0000002CUL
 
#define _SMU_PPUFS_RESETVALUE   0x00000000UL
 
#define _SMU_PPUPATD0_ACMP0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ACMP0_MASK   0x1UL
 
#define _SMU_PPUPATD0_ACMP0_SHIFT   0
 
#define _SMU_PPUPATD0_ACMP1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ACMP1_MASK   0x2UL
 
#define _SMU_PPUPATD0_ACMP1_SHIFT   1
 
#define _SMU_PPUPATD0_ADC0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ADC0_MASK   0x4UL
 
#define _SMU_PPUPATD0_ADC0_SHIFT   2
 
#define _SMU_PPUPATD0_CMU_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CMU_MASK   0x20UL
 
#define _SMU_PPUPATD0_CMU_SHIFT   5
 
#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CRYOTIMER_MASK   0x80UL
 
#define _SMU_PPUPATD0_CRYOTIMER_SHIFT   7
 
#define _SMU_PPUPATD0_CRYPTO0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CRYPTO0_MASK   0x100UL
 
#define _SMU_PPUPATD0_CRYPTO0_SHIFT   8
 
#define _SMU_PPUPATD0_CRYPTO1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CRYPTO1_MASK   0x200UL
 
#define _SMU_PPUPATD0_CRYPTO1_SHIFT   9
 
#define _SMU_PPUPATD0_CSEN_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CSEN_MASK   0x400UL
 
#define _SMU_PPUPATD0_CSEN_SHIFT   10
 
#define _SMU_PPUPATD0_EMU_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_EMU_MASK   0x2000UL
 
#define _SMU_PPUPATD0_EMU_SHIFT   13
 
#define _SMU_PPUPATD0_FPUEH_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_FPUEH_MASK   0x4000UL
 
#define _SMU_PPUPATD0_FPUEH_SHIFT   14
 
#define _SMU_PPUPATD0_GPCRC_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_GPCRC_MASK   0x10000UL
 
#define _SMU_PPUPATD0_GPCRC_SHIFT   16
 
#define _SMU_PPUPATD0_GPIO_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_GPIO_MASK   0x20000UL
 
#define _SMU_PPUPATD0_GPIO_SHIFT   17
 
#define _SMU_PPUPATD0_I2C0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_I2C0_MASK   0x40000UL
 
#define _SMU_PPUPATD0_I2C0_SHIFT   18
 
#define _SMU_PPUPATD0_I2C1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_I2C1_MASK   0x80000UL
 
#define _SMU_PPUPATD0_I2C1_SHIFT   19
 
#define _SMU_PPUPATD0_IDAC0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_IDAC0_MASK   0x100000UL
 
#define _SMU_PPUPATD0_IDAC0_SHIFT   20
 
#define _SMU_PPUPATD0_LDMA_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LDMA_MASK   0x400000UL
 
#define _SMU_PPUPATD0_LDMA_SHIFT   22
 
#define _SMU_PPUPATD0_LESENSE_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LESENSE_MASK   0x800000UL
 
#define _SMU_PPUPATD0_LESENSE_SHIFT   23
 
#define _SMU_PPUPATD0_LETIMER0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LETIMER0_MASK   0x1000000UL
 
#define _SMU_PPUPATD0_LETIMER0_SHIFT   24
 
#define _SMU_PPUPATD0_LEUART0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LEUART0_MASK   0x2000000UL
 
#define _SMU_PPUPATD0_LEUART0_SHIFT   25
 
#define _SMU_PPUPATD0_MASK   0x0BFF7FA7UL
 
#define _SMU_PPUPATD0_MSC_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_MSC_MASK   0x200000UL
 
#define _SMU_PPUPATD0_MSC_SHIFT   21
 
#define _SMU_PPUPATD0_PCNT0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_PCNT0_MASK   0x8000000UL
 
#define _SMU_PPUPATD0_PCNT0_SHIFT   27
 
#define _SMU_PPUPATD0_PRS_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_PRS_MASK   0x1000UL
 
#define _SMU_PPUPATD0_PRS_SHIFT   12
 
#define _SMU_PPUPATD0_RESETVALUE   0x00000000UL
 
#define _SMU_PPUPATD0_VDAC0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_VDAC0_MASK   0x800UL
 
#define _SMU_PPUPATD0_VDAC0_SHIFT   11
 
#define _SMU_PPUPATD1_MASK   0x00001FF7UL
 
#define _SMU_PPUPATD1_RESETVALUE   0x00000000UL
 
#define _SMU_PPUPATD1_RMU_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_RMU_MASK   0x1UL
 
#define _SMU_PPUPATD1_RMU_SHIFT   0
 
#define _SMU_PPUPATD1_RTCC_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_RTCC_MASK   0x2UL
 
#define _SMU_PPUPATD1_RTCC_SHIFT   1
 
#define _SMU_PPUPATD1_SMU_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_SMU_MASK   0x4UL
 
#define _SMU_PPUPATD1_SMU_SHIFT   2
 
#define _SMU_PPUPATD1_TIMER0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TIMER0_MASK   0x10UL
 
#define _SMU_PPUPATD1_TIMER0_SHIFT   4
 
#define _SMU_PPUPATD1_TIMER1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TIMER1_MASK   0x20UL
 
#define _SMU_PPUPATD1_TIMER1_SHIFT   5
 
#define _SMU_PPUPATD1_TRNG0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TRNG0_MASK   0x40UL
 
#define _SMU_PPUPATD1_TRNG0_SHIFT   6
 
#define _SMU_PPUPATD1_USART0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USART0_MASK   0x80UL
 
#define _SMU_PPUPATD1_USART0_SHIFT   7
 
#define _SMU_PPUPATD1_USART1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USART1_MASK   0x100UL
 
#define _SMU_PPUPATD1_USART1_SHIFT   8
 
#define _SMU_PPUPATD1_USART2_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USART2_MASK   0x200UL
 
#define _SMU_PPUPATD1_USART2_SHIFT   9
 
#define _SMU_PPUPATD1_WDOG0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_WDOG0_MASK   0x400UL
 
#define _SMU_PPUPATD1_WDOG0_SHIFT   10
 
#define _SMU_PPUPATD1_WDOG1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_WDOG1_MASK   0x800UL
 
#define _SMU_PPUPATD1_WDOG1_SHIFT   11
 
#define _SMU_PPUPATD1_WTIMER0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_WTIMER0_MASK   0x1000UL
 
#define _SMU_PPUPATD1_WTIMER0_SHIFT   12
 
#define SMU_IEN_PPUPRIV   (0x1UL << 0)
 
#define SMU_IEN_PPUPRIV_DEFAULT   (_SMU_IEN_PPUPRIV_DEFAULT << 0)
 
#define SMU_IF_PPUPRIV   (0x1UL << 0)
 
#define SMU_IF_PPUPRIV_DEFAULT   (_SMU_IF_PPUPRIV_DEFAULT << 0)
 
#define SMU_IFC_PPUPRIV   (0x1UL << 0)
 
#define SMU_IFC_PPUPRIV_DEFAULT   (_SMU_IFC_PPUPRIV_DEFAULT << 0)
 
#define SMU_IFS_PPUPRIV   (0x1UL << 0)
 
#define SMU_IFS_PPUPRIV_DEFAULT   (_SMU_IFS_PPUPRIV_DEFAULT << 0)
 
#define SMU_PPUCTRL_ENABLE   (0x1UL << 0)
 
#define SMU_PPUCTRL_ENABLE_DEFAULT   (_SMU_PPUCTRL_ENABLE_DEFAULT << 0)
 
#define SMU_PPUFS_PERIPHID_ACMP0   (_SMU_PPUFS_PERIPHID_ACMP0 << 0)
 
#define SMU_PPUFS_PERIPHID_ACMP1   (_SMU_PPUFS_PERIPHID_ACMP1 << 0)
 
#define SMU_PPUFS_PERIPHID_ADC0   (_SMU_PPUFS_PERIPHID_ADC0 << 0)
 
#define SMU_PPUFS_PERIPHID_CMU   (_SMU_PPUFS_PERIPHID_CMU << 0)
 
#define SMU_PPUFS_PERIPHID_CRYOTIMER   (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0)
 
#define SMU_PPUFS_PERIPHID_CRYPTO0   (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0)
 
#define SMU_PPUFS_PERIPHID_CRYPTO1   (_SMU_PPUFS_PERIPHID_CRYPTO1 << 0)
 
#define SMU_PPUFS_PERIPHID_CSEN   (_SMU_PPUFS_PERIPHID_CSEN << 0)
 
#define SMU_PPUFS_PERIPHID_DEFAULT   (_SMU_PPUFS_PERIPHID_DEFAULT << 0)
 
#define SMU_PPUFS_PERIPHID_EMU   (_SMU_PPUFS_PERIPHID_EMU << 0)
 
#define SMU_PPUFS_PERIPHID_FPUEH   (_SMU_PPUFS_PERIPHID_FPUEH << 0)
 
#define SMU_PPUFS_PERIPHID_GPCRC   (_SMU_PPUFS_PERIPHID_GPCRC << 0)
 
#define SMU_PPUFS_PERIPHID_GPIO   (_SMU_PPUFS_PERIPHID_GPIO << 0)
 
#define SMU_PPUFS_PERIPHID_I2C0   (_SMU_PPUFS_PERIPHID_I2C0 << 0)
 
#define SMU_PPUFS_PERIPHID_I2C1   (_SMU_PPUFS_PERIPHID_I2C1 << 0)
 
#define SMU_PPUFS_PERIPHID_IDAC0   (_SMU_PPUFS_PERIPHID_IDAC0 << 0)
 
#define SMU_PPUFS_PERIPHID_LDMA   (_SMU_PPUFS_PERIPHID_LDMA << 0)
 
#define SMU_PPUFS_PERIPHID_LESENSE   (_SMU_PPUFS_PERIPHID_LESENSE << 0)
 
#define SMU_PPUFS_PERIPHID_LETIMER0   (_SMU_PPUFS_PERIPHID_LETIMER0 << 0)
 
#define SMU_PPUFS_PERIPHID_LEUART0   (_SMU_PPUFS_PERIPHID_LEUART0 << 0)
 
#define SMU_PPUFS_PERIPHID_MSC   (_SMU_PPUFS_PERIPHID_MSC << 0)
 
#define SMU_PPUFS_PERIPHID_PCNT0   (_SMU_PPUFS_PERIPHID_PCNT0 << 0)
 
#define SMU_PPUFS_PERIPHID_PRS   (_SMU_PPUFS_PERIPHID_PRS << 0)
 
#define SMU_PPUFS_PERIPHID_RMU   (_SMU_PPUFS_PERIPHID_RMU << 0)
 
#define SMU_PPUFS_PERIPHID_RTCC   (_SMU_PPUFS_PERIPHID_RTCC << 0)
 
#define SMU_PPUFS_PERIPHID_SMU   (_SMU_PPUFS_PERIPHID_SMU << 0)
 
#define SMU_PPUFS_PERIPHID_TIMER0   (_SMU_PPUFS_PERIPHID_TIMER0 << 0)
 
#define SMU_PPUFS_PERIPHID_TIMER1   (_SMU_PPUFS_PERIPHID_TIMER1 << 0)
 
#define SMU_PPUFS_PERIPHID_TRNG0   (_SMU_PPUFS_PERIPHID_TRNG0 << 0)
 
#define SMU_PPUFS_PERIPHID_USART0   (_SMU_PPUFS_PERIPHID_USART0 << 0)
 
#define SMU_PPUFS_PERIPHID_USART1   (_SMU_PPUFS_PERIPHID_USART1 << 0)
 
#define SMU_PPUFS_PERIPHID_USART2   (_SMU_PPUFS_PERIPHID_USART2 << 0)
 
#define SMU_PPUFS_PERIPHID_VDAC0   (_SMU_PPUFS_PERIPHID_VDAC0 << 0)
 
#define SMU_PPUFS_PERIPHID_WDOG0   (_SMU_PPUFS_PERIPHID_WDOG0 << 0)
 
#define SMU_PPUFS_PERIPHID_WDOG1   (_SMU_PPUFS_PERIPHID_WDOG1 << 0)
 
#define SMU_PPUFS_PERIPHID_WTIMER0   (_SMU_PPUFS_PERIPHID_WTIMER0 << 0)
 
#define SMU_PPUPATD0_ACMP0   (0x1UL << 0)
 
#define SMU_PPUPATD0_ACMP0_DEFAULT   (_SMU_PPUPATD0_ACMP0_DEFAULT << 0)
 
#define SMU_PPUPATD0_ACMP1   (0x1UL << 1)
 
#define SMU_PPUPATD0_ACMP1_DEFAULT   (_SMU_PPUPATD0_ACMP1_DEFAULT << 1)
 
#define SMU_PPUPATD0_ADC0   (0x1UL << 2)
 
#define SMU_PPUPATD0_ADC0_DEFAULT   (_SMU_PPUPATD0_ADC0_DEFAULT << 2)
 
#define SMU_PPUPATD0_CMU   (0x1UL << 5)
 
#define SMU_PPUPATD0_CMU_DEFAULT   (_SMU_PPUPATD0_CMU_DEFAULT << 5)
 
#define SMU_PPUPATD0_CRYOTIMER   (0x1UL << 7)
 
#define SMU_PPUPATD0_CRYOTIMER_DEFAULT   (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 7)
 
#define SMU_PPUPATD0_CRYPTO0   (0x1UL << 8)
 
#define SMU_PPUPATD0_CRYPTO0_DEFAULT   (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 8)
 
#define SMU_PPUPATD0_CRYPTO1   (0x1UL << 9)
 
#define SMU_PPUPATD0_CRYPTO1_DEFAULT   (_SMU_PPUPATD0_CRYPTO1_DEFAULT << 9)
 
#define SMU_PPUPATD0_CSEN   (0x1UL << 10)
 
#define SMU_PPUPATD0_CSEN_DEFAULT   (_SMU_PPUPATD0_CSEN_DEFAULT << 10)
 
#define SMU_PPUPATD0_EMU   (0x1UL << 13)
 
#define SMU_PPUPATD0_EMU_DEFAULT   (_SMU_PPUPATD0_EMU_DEFAULT << 13)
 
#define SMU_PPUPATD0_FPUEH   (0x1UL << 14)
 
#define SMU_PPUPATD0_FPUEH_DEFAULT   (_SMU_PPUPATD0_FPUEH_DEFAULT << 14)
 
#define SMU_PPUPATD0_GPCRC   (0x1UL << 16)
 
#define SMU_PPUPATD0_GPCRC_DEFAULT   (_SMU_PPUPATD0_GPCRC_DEFAULT << 16)
 
#define SMU_PPUPATD0_GPIO   (0x1UL << 17)
 
#define SMU_PPUPATD0_GPIO_DEFAULT   (_SMU_PPUPATD0_GPIO_DEFAULT << 17)
 
#define SMU_PPUPATD0_I2C0   (0x1UL << 18)
 
#define SMU_PPUPATD0_I2C0_DEFAULT   (_SMU_PPUPATD0_I2C0_DEFAULT << 18)
 
#define SMU_PPUPATD0_I2C1   (0x1UL << 19)
 
#define SMU_PPUPATD0_I2C1_DEFAULT   (_SMU_PPUPATD0_I2C1_DEFAULT << 19)
 
#define SMU_PPUPATD0_IDAC0   (0x1UL << 20)
 
#define SMU_PPUPATD0_IDAC0_DEFAULT   (_SMU_PPUPATD0_IDAC0_DEFAULT << 20)
 
#define SMU_PPUPATD0_LDMA   (0x1UL << 22)
 
#define SMU_PPUPATD0_LDMA_DEFAULT   (_SMU_PPUPATD0_LDMA_DEFAULT << 22)
 
#define SMU_PPUPATD0_LESENSE   (0x1UL << 23)
 
#define SMU_PPUPATD0_LESENSE_DEFAULT   (_SMU_PPUPATD0_LESENSE_DEFAULT << 23)
 
#define SMU_PPUPATD0_LETIMER0   (0x1UL << 24)
 
#define SMU_PPUPATD0_LETIMER0_DEFAULT   (_SMU_PPUPATD0_LETIMER0_DEFAULT << 24)
 
#define SMU_PPUPATD0_LEUART0   (0x1UL << 25)
 
#define SMU_PPUPATD0_LEUART0_DEFAULT   (_SMU_PPUPATD0_LEUART0_DEFAULT << 25)
 
#define SMU_PPUPATD0_MSC   (0x1UL << 21)
 
#define SMU_PPUPATD0_MSC_DEFAULT   (_SMU_PPUPATD0_MSC_DEFAULT << 21)
 
#define SMU_PPUPATD0_PCNT0   (0x1UL << 27)
 
#define SMU_PPUPATD0_PCNT0_DEFAULT   (_SMU_PPUPATD0_PCNT0_DEFAULT << 27)
 
#define SMU_PPUPATD0_PRS   (0x1UL << 12)
 
#define SMU_PPUPATD0_PRS_DEFAULT   (_SMU_PPUPATD0_PRS_DEFAULT << 12)
 
#define SMU_PPUPATD0_VDAC0   (0x1UL << 11)
 
#define SMU_PPUPATD0_VDAC0_DEFAULT   (_SMU_PPUPATD0_VDAC0_DEFAULT << 11)
 
#define SMU_PPUPATD1_RMU   (0x1UL << 0)
 
#define SMU_PPUPATD1_RMU_DEFAULT   (_SMU_PPUPATD1_RMU_DEFAULT << 0)
 
#define SMU_PPUPATD1_RTCC   (0x1UL << 1)
 
#define SMU_PPUPATD1_RTCC_DEFAULT   (_SMU_PPUPATD1_RTCC_DEFAULT << 1)
 
#define SMU_PPUPATD1_SMU   (0x1UL << 2)
 
#define SMU_PPUPATD1_SMU_DEFAULT   (_SMU_PPUPATD1_SMU_DEFAULT << 2)
 
#define SMU_PPUPATD1_TIMER0   (0x1UL << 4)
 
#define SMU_PPUPATD1_TIMER0_DEFAULT   (_SMU_PPUPATD1_TIMER0_DEFAULT << 4)
 
#define SMU_PPUPATD1_TIMER1   (0x1UL << 5)
 
#define SMU_PPUPATD1_TIMER1_DEFAULT   (_SMU_PPUPATD1_TIMER1_DEFAULT << 5)
 
#define SMU_PPUPATD1_TRNG0   (0x1UL << 6)
 
#define SMU_PPUPATD1_TRNG0_DEFAULT   (_SMU_PPUPATD1_TRNG0_DEFAULT << 6)
 
#define SMU_PPUPATD1_USART0   (0x1UL << 7)
 
#define SMU_PPUPATD1_USART0_DEFAULT   (_SMU_PPUPATD1_USART0_DEFAULT << 7)
 
#define SMU_PPUPATD1_USART1   (0x1UL << 8)
 
#define SMU_PPUPATD1_USART1_DEFAULT   (_SMU_PPUPATD1_USART1_DEFAULT << 8)
 
#define SMU_PPUPATD1_USART2   (0x1UL << 9)
 
#define SMU_PPUPATD1_USART2_DEFAULT   (_SMU_PPUPATD1_USART2_DEFAULT << 9)
 
#define SMU_PPUPATD1_WDOG0   (0x1UL << 10)
 
#define SMU_PPUPATD1_WDOG0_DEFAULT   (_SMU_PPUPATD1_WDOG0_DEFAULT << 10)
 
#define SMU_PPUPATD1_WDOG1   (0x1UL << 11)
 
#define SMU_PPUPATD1_WDOG1_DEFAULT   (_SMU_PPUPATD1_WDOG1_DEFAULT << 11)
 
#define SMU_PPUPATD1_WTIMER0   (0x1UL << 12)
 
#define SMU_PPUPATD1_WTIMER0_DEFAULT   (_SMU_PPUPATD1_WTIMER0_DEFAULT << 12)