EFR32 Blue Gecko 13 Software Documentation  efr32bg13-doc-5.1.2
efr32bg13p_emu.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
44  __IM uint32_t STATUS;
45  __IOM uint32_t LOCK;
46  __IOM uint32_t RAM0CTRL;
47  __IOM uint32_t CMD;
49  uint32_t RESERVED0[1];
50  __IOM uint32_t EM4CTRL;
51  __IOM uint32_t TEMPLIMITS;
52  __IM uint32_t TEMP;
53  __IM uint32_t IF;
54  __IOM uint32_t IFS;
55  __IOM uint32_t IFC;
56  __IOM uint32_t IEN;
57  __IOM uint32_t PWRLOCK;
59  uint32_t RESERVED1[1];
60  __IOM uint32_t PWRCTRL;
61  __IOM uint32_t DCDCCTRL;
63  uint32_t RESERVED2[2];
64  __IOM uint32_t DCDCMISCCTRL;
65  __IOM uint32_t DCDCZDETCTRL;
66  __IOM uint32_t DCDCCLIMCTRL;
67  __IOM uint32_t DCDCLNCOMPCTRL;
68  __IOM uint32_t DCDCLNVCTRL;
70  uint32_t RESERVED3[1];
71  __IOM uint32_t DCDCLPVCTRL;
73  uint32_t RESERVED4[1];
74  __IOM uint32_t DCDCLPCTRL;
75  __IOM uint32_t DCDCLNFREQCTRL;
77  uint32_t RESERVED5[1];
78  __IM uint32_t DCDCSYNC;
80  uint32_t RESERVED6[5];
81  __IOM uint32_t VMONAVDDCTRL;
82  __IOM uint32_t VMONALTAVDDCTRL;
83  __IOM uint32_t VMONDVDDCTRL;
84  __IOM uint32_t VMONIO0CTRL;
86  uint32_t RESERVED7[4];
87  __IOM uint32_t RAM1CTRL;
88  __IOM uint32_t RAM2CTRL;
90  uint32_t RESERVED8[10];
91  __IOM uint32_t DCDCLPEM01CFG;
93  uint32_t RESERVED9[4];
94  __IOM uint32_t EM23PERNORETAINCMD;
95  __IM uint32_t EM23PERNORETAINSTATUS;
96  __IOM uint32_t EM23PERNORETAINCTRL;
97 } EMU_TypeDef;
99 /**************************************************************************/
104 /* Bit fields for EMU CTRL */
105 #define _EMU_CTRL_RESETVALUE 0x00000000UL
106 #define _EMU_CTRL_MASK 0x0003031EUL
107 #define EMU_CTRL_EM2BLOCK (0x1UL << 1)
108 #define _EMU_CTRL_EM2BLOCK_SHIFT 1
109 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL
110 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL
111 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)
112 #define EMU_CTRL_EM2BODDIS (0x1UL << 2)
113 #define _EMU_CTRL_EM2BODDIS_SHIFT 2
114 #define _EMU_CTRL_EM2BODDIS_MASK 0x4UL
115 #define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL
116 #define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2)
117 #define EMU_CTRL_EM01LD (0x1UL << 3)
118 #define _EMU_CTRL_EM01LD_SHIFT 3
119 #define _EMU_CTRL_EM01LD_MASK 0x8UL
120 #define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL
121 #define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3)
122 #define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4)
123 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4
124 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL
125 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL
126 #define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4)
127 #define _EMU_CTRL_EM23VSCALE_SHIFT 8
128 #define _EMU_CTRL_EM23VSCALE_MASK 0x300UL
129 #define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL
130 #define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL
131 #define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL
132 #define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL
133 #define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8)
134 #define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8)
135 #define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8)
136 #define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8)
137 #define _EMU_CTRL_EM4HVSCALE_SHIFT 16
138 #define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL
139 #define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL
140 #define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL
141 #define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL
142 #define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL
143 #define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16)
144 #define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16)
145 #define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16)
146 #define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16)
148 /* Bit fields for EMU STATUS */
149 #define _EMU_STATUS_RESETVALUE 0x00000000UL
150 #define _EMU_STATUS_MASK 0x0417011FUL
151 #define EMU_STATUS_VMONRDY (0x1UL << 0)
152 #define _EMU_STATUS_VMONRDY_SHIFT 0
153 #define _EMU_STATUS_VMONRDY_MASK 0x1UL
154 #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL
155 #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0)
156 #define EMU_STATUS_VMONAVDD (0x1UL << 1)
157 #define _EMU_STATUS_VMONAVDD_SHIFT 1
158 #define _EMU_STATUS_VMONAVDD_MASK 0x2UL
159 #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL
160 #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1)
161 #define EMU_STATUS_VMONALTAVDD (0x1UL << 2)
162 #define _EMU_STATUS_VMONALTAVDD_SHIFT 2
163 #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL
164 #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL
165 #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2)
166 #define EMU_STATUS_VMONDVDD (0x1UL << 3)
167 #define _EMU_STATUS_VMONDVDD_SHIFT 3
168 #define _EMU_STATUS_VMONDVDD_MASK 0x8UL
169 #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL
170 #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3)
171 #define EMU_STATUS_VMONIO0 (0x1UL << 4)
172 #define _EMU_STATUS_VMONIO0_SHIFT 4
173 #define _EMU_STATUS_VMONIO0_MASK 0x10UL
174 #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL
175 #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4)
176 #define EMU_STATUS_VMONFVDD (0x1UL << 8)
177 #define _EMU_STATUS_VMONFVDD_SHIFT 8
178 #define _EMU_STATUS_VMONFVDD_MASK 0x100UL
179 #define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL
180 #define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8)
181 #define _EMU_STATUS_VSCALE_SHIFT 16
182 #define _EMU_STATUS_VSCALE_MASK 0x30000UL
183 #define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL
184 #define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL
185 #define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL
186 #define _EMU_STATUS_VSCALE_RESV 0x00000003UL
187 #define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16)
188 #define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16)
189 #define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16)
190 #define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16)
191 #define EMU_STATUS_VSCALEBUSY (0x1UL << 18)
192 #define _EMU_STATUS_VSCALEBUSY_SHIFT 18
193 #define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL
194 #define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL
195 #define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18)
196 #define EMU_STATUS_EM4IORET (0x1UL << 20)
197 #define _EMU_STATUS_EM4IORET_SHIFT 20
198 #define _EMU_STATUS_EM4IORET_MASK 0x100000UL
199 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL
200 #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL
201 #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL
202 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20)
203 #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20)
204 #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20)
205 #define EMU_STATUS_TEMPACTIVE (0x1UL << 26)
206 #define _EMU_STATUS_TEMPACTIVE_SHIFT 26
207 #define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL
208 #define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL
209 #define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26)
211 /* Bit fields for EMU LOCK */
212 #define _EMU_LOCK_RESETVALUE 0x00000000UL
213 #define _EMU_LOCK_MASK 0x0000FFFFUL
214 #define _EMU_LOCK_LOCKKEY_SHIFT 0
215 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL
216 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
217 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL
218 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
219 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
220 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL
221 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0)
222 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0)
223 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0)
224 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0)
225 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0)
227 /* Bit fields for EMU RAM0CTRL */
228 #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL
229 #define _EMU_RAM0CTRL_MASK 0x00000001UL
230 #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0
231 #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x1UL
232 #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL
233 #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL
234 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1 0x00000001UL
235 #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0)
236 #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0)
237 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1 << 0)
239 /* Bit fields for EMU CMD */
240 #define _EMU_CMD_RESETVALUE 0x00000000UL
241 #define _EMU_CMD_MASK 0x00000051UL
242 #define EMU_CMD_EM4UNLATCH (0x1UL << 0)
243 #define _EMU_CMD_EM4UNLATCH_SHIFT 0
244 #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL
245 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL
246 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0)
247 #define EMU_CMD_EM01VSCALE0 (0x1UL << 4)
248 #define _EMU_CMD_EM01VSCALE0_SHIFT 4
249 #define _EMU_CMD_EM01VSCALE0_MASK 0x10UL
250 #define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL
251 #define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4)
252 #define EMU_CMD_EM01VSCALE2 (0x1UL << 6)
253 #define _EMU_CMD_EM01VSCALE2_SHIFT 6
254 #define _EMU_CMD_EM01VSCALE2_MASK 0x40UL
255 #define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL
256 #define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6)
258 /* Bit fields for EMU EM4CTRL */
259 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL
260 #define _EMU_EM4CTRL_MASK 0x0003003FUL
261 #define EMU_EM4CTRL_EM4STATE (0x1UL << 0)
262 #define _EMU_EM4CTRL_EM4STATE_SHIFT 0
263 #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL
264 #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL
265 #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL
266 #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL
267 #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0)
268 #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0)
269 #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0)
270 #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1)
271 #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1
272 #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL
273 #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL
274 #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1)
275 #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2)
276 #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2
277 #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL
278 #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL
279 #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2)
280 #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3)
281 #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3
282 #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL
283 #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL
284 #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3)
285 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4
286 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL
287 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL
288 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL
289 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL
290 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL
291 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4)
292 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4)
293 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4)
294 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4)
295 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16
296 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL
297 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL
298 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16)
300 /* Bit fields for EMU TEMPLIMITS */
301 #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL
302 #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL
303 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0
304 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL
305 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL
306 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0)
307 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8
308 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL
309 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL
310 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8)
311 #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16)
312 #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16
313 #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL
314 #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL
315 #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16)
317 /* Bit fields for EMU TEMP */
318 #define _EMU_TEMP_RESETVALUE 0x00000000UL
319 #define _EMU_TEMP_MASK 0x000000FFUL
320 #define _EMU_TEMP_TEMP_SHIFT 0
321 #define _EMU_TEMP_TEMP_MASK 0xFFUL
322 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL
323 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0)
325 /* Bit fields for EMU IF */
326 #define _EMU_IF_RESETVALUE 0x00000000UL
327 #define _EMU_IF_MASK 0xE31FC0FFUL
328 #define EMU_IF_VMONAVDDFALL (0x1UL << 0)
329 #define _EMU_IF_VMONAVDDFALL_SHIFT 0
330 #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL
331 #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL
332 #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0)
333 #define EMU_IF_VMONAVDDRISE (0x1UL << 1)
334 #define _EMU_IF_VMONAVDDRISE_SHIFT 1
335 #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL
336 #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL
337 #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1)
338 #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2)
339 #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2
340 #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL
341 #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL
342 #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2)
343 #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3)
344 #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3
345 #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL
346 #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL
347 #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3)
348 #define EMU_IF_VMONDVDDFALL (0x1UL << 4)
349 #define _EMU_IF_VMONDVDDFALL_SHIFT 4
350 #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL
351 #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL
352 #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4)
353 #define EMU_IF_VMONDVDDRISE (0x1UL << 5)
354 #define _EMU_IF_VMONDVDDRISE_SHIFT 5
355 #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL
356 #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL
357 #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5)
358 #define EMU_IF_VMONIO0FALL (0x1UL << 6)
359 #define _EMU_IF_VMONIO0FALL_SHIFT 6
360 #define _EMU_IF_VMONIO0FALL_MASK 0x40UL
361 #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL
362 #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6)
363 #define EMU_IF_VMONIO0RISE (0x1UL << 7)
364 #define _EMU_IF_VMONIO0RISE_SHIFT 7
365 #define _EMU_IF_VMONIO0RISE_MASK 0x80UL
366 #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL
367 #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7)
368 #define EMU_IF_VMONFVDDFALL (0x1UL << 14)
369 #define _EMU_IF_VMONFVDDFALL_SHIFT 14
370 #define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL
371 #define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL
372 #define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14)
373 #define EMU_IF_VMONFVDDRISE (0x1UL << 15)
374 #define _EMU_IF_VMONFVDDRISE_SHIFT 15
375 #define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL
376 #define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL
377 #define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15)
378 #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16)
379 #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16
380 #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL
381 #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
382 #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16)
383 #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17)
384 #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17
385 #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL
386 #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
387 #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17)
388 #define EMU_IF_DCDCLPRUNNING (0x1UL << 18)
389 #define _EMU_IF_DCDCLPRUNNING_SHIFT 18
390 #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL
391 #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL
392 #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18)
393 #define EMU_IF_DCDCLNRUNNING (0x1UL << 19)
394 #define _EMU_IF_DCDCLNRUNNING_SHIFT 19
395 #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL
396 #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL
397 #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19)
398 #define EMU_IF_DCDCINBYPASS (0x1UL << 20)
399 #define _EMU_IF_DCDCINBYPASS_SHIFT 20
400 #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL
401 #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL
402 #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20)
403 #define EMU_IF_EM23WAKEUP (0x1UL << 24)
404 #define _EMU_IF_EM23WAKEUP_SHIFT 24
405 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL
406 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL
407 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24)
408 #define EMU_IF_VSCALEDONE (0x1UL << 25)
409 #define _EMU_IF_VSCALEDONE_SHIFT 25
410 #define _EMU_IF_VSCALEDONE_MASK 0x2000000UL
411 #define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL
412 #define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25)
413 #define EMU_IF_TEMP (0x1UL << 29)
414 #define _EMU_IF_TEMP_SHIFT 29
415 #define _EMU_IF_TEMP_MASK 0x20000000UL
416 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL
417 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29)
418 #define EMU_IF_TEMPLOW (0x1UL << 30)
419 #define _EMU_IF_TEMPLOW_SHIFT 30
420 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL
421 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL
422 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30)
423 #define EMU_IF_TEMPHIGH (0x1UL << 31)
424 #define _EMU_IF_TEMPHIGH_SHIFT 31
425 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL
426 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL
427 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31)
429 /* Bit fields for EMU IFS */
430 #define _EMU_IFS_RESETVALUE 0x00000000UL
431 #define _EMU_IFS_MASK 0xE31FC0FFUL
432 #define EMU_IFS_VMONAVDDFALL (0x1UL << 0)
433 #define _EMU_IFS_VMONAVDDFALL_SHIFT 0
434 #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL
435 #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL
436 #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0)
437 #define EMU_IFS_VMONAVDDRISE (0x1UL << 1)
438 #define _EMU_IFS_VMONAVDDRISE_SHIFT 1
439 #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL
440 #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL
441 #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1)
442 #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2)
443 #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2
444 #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL
445 #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL
446 #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2)
447 #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3)
448 #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3
449 #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL
450 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL
451 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3)
452 #define EMU_IFS_VMONDVDDFALL (0x1UL << 4)
453 #define _EMU_IFS_VMONDVDDFALL_SHIFT 4
454 #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL
455 #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL
456 #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4)
457 #define EMU_IFS_VMONDVDDRISE (0x1UL << 5)
458 #define _EMU_IFS_VMONDVDDRISE_SHIFT 5
459 #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL
460 #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL
461 #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5)
462 #define EMU_IFS_VMONIO0FALL (0x1UL << 6)
463 #define _EMU_IFS_VMONIO0FALL_SHIFT 6
464 #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL
465 #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL
466 #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6)
467 #define EMU_IFS_VMONIO0RISE (0x1UL << 7)
468 #define _EMU_IFS_VMONIO0RISE_SHIFT 7
469 #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL
470 #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL
471 #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7)
472 #define EMU_IFS_VMONFVDDFALL (0x1UL << 14)
473 #define _EMU_IFS_VMONFVDDFALL_SHIFT 14
474 #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL
475 #define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL
476 #define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14)
477 #define EMU_IFS_VMONFVDDRISE (0x1UL << 15)
478 #define _EMU_IFS_VMONFVDDRISE_SHIFT 15
479 #define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL
480 #define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL
481 #define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15)
482 #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16)
483 #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16
484 #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL
485 #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
486 #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16)
487 #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17)
488 #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17
489 #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL
490 #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
491 #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17)
492 #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18)
493 #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18
494 #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL
495 #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL
496 #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18)
497 #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19)
498 #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19
499 #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL
500 #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL
501 #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19)
502 #define EMU_IFS_DCDCINBYPASS (0x1UL << 20)
503 #define _EMU_IFS_DCDCINBYPASS_SHIFT 20
504 #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL
505 #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL
506 #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20)
507 #define EMU_IFS_EM23WAKEUP (0x1UL << 24)
508 #define _EMU_IFS_EM23WAKEUP_SHIFT 24
509 #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL
510 #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL
511 #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24)
512 #define EMU_IFS_VSCALEDONE (0x1UL << 25)
513 #define _EMU_IFS_VSCALEDONE_SHIFT 25
514 #define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL
515 #define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL
516 #define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25)
517 #define EMU_IFS_TEMP (0x1UL << 29)
518 #define _EMU_IFS_TEMP_SHIFT 29
519 #define _EMU_IFS_TEMP_MASK 0x20000000UL
520 #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL
521 #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29)
522 #define EMU_IFS_TEMPLOW (0x1UL << 30)
523 #define _EMU_IFS_TEMPLOW_SHIFT 30
524 #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL
525 #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL
526 #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30)
527 #define EMU_IFS_TEMPHIGH (0x1UL << 31)
528 #define _EMU_IFS_TEMPHIGH_SHIFT 31
529 #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL
530 #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL
531 #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31)
533 /* Bit fields for EMU IFC */
534 #define _EMU_IFC_RESETVALUE 0x00000000UL
535 #define _EMU_IFC_MASK 0xE31FC0FFUL
536 #define EMU_IFC_VMONAVDDFALL (0x1UL << 0)
537 #define _EMU_IFC_VMONAVDDFALL_SHIFT 0
538 #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL
539 #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL
540 #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0)
541 #define EMU_IFC_VMONAVDDRISE (0x1UL << 1)
542 #define _EMU_IFC_VMONAVDDRISE_SHIFT 1
543 #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL
544 #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL
545 #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1)
546 #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2)
547 #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2
548 #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL
549 #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL
550 #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2)
551 #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3)
552 #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3
553 #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL
554 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL
555 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3)
556 #define EMU_IFC_VMONDVDDFALL (0x1UL << 4)
557 #define _EMU_IFC_VMONDVDDFALL_SHIFT 4
558 #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL
559 #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL
560 #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4)
561 #define EMU_IFC_VMONDVDDRISE (0x1UL << 5)
562 #define _EMU_IFC_VMONDVDDRISE_SHIFT 5
563 #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL
564 #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL
565 #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5)
566 #define EMU_IFC_VMONIO0FALL (0x1UL << 6)
567 #define _EMU_IFC_VMONIO0FALL_SHIFT 6
568 #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL
569 #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL
570 #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6)
571 #define EMU_IFC_VMONIO0RISE (0x1UL << 7)
572 #define _EMU_IFC_VMONIO0RISE_SHIFT 7
573 #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL
574 #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL
575 #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7)
576 #define EMU_IFC_VMONFVDDFALL (0x1UL << 14)
577 #define _EMU_IFC_VMONFVDDFALL_SHIFT 14
578 #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL
579 #define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL
580 #define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14)
581 #define EMU_IFC_VMONFVDDRISE (0x1UL << 15)
582 #define _EMU_IFC_VMONFVDDRISE_SHIFT 15
583 #define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL
584 #define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL
585 #define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15)
586 #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16)
587 #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16
588 #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL
589 #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
590 #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16)
591 #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17)
592 #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17
593 #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL
594 #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
595 #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17)
596 #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18)
597 #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18
598 #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL
599 #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL
600 #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18)
601 #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19)
602 #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19
603 #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL
604 #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL
605 #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19)
606 #define EMU_IFC_DCDCINBYPASS (0x1UL << 20)
607 #define _EMU_IFC_DCDCINBYPASS_SHIFT 20
608 #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL
609 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL
610 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20)
611 #define EMU_IFC_EM23WAKEUP (0x1UL << 24)
612 #define _EMU_IFC_EM23WAKEUP_SHIFT 24
613 #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL
614 #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL
615 #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24)
616 #define EMU_IFC_VSCALEDONE (0x1UL << 25)
617 #define _EMU_IFC_VSCALEDONE_SHIFT 25
618 #define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL
619 #define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL
620 #define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25)
621 #define EMU_IFC_TEMP (0x1UL << 29)
622 #define _EMU_IFC_TEMP_SHIFT 29
623 #define _EMU_IFC_TEMP_MASK 0x20000000UL
624 #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL
625 #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29)
626 #define EMU_IFC_TEMPLOW (0x1UL << 30)
627 #define _EMU_IFC_TEMPLOW_SHIFT 30
628 #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL
629 #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL
630 #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30)
631 #define EMU_IFC_TEMPHIGH (0x1UL << 31)
632 #define _EMU_IFC_TEMPHIGH_SHIFT 31
633 #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL
634 #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL
635 #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31)
637 /* Bit fields for EMU IEN */
638 #define _EMU_IEN_RESETVALUE 0x00000000UL
639 #define _EMU_IEN_MASK 0xE31FC0FFUL
640 #define EMU_IEN_VMONAVDDFALL (0x1UL << 0)
641 #define _EMU_IEN_VMONAVDDFALL_SHIFT 0
642 #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL
643 #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL
644 #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0)
645 #define EMU_IEN_VMONAVDDRISE (0x1UL << 1)
646 #define _EMU_IEN_VMONAVDDRISE_SHIFT 1
647 #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL
648 #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL
649 #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1)
650 #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2)
651 #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2
652 #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL
653 #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL
654 #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2)
655 #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3)
656 #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3
657 #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL
658 #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL
659 #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3)
660 #define EMU_IEN_VMONDVDDFALL (0x1UL << 4)
661 #define _EMU_IEN_VMONDVDDFALL_SHIFT 4
662 #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL
663 #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL
664 #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4)
665 #define EMU_IEN_VMONDVDDRISE (0x1UL << 5)
666 #define _EMU_IEN_VMONDVDDRISE_SHIFT 5
667 #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL
668 #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL
669 #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5)
670 #define EMU_IEN_VMONIO0FALL (0x1UL << 6)
671 #define _EMU_IEN_VMONIO0FALL_SHIFT 6
672 #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL
673 #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL
674 #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6)
675 #define EMU_IEN_VMONIO0RISE (0x1UL << 7)
676 #define _EMU_IEN_VMONIO0RISE_SHIFT 7
677 #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL
678 #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL
679 #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7)
680 #define EMU_IEN_VMONFVDDFALL (0x1UL << 14)
681 #define _EMU_IEN_VMONFVDDFALL_SHIFT 14
682 #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL
683 #define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL
684 #define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14)
685 #define EMU_IEN_VMONFVDDRISE (0x1UL << 15)
686 #define _EMU_IEN_VMONFVDDRISE_SHIFT 15
687 #define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL
688 #define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL
689 #define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15)
690 #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16)
691 #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16
692 #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL
693 #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
694 #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16)
695 #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17)
696 #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17
697 #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL
698 #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL
699 #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17)
700 #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18)
701 #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18
702 #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL
703 #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL
704 #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18)
705 #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19)
706 #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19
707 #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL
708 #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL
709 #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19)
710 #define EMU_IEN_DCDCINBYPASS (0x1UL << 20)
711 #define _EMU_IEN_DCDCINBYPASS_SHIFT 20
712 #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL
713 #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL
714 #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20)
715 #define EMU_IEN_EM23WAKEUP (0x1UL << 24)
716 #define _EMU_IEN_EM23WAKEUP_SHIFT 24
717 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL
718 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL
719 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24)
720 #define EMU_IEN_VSCALEDONE (0x1UL << 25)
721 #define _EMU_IEN_VSCALEDONE_SHIFT 25
722 #define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL
723 #define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL
724 #define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25)
725 #define EMU_IEN_TEMP (0x1UL << 29)
726 #define _EMU_IEN_TEMP_SHIFT 29
727 #define _EMU_IEN_TEMP_MASK 0x20000000UL
728 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL
729 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29)
730 #define EMU_IEN_TEMPLOW (0x1UL << 30)
731 #define _EMU_IEN_TEMPLOW_SHIFT 30
732 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL
733 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL
734 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30)
735 #define EMU_IEN_TEMPHIGH (0x1UL << 31)
736 #define _EMU_IEN_TEMPHIGH_SHIFT 31
737 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL
738 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL
739 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31)
741 /* Bit fields for EMU PWRLOCK */
742 #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL
743 #define _EMU_PWRLOCK_MASK 0x0000FFFFUL
744 #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0
745 #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL
746 #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL
747 #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL
748 #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL
749 #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL
750 #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL
751 #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0)
752 #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0)
753 #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0)
754 #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0)
755 #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0)
757 /* Bit fields for EMU PWRCTRL */
758 #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL
759 #define _EMU_PWRCTRL_MASK 0x00002420UL
760 #define EMU_PWRCTRL_ANASW (0x1UL << 5)
761 #define _EMU_PWRCTRL_ANASW_SHIFT 5
762 #define _EMU_PWRCTRL_ANASW_MASK 0x20UL
763 #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL
764 #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL
765 #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL
766 #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5)
767 #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5)
768 #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5)
769 #define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10)
770 #define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10
771 #define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL
772 #define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL
773 #define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL
774 #define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL
775 #define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10)
776 #define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10)
777 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10)
778 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13)
779 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13
780 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL
781 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL
782 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13)
784 /* Bit fields for EMU DCDCCTRL */
785 #define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL
786 #define _EMU_DCDCCTRL_MASK 0x00000033UL
787 #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0
788 #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL
789 #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL
790 #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL
791 #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL
792 #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL
793 #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL
794 #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0)
795 #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0)
796 #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0)
797 #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0)
798 #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0)
799 #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4)
800 #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4
801 #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL
802 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL
803 #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL
804 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL
805 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4)
806 #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4)
807 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4)
808 #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5)
809 #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5
810 #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL
811 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL
812 #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL
813 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL
814 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5)
815 #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5)
816 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5)
818 /* Bit fields for EMU DCDCMISCCTRL */
819 #define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL
820 #define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL
821 #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0)
822 #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0
823 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL
824 #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL
825 #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0)
826 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1)
827 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1
828 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL
829 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL
830 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1)
831 #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2)
832 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2
833 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL
834 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL
835 #define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2)
836 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5)
837 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5
838 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL
839 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL
840 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5)
841 #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8
842 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL
843 #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL
844 #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8)
845 #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12
846 #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL
847 #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL
848 #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12)
849 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16
850 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL
851 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL
852 #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16)
853 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20
854 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL
855 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL
856 #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20)
857 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24
858 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL
859 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL
860 #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24)
861 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28
862 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL
863 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL
864 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL
865 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL
866 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL
867 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL
868 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28)
869 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28)
870 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28)
871 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28)
872 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28)
874 /* Bit fields for EMU DCDCZDETCTRL */
875 #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL
876 #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL
877 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4
878 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL
879 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL
880 #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4)
881 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8
882 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL
883 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL
884 #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8)
886 /* Bit fields for EMU DCDCCLIMCTRL */
887 #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL
888 #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL
889 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8
890 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL
891 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL
892 #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8)
893 #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13)
894 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13
895 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL
896 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL
897 #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13)
899 /* Bit fields for EMU DCDCLNCOMPCTRL */
900 #define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL
901 #define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL
902 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0
903 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL
904 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL
905 #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0)
906 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4
907 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL
908 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL
909 #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4)
910 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12
911 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL
912 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL
913 #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12)
914 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20
915 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL
916 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL
917 #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20)
918 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24
919 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL
920 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL
921 #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24)
922 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28
923 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL
924 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL
925 #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28)
927 /* Bit fields for EMU DCDCLNVCTRL */
928 #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL
929 #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL
930 #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1)
931 #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1
932 #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL
933 #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL
934 #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL
935 #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL
936 #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1)
937 #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1)
938 #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1)
939 #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8
940 #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL
941 #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL
942 #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8)
944 /* Bit fields for EMU DCDCLPVCTRL */
945 #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL
946 #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL
947 #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0)
948 #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0
949 #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL
950 #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL
951 #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL
952 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL
953 #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0)
954 #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0)
955 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0)
956 #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1
957 #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL
958 #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL
959 #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1)
961 /* Bit fields for EMU DCDCLPCTRL */
962 #define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL
963 #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL
964 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12
965 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL
966 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL
967 #define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12)
968 #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24)
969 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24
970 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL
971 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL
972 #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24)
973 #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25
974 #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL
975 #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL
976 #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25)
978 /* Bit fields for EMU DCDCLNFREQCTRL */
979 #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL
980 #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL
981 #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0
982 #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL
983 #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL
984 #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0)
985 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24
986 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL
987 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL
988 #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24)
990 /* Bit fields for EMU DCDCSYNC */
991 #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL
992 #define _EMU_DCDCSYNC_MASK 0x00000001UL
993 #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0)
994 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0
995 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL
996 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL
997 #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0)
999 /* Bit fields for EMU VMONAVDDCTRL */
1000 #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL
1001 #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL
1002 #define EMU_VMONAVDDCTRL_EN (0x1UL << 0)
1003 #define _EMU_VMONAVDDCTRL_EN_SHIFT 0
1004 #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL
1005 #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL
1006 #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0)
1007 #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2)
1008 #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2
1009 #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL
1010 #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL
1011 #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2)
1012 #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3)
1013 #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3
1014 #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL
1015 #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL
1016 #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3)
1017 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8
1018 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL
1019 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL
1020 #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8)
1021 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12
1022 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL
1023 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL
1024 #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12)
1025 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16
1026 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL
1027 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL
1028 #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16)
1029 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20
1030 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL
1031 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL
1032 #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20)
1034 /* Bit fields for EMU VMONALTAVDDCTRL */
1035 #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL
1036 #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL
1037 #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0)
1038 #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0
1039 #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL
1040 #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL
1041 #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0)
1042 #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2)
1043 #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2
1044 #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL
1045 #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL
1046 #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2)
1047 #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3)
1048 #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3
1049 #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL
1050 #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL
1051 #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3)
1052 #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8
1053 #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL
1054 #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL
1055 #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8)
1056 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12
1057 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL
1058 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL
1059 #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12)
1061 /* Bit fields for EMU VMONDVDDCTRL */
1062 #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL
1063 #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL
1064 #define EMU_VMONDVDDCTRL_EN (0x1UL << 0)
1065 #define _EMU_VMONDVDDCTRL_EN_SHIFT 0
1066 #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL
1067 #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL
1068 #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0)
1069 #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2)
1070 #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2
1071 #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL
1072 #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL
1073 #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2)
1074 #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3)
1075 #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3
1076 #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL
1077 #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL
1078 #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3)
1079 #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8
1080 #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL
1081 #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL
1082 #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8)
1083 #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12
1084 #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL
1085 #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL
1086 #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12)
1088 /* Bit fields for EMU VMONIO0CTRL */
1089 #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL
1090 #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL
1091 #define EMU_VMONIO0CTRL_EN (0x1UL << 0)
1092 #define _EMU_VMONIO0CTRL_EN_SHIFT 0
1093 #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL
1094 #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL
1095 #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0)
1096 #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2)
1097 #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2
1098 #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL
1099 #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL
1100 #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2)
1101 #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3)
1102 #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3
1103 #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL
1104 #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL
1105 #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3)
1106 #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4)
1107 #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4
1108 #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL
1109 #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL
1110 #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4)
1111 #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8
1112 #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL
1113 #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL
1114 #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8)
1115 #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12
1116 #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL
1117 #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL
1118 #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12)
1120 /* Bit fields for EMU RAM1CTRL */
1121 #define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL
1122 #define _EMU_RAM1CTRL_MASK 0x00000003UL
1123 #define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0
1124 #define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0x3UL
1125 #define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL
1126 #define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL
1127 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 0x00000002UL
1128 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 0x00000003UL
1129 #define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0)
1130 #define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0)
1131 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 << 0)
1132 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 << 0)
1134 /* Bit fields for EMU RAM2CTRL */
1135 #define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL
1136 #define _EMU_RAM2CTRL_MASK 0x00000001UL
1137 #define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0
1138 #define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0x1UL
1139 #define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL
1140 #define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL
1141 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK 0x00000001UL
1142 #define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0)
1143 #define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0)
1144 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0)
1146 /* Bit fields for EMU DCDCLPEM01CFG */
1147 #define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL
1148 #define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL
1149 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8
1150 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL
1151 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL
1152 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL
1153 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL
1154 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL
1155 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL
1156 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8)
1157 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8)
1158 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8)
1159 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8)
1160 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8)
1161 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12
1162 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL
1163 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL
1164 #define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12)
1166 /* Bit fields for EMU EM23PERNORETAINCMD */
1167 #define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL
1168 #define _EMU_EM23PERNORETAINCMD_MASK 0x0000FFE7UL
1169 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0)
1170 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0
1171 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL
1172 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL
1173 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0)
1174 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1)
1175 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1
1176 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL
1177 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL
1178 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1)
1179 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2)
1180 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2
1181 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL
1182 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL
1183 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2)
1184 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5)
1185 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5
1186 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL
1187 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL
1188 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5)
1189 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6)
1190 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6
1191 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL
1192 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL
1193 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6)
1194 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7)
1195 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7
1196 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL
1197 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL
1198 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7)
1199 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8)
1200 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8
1201 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL
1202 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL
1203 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8)
1204 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9)
1205 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9
1206 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL
1207 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL
1208 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9)
1209 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10)
1210 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10
1211 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL
1212 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL
1213 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10)
1214 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11)
1215 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11
1216 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL
1217 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL
1218 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11)
1219 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12)
1220 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12
1221 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL
1222 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL
1223 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12)
1224 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13)
1225 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13
1226 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL
1227 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL
1228 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13)
1229 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14)
1230 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14
1231 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL
1232 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL
1233 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14)
1234 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15)
1235 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15
1236 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL
1237 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL
1238 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15)
1240 /* Bit fields for EMU EM23PERNORETAINSTATUS */
1241 #define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL
1242 #define _EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFE7UL
1243 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0)
1244 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0
1245 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL
1246 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL
1247 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0)
1248 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1)
1249 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1
1250 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL
1251 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL
1252 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1)
1253 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2)
1254 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2
1255 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL
1256 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL
1257 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2)
1258 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5)
1259 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5
1260 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL
1261 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL
1262 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5)
1263 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6)
1264 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6
1265 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL
1266 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL
1267 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6)
1268 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7)
1269 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7
1270 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL
1271 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL
1272 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7)
1273 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8)
1274 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8
1275 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL
1276 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL
1277 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8)
1278 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9)
1279 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9
1280 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL
1281 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL
1282 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9)
1283 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10)
1284 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10
1285 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL
1286 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL
1287 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10)
1288 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11)
1289 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11
1290 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL
1291 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL
1292 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11)
1293 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12)
1294 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12
1295 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL
1296 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL
1297 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12)
1298 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13)
1299 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13
1300 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL
1301 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL
1302 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13)
1303 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14)
1304 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14
1305 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL
1306 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL
1307 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14)
1308 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15)
1309 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15
1310 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL
1311 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL
1312 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15)
1314 /* Bit fields for EMU EM23PERNORETAINCTRL */
1315 #define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL
1316 #define _EMU_EM23PERNORETAINCTRL_MASK 0x0000FFE7UL
1317 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0)
1318 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0
1319 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL
1320 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL
1321 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0)
1322 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1)
1323 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1
1324 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL
1325 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL
1326 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1)
1327 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2)
1328 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2
1329 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL
1330 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL
1331 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2)
1332 #define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5)
1333 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5
1334 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL
1335 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL
1336 #define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5)
1337 #define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6)
1338 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6
1339 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL
1340 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL
1341 #define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6)
1342 #define EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7)
1343 #define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7
1344 #define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL
1345 #define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL
1346 #define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7)
1347 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8)
1348 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8
1349 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL
1350 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL
1351 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8)
1352 #define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9)
1353 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9
1354 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL
1355 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL
1356 #define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9)
1357 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10)
1358 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10
1359 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL
1360 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL
1361 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10)
1362 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11)
1363 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11
1364 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL
1365 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL
1366 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11)
1367 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12)
1368 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12
1369 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL
1370 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL
1371 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12)
1372 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13)
1373 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13
1374 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL
1375 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL
1376 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13)
1377 #define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14)
1378 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14
1379 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL
1380 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL
1381 #define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14)
1382 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15)
1383 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15
1384 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL
1385 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL
1386 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15)
__IOM uint32_t EM4CTRL
__IOM uint32_t PWRCTRL
__IOM uint32_t DCDCLPVCTRL
__IM uint32_t TEMP
__IOM uint32_t DCDCLNFREQCTRL
__IOM uint32_t IFS
__IOM uint32_t RAM2CTRL
__IOM uint32_t DCDCLNVCTRL
__IOM uint32_t RAM1CTRL
__IOM uint32_t IFC
__IOM uint32_t DCDCCTRL
__IOM uint32_t EM23PERNORETAINCTRL
__IOM uint32_t IEN
__IOM uint32_t VMONAVDDCTRL
__IOM uint32_t DCDCLPEM01CFG
__IOM uint32_t CMD
__IOM uint32_t VMONIO0CTRL
__IOM uint32_t TEMPLIMITS
__IOM uint32_t DCDCLPCTRL
__IOM uint32_t DCDCCLIMCTRL
__IM uint32_t IF
__IOM uint32_t CTRL
__IM uint32_t DCDCSYNC
__IOM uint32_t VMONALTAVDDCTRL
__IOM uint32_t DCDCLNCOMPCTRL
__IOM uint32_t PWRLOCK
__IM uint32_t STATUS
__IOM uint32_t DCDCZDETCTRL
__IOM uint32_t RAM0CTRL
__IOM uint32_t EM23PERNORETAINCMD
__IOM uint32_t LOCK
__IM uint32_t EM23PERNORETAINSTATUS
__IOM uint32_t DCDCMISCCTRL
__IOM uint32_t VMONDVDDCTRL