EFR32 Blue Gecko 13 Software Documentation  efr32bg13-doc-5.1.2
efr32bg13p_devinfo.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IM uint32_t CAL;
44  uint32_t RESERVED0[7];
45  __IM uint32_t EXTINFO;
46  uint32_t RESERVED1[1];
47  __IM uint32_t EUI48L;
48  __IM uint32_t EUI48H;
49  __IM uint32_t CUSTOMINFO;
50  __IM uint32_t MEMINFO;
51  uint32_t RESERVED2[2];
52  __IM uint32_t UNIQUEL;
53  __IM uint32_t UNIQUEH;
54  __IM uint32_t MSIZE;
55  __IM uint32_t PART;
56  __IM uint32_t DEVINFOREV;
57  __IM uint32_t EMUTEMP;
58  uint32_t RESERVED3[2];
59  __IM uint32_t ADC0CAL0;
60  __IM uint32_t ADC0CAL1;
61  __IM uint32_t ADC0CAL2;
62  __IM uint32_t ADC0CAL3;
63  uint32_t RESERVED4[4];
64  __IM uint32_t HFRCOCAL0;
65  uint32_t RESERVED5[2];
66  __IM uint32_t HFRCOCAL3;
67  uint32_t RESERVED6[2];
68  __IM uint32_t HFRCOCAL6;
69  __IM uint32_t HFRCOCAL7;
70  __IM uint32_t HFRCOCAL8;
71  uint32_t RESERVED7[1];
72  __IM uint32_t HFRCOCAL10;
73  __IM uint32_t HFRCOCAL11;
74  __IM uint32_t HFRCOCAL12;
75  uint32_t RESERVED8[11];
76  __IM uint32_t AUXHFRCOCAL0;
77  uint32_t RESERVED9[2];
78  __IM uint32_t AUXHFRCOCAL3;
79  uint32_t RESERVED10[2];
80  __IM uint32_t AUXHFRCOCAL6;
81  __IM uint32_t AUXHFRCOCAL7;
82  __IM uint32_t AUXHFRCOCAL8;
83  uint32_t RESERVED11[1];
84  __IM uint32_t AUXHFRCOCAL10;
85  __IM uint32_t AUXHFRCOCAL11;
86  __IM uint32_t AUXHFRCOCAL12;
87  uint32_t RESERVED12[11];
88  __IM uint32_t VMONCAL0;
89  __IM uint32_t VMONCAL1;
90  __IM uint32_t VMONCAL2;
91  uint32_t RESERVED13[3];
92  __IM uint32_t IDAC0CAL0;
93  __IM uint32_t IDAC0CAL1;
94  uint32_t RESERVED14[2];
95  __IM uint32_t DCDCLNVCTRL0;
96  __IM uint32_t DCDCLPVCTRL0;
97  __IM uint32_t DCDCLPVCTRL1;
98  __IM uint32_t DCDCLPVCTRL2;
99  __IM uint32_t DCDCLPVCTRL3;
100  __IM uint32_t DCDCLPCMPHYSSEL0;
101  __IM uint32_t DCDCLPCMPHYSSEL1;
102  __IM uint32_t VDAC0MAINCAL;
103  __IM uint32_t VDAC0ALTCAL;
104  __IM uint32_t VDAC0CH1CAL;
105  __IM uint32_t OPA0CAL0;
106  __IM uint32_t OPA0CAL1;
107  __IM uint32_t OPA0CAL2;
108  __IM uint32_t OPA0CAL3;
109  __IM uint32_t OPA1CAL0;
110  __IM uint32_t OPA1CAL1;
111  __IM uint32_t OPA1CAL2;
112  __IM uint32_t OPA1CAL3;
113  __IM uint32_t OPA2CAL0;
114  __IM uint32_t OPA2CAL1;
115  __IM uint32_t OPA2CAL2;
116  __IM uint32_t OPA2CAL3;
117  __IM uint32_t CSENGAINCAL;
118  uint32_t RESERVED15[3];
119  __IM uint32_t OPA0CAL4;
120  __IM uint32_t OPA0CAL5;
121  __IM uint32_t OPA0CAL6;
122  __IM uint32_t OPA0CAL7;
123  __IM uint32_t OPA1CAL4;
124  __IM uint32_t OPA1CAL5;
125  __IM uint32_t OPA1CAL6;
126  __IM uint32_t OPA1CAL7;
127  __IM uint32_t OPA2CAL4;
128  __IM uint32_t OPA2CAL5;
129  __IM uint32_t OPA2CAL6;
130  __IM uint32_t OPA2CAL7;
131 } DEVINFO_TypeDef;
133 /**************************************************************************/
138 /* Bit fields for DEVINFO CAL */
139 #define _DEVINFO_CAL_MASK 0x00FFFFFFUL
140 #define _DEVINFO_CAL_CRC_SHIFT 0
141 #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL
142 #define _DEVINFO_CAL_TEMP_SHIFT 16
143 #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL
145 /* Bit fields for DEVINFO EXTINFO */
146 #define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL
147 #define _DEVINFO_EXTINFO_TYPE_SHIFT 0
148 #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL
149 #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL
150 #define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL
151 #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL
152 #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0)
153 #define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0)
154 #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0)
155 #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8
156 #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL
157 #define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL
158 #define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL
159 #define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8)
160 #define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8)
161 #define _DEVINFO_EXTINFO_REV_SHIFT 16
162 #define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL
163 #define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL
164 #define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL
165 #define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16)
166 #define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16)
168 /* Bit fields for DEVINFO EUI48L */
169 #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL
170 #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0
171 #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL
172 #define _DEVINFO_EUI48L_OUI48L_SHIFT 24
173 #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL
175 /* Bit fields for DEVINFO EUI48H */
176 #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL
177 #define _DEVINFO_EUI48H_OUI48H_SHIFT 0
178 #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL
180 /* Bit fields for DEVINFO CUSTOMINFO */
181 #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL
182 #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16
183 #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL
185 /* Bit fields for DEVINFO MEMINFO */
186 #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL
187 #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0
188 #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL
189 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL
190 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL
191 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL
192 #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL
193 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0)
194 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0)
195 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0)
196 #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0)
197 #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8
198 #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL
199 #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL
200 #define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL
201 #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL
202 #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL
203 #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8)
204 #define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8)
205 #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8)
206 #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8)
207 #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16
208 #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL
209 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24
210 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL
212 /* Bit fields for DEVINFO UNIQUEL */
213 #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL
214 #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0
215 #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL
217 /* Bit fields for DEVINFO UNIQUEH */
218 #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL
219 #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0
220 #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL
222 /* Bit fields for DEVINFO MSIZE */
223 #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL
224 #define _DEVINFO_MSIZE_FLASH_SHIFT 0
225 #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL
226 #define _DEVINFO_MSIZE_SRAM_SHIFT 16
227 #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL
229 /* Bit fields for DEVINFO PART */
230 #define _DEVINFO_PART_MASK 0xFFFFFFFFUL
231 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0
232 #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL
233 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16
234 #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL
235 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL
236 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL
237 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL
238 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL
239 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL
240 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL
241 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL
242 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL
243 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL
244 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL
245 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL
246 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL
247 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL
248 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL
249 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL
250 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL
251 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL
252 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL
253 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL
254 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL
255 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL
256 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL
257 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL
258 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL
259 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL
260 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL
261 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL
262 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL
263 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL
264 #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL
265 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL
266 #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL
267 #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL
268 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL
269 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL
270 #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL
271 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL
272 #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL
273 #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL
274 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL
275 #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL
276 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL
277 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL
278 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL
279 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL
280 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL
281 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL
282 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL
283 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL
284 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL
285 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL
286 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16)
287 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16)
288 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16)
289 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16)
290 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16)
291 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16)
292 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16)
293 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16)
294 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16)
295 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16)
296 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16)
297 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16)
298 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16)
299 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16)
300 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16)
301 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16)
302 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16)
303 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16)
304 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16)
305 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16)
306 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16)
307 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16)
308 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16)
309 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16)
310 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16)
311 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16)
312 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16)
313 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16)
314 #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16)
315 #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16)
316 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16)
317 #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16)
318 #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16)
319 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16)
320 #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16)
321 #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16)
322 #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16)
323 #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16)
324 #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16)
325 #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16)
326 #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16)
327 #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16)
328 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16)
329 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16)
330 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16)
331 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16)
332 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16)
333 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16)
334 #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16)
335 #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16)
336 #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16)
337 #define _DEVINFO_PART_PROD_REV_SHIFT 24
338 #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL
340 /* Bit fields for DEVINFO DEVINFOREV */
341 #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL
342 #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0
343 #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL
345 /* Bit fields for DEVINFO EMUTEMP */
346 #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL
347 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0
348 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL
350 /* Bit fields for DEVINFO ADC0CAL0 */
351 #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL
352 #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0
353 #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL
354 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4
355 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL
356 #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8
357 #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL
358 #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16
359 #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL
360 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20
361 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL
362 #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24
363 #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL
365 /* Bit fields for DEVINFO ADC0CAL1 */
366 #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL
367 #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0
368 #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL
369 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4
370 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL
371 #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8
372 #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL
373 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16
374 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL
375 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20
376 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL
377 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24
378 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL
380 /* Bit fields for DEVINFO ADC0CAL2 */
381 #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL
382 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0
383 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL
384 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4
385 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL
387 /* Bit fields for DEVINFO ADC0CAL3 */
388 #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL
389 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4
390 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL
392 /* Bit fields for DEVINFO HFRCOCAL0 */
393 #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL
394 #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0
395 #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL
396 #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8
397 #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL
398 #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16
399 #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL
400 #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21
401 #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL
402 #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24
403 #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL
404 #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25
405 #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL
406 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27
407 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL
408 #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28
409 #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL
411 /* Bit fields for DEVINFO HFRCOCAL3 */
412 #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL
413 #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0
414 #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL
415 #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8
416 #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL
417 #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16
418 #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL
419 #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21
420 #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL
421 #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24
422 #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL
423 #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25
424 #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL
425 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27
426 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL
427 #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28
428 #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL
430 /* Bit fields for DEVINFO HFRCOCAL6 */
431 #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL
432 #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0
433 #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL
434 #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8
435 #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL
436 #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16
437 #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL
438 #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21
439 #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL
440 #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24
441 #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL
442 #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25
443 #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL
444 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27
445 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL
446 #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28
447 #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL
449 /* Bit fields for DEVINFO HFRCOCAL7 */
450 #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL
451 #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0
452 #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL
453 #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8
454 #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL
455 #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16
456 #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL
457 #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21
458 #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL
459 #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24
460 #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL
461 #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25
462 #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL
463 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27
464 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL
465 #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28
466 #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL
468 /* Bit fields for DEVINFO HFRCOCAL8 */
469 #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL
470 #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0
471 #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL
472 #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8
473 #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL
474 #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16
475 #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL
476 #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21
477 #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL
478 #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24
479 #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL
480 #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25
481 #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL
482 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27
483 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL
484 #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28
485 #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL
487 /* Bit fields for DEVINFO HFRCOCAL10 */
488 #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL
489 #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0
490 #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL
491 #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8
492 #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL
493 #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16
494 #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL
495 #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21
496 #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL
497 #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24
498 #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL
499 #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25
500 #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL
501 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27
502 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL
503 #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28
504 #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL
506 /* Bit fields for DEVINFO HFRCOCAL11 */
507 #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL
508 #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0
509 #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL
510 #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8
511 #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL
512 #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16
513 #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL
514 #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21
515 #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL
516 #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24
517 #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL
518 #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25
519 #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL
520 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27
521 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL
522 #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28
523 #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL
525 /* Bit fields for DEVINFO HFRCOCAL12 */
526 #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL
527 #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0
528 #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL
529 #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8
530 #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL
531 #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16
532 #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL
533 #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21
534 #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL
535 #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24
536 #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL
537 #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25
538 #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL
539 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27
540 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL
541 #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28
542 #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL
544 /* Bit fields for DEVINFO AUXHFRCOCAL0 */
545 #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL
546 #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0
547 #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL
548 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8
549 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL
550 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16
551 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL
552 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21
553 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL
554 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24
555 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL
556 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25
557 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL
558 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27
559 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL
560 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28
561 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL
563 /* Bit fields for DEVINFO AUXHFRCOCAL3 */
564 #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL
565 #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0
566 #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL
567 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8
568 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL
569 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16
570 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL
571 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21
572 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL
573 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24
574 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL
575 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25
576 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL
577 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27
578 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL
579 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28
580 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL
582 /* Bit fields for DEVINFO AUXHFRCOCAL6 */
583 #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL
584 #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0
585 #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL
586 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8
587 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL
588 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16
589 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL
590 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21
591 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL
592 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24
593 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL
594 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25
595 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL
596 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27
597 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL
598 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28
599 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL
601 /* Bit fields for DEVINFO AUXHFRCOCAL7 */
602 #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL
603 #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0
604 #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL
605 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8
606 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL
607 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16
608 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL
609 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21
610 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL
611 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24
612 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL
613 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25
614 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL
615 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27
616 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL
617 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28
618 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL
620 /* Bit fields for DEVINFO AUXHFRCOCAL8 */
621 #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL
622 #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0
623 #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL
624 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8
625 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL
626 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16
627 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL
628 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21
629 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL
630 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24
631 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL
632 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25
633 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL
634 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27
635 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL
636 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28
637 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL
639 /* Bit fields for DEVINFO AUXHFRCOCAL10 */
640 #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL
641 #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0
642 #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL
643 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8
644 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL
645 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16
646 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL
647 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21
648 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL
649 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24
650 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL
651 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25
652 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL
653 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27
654 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL
655 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28
656 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL
658 /* Bit fields for DEVINFO AUXHFRCOCAL11 */
659 #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL
660 #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0
661 #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL
662 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8
663 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL
664 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16
665 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL
666 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21
667 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL
668 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24
669 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL
670 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25
671 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL
672 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27
673 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL
674 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28
675 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL
677 /* Bit fields for DEVINFO AUXHFRCOCAL12 */
678 #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL
679 #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0
680 #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL
681 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8
682 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL
683 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16
684 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL
685 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21
686 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL
687 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24
688 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL
689 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25
690 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL
691 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27
692 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL
693 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28
694 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL
696 /* Bit fields for DEVINFO VMONCAL0 */
697 #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL
698 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0
699 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL
700 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4
701 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL
702 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8
703 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL
704 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12
705 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL
706 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16
707 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL
708 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20
709 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL
710 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24
711 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL
712 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28
713 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL
715 /* Bit fields for DEVINFO VMONCAL1 */
716 #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL
717 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0
718 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL
719 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4
720 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL
721 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8
722 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL
723 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12
724 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL
725 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16
726 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL
727 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20
728 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL
729 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24
730 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL
731 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28
732 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL
734 /* Bit fields for DEVINFO VMONCAL2 */
735 #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL
736 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0
737 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL
738 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4
739 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL
740 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8
741 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL
742 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12
743 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL
744 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16
745 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL
746 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20
747 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL
748 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24
749 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL
750 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28
751 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL
753 /* Bit fields for DEVINFO IDAC0CAL0 */
754 #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL
755 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0
756 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL
757 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8
758 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL
759 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16
760 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL
761 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24
762 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL
764 /* Bit fields for DEVINFO IDAC0CAL1 */
765 #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL
766 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0
767 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL
768 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8
769 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL
770 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16
771 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL
772 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24
773 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL
775 /* Bit fields for DEVINFO DCDCLNVCTRL0 */
776 #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL
777 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0
778 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL
779 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8
780 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL
781 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16
782 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL
783 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24
784 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL
786 /* Bit fields for DEVINFO DCDCLPVCTRL0 */
787 #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL
788 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0
789 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL
790 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8
791 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL
792 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16
793 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL
794 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24
795 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL
797 /* Bit fields for DEVINFO DCDCLPVCTRL1 */
798 #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL
799 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0
800 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL
801 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8
802 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL
803 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16
804 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL
805 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24
806 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL
808 /* Bit fields for DEVINFO DCDCLPVCTRL2 */
809 #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL
810 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0
811 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL
812 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8
813 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL
814 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16
815 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL
816 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24
817 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL
819 /* Bit fields for DEVINFO DCDCLPVCTRL3 */
820 #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL
821 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0
822 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL
823 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8
824 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL
825 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16
826 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL
827 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24
828 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL
830 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */
831 #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL
832 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0
833 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL
834 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8
835 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL
837 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */
838 #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL
839 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0
840 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL
841 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8
842 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL
843 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16
844 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL
845 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24
846 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL
848 /* Bit fields for DEVINFO VDAC0MAINCAL */
849 #define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL
850 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0
851 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL
852 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6
853 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL
854 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12
855 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL
856 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18
857 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL
858 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24
859 #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL
861 /* Bit fields for DEVINFO VDAC0ALTCAL */
862 #define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL
863 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0
864 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL
865 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6
866 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL
867 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12
868 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL
869 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18
870 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL
871 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24
872 #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL
874 /* Bit fields for DEVINFO VDAC0CH1CAL */
875 #define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL
876 #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0
877 #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL
878 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4
879 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL
880 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8
881 #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL
883 /* Bit fields for DEVINFO OPA0CAL0 */
884 #define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL
885 #define _DEVINFO_OPA0CAL0_CM1_SHIFT 0
886 #define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL
887 #define _DEVINFO_OPA0CAL0_CM2_SHIFT 5
888 #define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL
889 #define _DEVINFO_OPA0CAL0_CM3_SHIFT 10
890 #define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL
891 #define _DEVINFO_OPA0CAL0_GM_SHIFT 13
892 #define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL
893 #define _DEVINFO_OPA0CAL0_GM3_SHIFT 17
894 #define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL
895 #define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20
896 #define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL
897 #define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26
898 #define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL
900 /* Bit fields for DEVINFO OPA0CAL1 */
901 #define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL
902 #define _DEVINFO_OPA0CAL1_CM1_SHIFT 0
903 #define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL
904 #define _DEVINFO_OPA0CAL1_CM2_SHIFT 5
905 #define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL
906 #define _DEVINFO_OPA0CAL1_CM3_SHIFT 10
907 #define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL
908 #define _DEVINFO_OPA0CAL1_GM_SHIFT 13
909 #define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL
910 #define _DEVINFO_OPA0CAL1_GM3_SHIFT 17
911 #define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL
912 #define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20
913 #define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL
914 #define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26
915 #define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL
917 /* Bit fields for DEVINFO OPA0CAL2 */
918 #define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL
919 #define _DEVINFO_OPA0CAL2_CM1_SHIFT 0
920 #define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL
921 #define _DEVINFO_OPA0CAL2_CM2_SHIFT 5
922 #define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL
923 #define _DEVINFO_OPA0CAL2_CM3_SHIFT 10
924 #define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL
925 #define _DEVINFO_OPA0CAL2_GM_SHIFT 13
926 #define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL
927 #define _DEVINFO_OPA0CAL2_GM3_SHIFT 17
928 #define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL
929 #define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20
930 #define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL
931 #define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26
932 #define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL
934 /* Bit fields for DEVINFO OPA0CAL3 */
935 #define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL
936 #define _DEVINFO_OPA0CAL3_CM1_SHIFT 0
937 #define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL
938 #define _DEVINFO_OPA0CAL3_CM2_SHIFT 5
939 #define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL
940 #define _DEVINFO_OPA0CAL3_CM3_SHIFT 10
941 #define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL
942 #define _DEVINFO_OPA0CAL3_GM_SHIFT 13
943 #define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL
944 #define _DEVINFO_OPA0CAL3_GM3_SHIFT 17
945 #define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL
946 #define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20
947 #define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL
948 #define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26
949 #define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL
951 /* Bit fields for DEVINFO OPA1CAL0 */
952 #define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL
953 #define _DEVINFO_OPA1CAL0_CM1_SHIFT 0
954 #define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL
955 #define _DEVINFO_OPA1CAL0_CM2_SHIFT 5
956 #define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL
957 #define _DEVINFO_OPA1CAL0_CM3_SHIFT 10
958 #define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL
959 #define _DEVINFO_OPA1CAL0_GM_SHIFT 13
960 #define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL
961 #define _DEVINFO_OPA1CAL0_GM3_SHIFT 17
962 #define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL
963 #define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20
964 #define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL
965 #define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26
966 #define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL
968 /* Bit fields for DEVINFO OPA1CAL1 */
969 #define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL
970 #define _DEVINFO_OPA1CAL1_CM1_SHIFT 0
971 #define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL
972 #define _DEVINFO_OPA1CAL1_CM2_SHIFT 5
973 #define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL
974 #define _DEVINFO_OPA1CAL1_CM3_SHIFT 10
975 #define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL
976 #define _DEVINFO_OPA1CAL1_GM_SHIFT 13
977 #define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL
978 #define _DEVINFO_OPA1CAL1_GM3_SHIFT 17
979 #define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL
980 #define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20
981 #define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL
982 #define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26
983 #define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL
985 /* Bit fields for DEVINFO OPA1CAL2 */
986 #define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL
987 #define _DEVINFO_OPA1CAL2_CM1_SHIFT 0
988 #define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL
989 #define _DEVINFO_OPA1CAL2_CM2_SHIFT 5
990 #define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL
991 #define _DEVINFO_OPA1CAL2_CM3_SHIFT 10
992 #define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL
993 #define _DEVINFO_OPA1CAL2_GM_SHIFT 13
994 #define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL
995 #define _DEVINFO_OPA1CAL2_GM3_SHIFT 17
996 #define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL
997 #define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20
998 #define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL
999 #define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26
1000 #define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL
1002 /* Bit fields for DEVINFO OPA1CAL3 */
1003 #define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL
1004 #define _DEVINFO_OPA1CAL3_CM1_SHIFT 0
1005 #define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL
1006 #define _DEVINFO_OPA1CAL3_CM2_SHIFT 5
1007 #define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL
1008 #define _DEVINFO_OPA1CAL3_CM3_SHIFT 10
1009 #define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL
1010 #define _DEVINFO_OPA1CAL3_GM_SHIFT 13
1011 #define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL
1012 #define _DEVINFO_OPA1CAL3_GM3_SHIFT 17
1013 #define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL
1014 #define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20
1015 #define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL
1016 #define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26
1017 #define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL
1019 /* Bit fields for DEVINFO OPA2CAL0 */
1020 #define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL
1021 #define _DEVINFO_OPA2CAL0_CM1_SHIFT 0
1022 #define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL
1023 #define _DEVINFO_OPA2CAL0_CM2_SHIFT 5
1024 #define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL
1025 #define _DEVINFO_OPA2CAL0_CM3_SHIFT 10
1026 #define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL
1027 #define _DEVINFO_OPA2CAL0_GM_SHIFT 13
1028 #define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL
1029 #define _DEVINFO_OPA2CAL0_GM3_SHIFT 17
1030 #define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL
1031 #define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20
1032 #define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL
1033 #define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26
1034 #define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL
1036 /* Bit fields for DEVINFO OPA2CAL1 */
1037 #define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL
1038 #define _DEVINFO_OPA2CAL1_CM1_SHIFT 0
1039 #define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL
1040 #define _DEVINFO_OPA2CAL1_CM2_SHIFT 5
1041 #define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL
1042 #define _DEVINFO_OPA2CAL1_CM3_SHIFT 10
1043 #define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL
1044 #define _DEVINFO_OPA2CAL1_GM_SHIFT 13
1045 #define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL
1046 #define _DEVINFO_OPA2CAL1_GM3_SHIFT 17
1047 #define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL
1048 #define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20
1049 #define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL
1050 #define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26
1051 #define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL
1053 /* Bit fields for DEVINFO OPA2CAL2 */
1054 #define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL
1055 #define _DEVINFO_OPA2CAL2_CM1_SHIFT 0
1056 #define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL
1057 #define _DEVINFO_OPA2CAL2_CM2_SHIFT 5
1058 #define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL
1059 #define _DEVINFO_OPA2CAL2_CM3_SHIFT 10
1060 #define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL
1061 #define _DEVINFO_OPA2CAL2_GM_SHIFT 13
1062 #define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL
1063 #define _DEVINFO_OPA2CAL2_GM3_SHIFT 17
1064 #define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL
1065 #define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20
1066 #define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL
1067 #define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26
1068 #define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL
1070 /* Bit fields for DEVINFO OPA2CAL3 */
1071 #define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL
1072 #define _DEVINFO_OPA2CAL3_CM1_SHIFT 0
1073 #define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL
1074 #define _DEVINFO_OPA2CAL3_CM2_SHIFT 5
1075 #define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL
1076 #define _DEVINFO_OPA2CAL3_CM3_SHIFT 10
1077 #define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL
1078 #define _DEVINFO_OPA2CAL3_GM_SHIFT 13
1079 #define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL
1080 #define _DEVINFO_OPA2CAL3_GM3_SHIFT 17
1081 #define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL
1082 #define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20
1083 #define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL
1084 #define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26
1085 #define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL
1087 /* Bit fields for DEVINFO CSENGAINCAL */
1088 #define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL
1089 #define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0
1090 #define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL
1092 /* Bit fields for DEVINFO OPA0CAL4 */
1093 #define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL
1094 #define _DEVINFO_OPA0CAL4_CM1_SHIFT 0
1095 #define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL
1096 #define _DEVINFO_OPA0CAL4_CM2_SHIFT 5
1097 #define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL
1098 #define _DEVINFO_OPA0CAL4_CM3_SHIFT 10
1099 #define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL
1100 #define _DEVINFO_OPA0CAL4_GM_SHIFT 13
1101 #define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL
1102 #define _DEVINFO_OPA0CAL4_GM3_SHIFT 17
1103 #define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL
1104 #define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20
1105 #define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL
1106 #define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26
1107 #define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL
1109 /* Bit fields for DEVINFO OPA0CAL5 */
1110 #define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL
1111 #define _DEVINFO_OPA0CAL5_CM1_SHIFT 0
1112 #define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL
1113 #define _DEVINFO_OPA0CAL5_CM2_SHIFT 5
1114 #define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL
1115 #define _DEVINFO_OPA0CAL5_CM3_SHIFT 10
1116 #define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL
1117 #define _DEVINFO_OPA0CAL5_GM_SHIFT 13
1118 #define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL
1119 #define _DEVINFO_OPA0CAL5_GM3_SHIFT 17
1120 #define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL
1121 #define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20
1122 #define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL
1123 #define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26
1124 #define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL
1126 /* Bit fields for DEVINFO OPA0CAL6 */
1127 #define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL
1128 #define _DEVINFO_OPA0CAL6_CM1_SHIFT 0
1129 #define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL
1130 #define _DEVINFO_OPA0CAL6_CM2_SHIFT 5
1131 #define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL
1132 #define _DEVINFO_OPA0CAL6_CM3_SHIFT 10
1133 #define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL
1134 #define _DEVINFO_OPA0CAL6_GM_SHIFT 13
1135 #define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL
1136 #define _DEVINFO_OPA0CAL6_GM3_SHIFT 17
1137 #define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL
1138 #define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20
1139 #define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL
1140 #define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26
1141 #define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL
1143 /* Bit fields for DEVINFO OPA0CAL7 */
1144 #define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL
1145 #define _DEVINFO_OPA0CAL7_CM1_SHIFT 0
1146 #define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL
1147 #define _DEVINFO_OPA0CAL7_CM2_SHIFT 5
1148 #define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL
1149 #define _DEVINFO_OPA0CAL7_CM3_SHIFT 10
1150 #define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL
1151 #define _DEVINFO_OPA0CAL7_GM_SHIFT 13
1152 #define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL
1153 #define _DEVINFO_OPA0CAL7_GM3_SHIFT 17
1154 #define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL
1155 #define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20
1156 #define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL
1157 #define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26
1158 #define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL
1160 /* Bit fields for DEVINFO OPA1CAL4 */
1161 #define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL
1162 #define _DEVINFO_OPA1CAL4_CM1_SHIFT 0
1163 #define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL
1164 #define _DEVINFO_OPA1CAL4_CM2_SHIFT 5
1165 #define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL
1166 #define _DEVINFO_OPA1CAL4_CM3_SHIFT 10
1167 #define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL
1168 #define _DEVINFO_OPA1CAL4_GM_SHIFT 13
1169 #define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL
1170 #define _DEVINFO_OPA1CAL4_GM3_SHIFT 17
1171 #define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL
1172 #define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20
1173 #define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL
1174 #define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26
1175 #define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL
1177 /* Bit fields for DEVINFO OPA1CAL5 */
1178 #define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL
1179 #define _DEVINFO_OPA1CAL5_CM1_SHIFT 0
1180 #define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL
1181 #define _DEVINFO_OPA1CAL5_CM2_SHIFT 5
1182 #define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL
1183 #define _DEVINFO_OPA1CAL5_CM3_SHIFT 10
1184 #define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL
1185 #define _DEVINFO_OPA1CAL5_GM_SHIFT 13
1186 #define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL
1187 #define _DEVINFO_OPA1CAL5_GM3_SHIFT 17
1188 #define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL
1189 #define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20
1190 #define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL
1191 #define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26
1192 #define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL
1194 /* Bit fields for DEVINFO OPA1CAL6 */
1195 #define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL
1196 #define _DEVINFO_OPA1CAL6_CM1_SHIFT 0
1197 #define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL
1198 #define _DEVINFO_OPA1CAL6_CM2_SHIFT 5
1199 #define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL
1200 #define _DEVINFO_OPA1CAL6_CM3_SHIFT 10
1201 #define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL
1202 #define _DEVINFO_OPA1CAL6_GM_SHIFT 13
1203 #define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL
1204 #define _DEVINFO_OPA1CAL6_GM3_SHIFT 17
1205 #define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL
1206 #define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20
1207 #define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL
1208 #define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26
1209 #define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL
1211 /* Bit fields for DEVINFO OPA1CAL7 */
1212 #define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL
1213 #define _DEVINFO_OPA1CAL7_CM1_SHIFT 0
1214 #define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL
1215 #define _DEVINFO_OPA1CAL7_CM2_SHIFT 5
1216 #define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL
1217 #define _DEVINFO_OPA1CAL7_CM3_SHIFT 10
1218 #define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL
1219 #define _DEVINFO_OPA1CAL7_GM_SHIFT 13
1220 #define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL
1221 #define _DEVINFO_OPA1CAL7_GM3_SHIFT 17
1222 #define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL
1223 #define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20
1224 #define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL
1225 #define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26
1226 #define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL
1228 /* Bit fields for DEVINFO OPA2CAL4 */
1229 #define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL
1230 #define _DEVINFO_OPA2CAL4_CM1_SHIFT 0
1231 #define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL
1232 #define _DEVINFO_OPA2CAL4_CM2_SHIFT 5
1233 #define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL
1234 #define _DEVINFO_OPA2CAL4_CM3_SHIFT 10
1235 #define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL
1236 #define _DEVINFO_OPA2CAL4_GM_SHIFT 13
1237 #define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL
1238 #define _DEVINFO_OPA2CAL4_GM3_SHIFT 17
1239 #define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL
1240 #define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20
1241 #define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL
1242 #define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26
1243 #define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL
1245 /* Bit fields for DEVINFO OPA2CAL5 */
1246 #define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL
1247 #define _DEVINFO_OPA2CAL5_CM1_SHIFT 0
1248 #define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL
1249 #define _DEVINFO_OPA2CAL5_CM2_SHIFT 5
1250 #define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL
1251 #define _DEVINFO_OPA2CAL5_CM3_SHIFT 10
1252 #define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL
1253 #define _DEVINFO_OPA2CAL5_GM_SHIFT 13
1254 #define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL
1255 #define _DEVINFO_OPA2CAL5_GM3_SHIFT 17
1256 #define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL
1257 #define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20
1258 #define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL
1259 #define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26
1260 #define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL
1262 /* Bit fields for DEVINFO OPA2CAL6 */
1263 #define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL
1264 #define _DEVINFO_OPA2CAL6_CM1_SHIFT 0
1265 #define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL
1266 #define _DEVINFO_OPA2CAL6_CM2_SHIFT 5
1267 #define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL
1268 #define _DEVINFO_OPA2CAL6_CM3_SHIFT 10
1269 #define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL
1270 #define _DEVINFO_OPA2CAL6_GM_SHIFT 13
1271 #define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL
1272 #define _DEVINFO_OPA2CAL6_GM3_SHIFT 17
1273 #define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL
1274 #define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20
1275 #define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL
1276 #define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26
1277 #define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL
1279 /* Bit fields for DEVINFO OPA2CAL7 */
1280 #define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL
1281 #define _DEVINFO_OPA2CAL7_CM1_SHIFT 0
1282 #define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL
1283 #define _DEVINFO_OPA2CAL7_CM2_SHIFT 5
1284 #define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL
1285 #define _DEVINFO_OPA2CAL7_CM3_SHIFT 10
1286 #define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL
1287 #define _DEVINFO_OPA2CAL7_GM_SHIFT 13
1288 #define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL
1289 #define _DEVINFO_OPA2CAL7_GM3_SHIFT 17
1290 #define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL
1291 #define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20
1292 #define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL
1293 #define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26
1294 #define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL
__IM uint32_t UNIQUEH
__IM uint32_t HFRCOCAL12
__IM uint32_t OPA0CAL0
__IM uint32_t DCDCLPVCTRL1
__IM uint32_t EUI48L
__IM uint32_t AUXHFRCOCAL11
__IM uint32_t OPA0CAL1
__IM uint32_t OPA2CAL4
__IM uint32_t AUXHFRCOCAL8
__IM uint32_t EUI48H
__IM uint32_t VMONCAL1
__IM uint32_t OPA0CAL5
__IM uint32_t OPA1CAL2
__IM uint32_t HFRCOCAL10
__IM uint32_t AUXHFRCOCAL6
__IM uint32_t DCDCLPVCTRL2
__IM uint32_t CSENGAINCAL
__IM uint32_t DCDCLPCMPHYSSEL0
__IM uint32_t DCDCLPCMPHYSSEL1
__IM uint32_t OPA2CAL3
__IM uint32_t OPA2CAL0
__IM uint32_t IDAC0CAL1
__IM uint32_t EMUTEMP
__IM uint32_t HFRCOCAL3
__IM uint32_t AUXHFRCOCAL0
__IM uint32_t DCDCLPVCTRL3
__IM uint32_t AUXHFRCOCAL7
__IM uint32_t AUXHFRCOCAL10
__IM uint32_t ADC0CAL3
__IM uint32_t CUSTOMINFO
__IM uint32_t HFRCOCAL7
__IM uint32_t OPA0CAL6
__IM uint32_t VDAC0ALTCAL
__IM uint32_t AUXHFRCOCAL3
__IM uint32_t VMONCAL0
__IM uint32_t MSIZE
__IM uint32_t OPA0CAL3
__IM uint32_t DCDCLNVCTRL0
__IM uint32_t OPA1CAL0
__IM uint32_t VDAC0CH1CAL
__IM uint32_t VDAC0MAINCAL
__IM uint32_t ADC0CAL0
__IM uint32_t OPA0CAL4
__IM uint32_t OPA2CAL7
__IM uint32_t OPA2CAL5
__IM uint32_t OPA1CAL3
__IM uint32_t OPA1CAL6
__IM uint32_t HFRCOCAL6
__IM uint32_t OPA1CAL5
__IM uint32_t OPA0CAL7
__IM uint32_t MEMINFO
__IM uint32_t OPA2CAL2
__IM uint32_t OPA0CAL2
__IM uint32_t IDAC0CAL0
__IM uint32_t OPA1CAL1
__IM uint32_t HFRCOCAL11
__IM uint32_t EXTINFO
__IM uint32_t ADC0CAL1
__IM uint32_t DEVINFOREV
__IM uint32_t VMONCAL2
__IM uint32_t PART
__IM uint32_t HFRCOCAL8
__IM uint32_t AUXHFRCOCAL12
__IM uint32_t UNIQUEL
__IM uint32_t OPA2CAL1
__IM uint32_t CAL
__IM uint32_t ADC0CAL2
__IM uint32_t OPA1CAL7
__IM uint32_t OPA2CAL6
__IM uint32_t OPA1CAL4
__IM uint32_t HFRCOCAL0
__IM uint32_t DCDCLPVCTRL0