EFR32 Blue Gecko 13 Software Documentation  efr32bg13-doc-5.1.2
efr32bg13p_cmu.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
45  uint32_t RESERVED0[3];
46  __IOM uint32_t HFRCOCTRL;
48  uint32_t RESERVED1[1];
49  __IOM uint32_t AUXHFRCOCTRL;
51  uint32_t RESERVED2[1];
52  __IOM uint32_t LFRCOCTRL;
53  __IOM uint32_t HFXOCTRL;
55  uint32_t RESERVED3[1];
56  __IOM uint32_t HFXOSTARTUPCTRL;
57  __IOM uint32_t HFXOSTEADYSTATECTRL;
58  __IOM uint32_t HFXOTIMEOUTCTRL;
59  __IOM uint32_t LFXOCTRL;
61  uint32_t RESERVED4[1];
62  __IOM uint32_t DPLLCTRL;
63  __IOM uint32_t DPLLCTRL1;
64  uint32_t RESERVED5[2];
65  __IOM uint32_t CALCTRL;
66  __IOM uint32_t CALCNT;
67  uint32_t RESERVED6[2];
68  __IOM uint32_t OSCENCMD;
69  __IOM uint32_t CMD;
70  uint32_t RESERVED7[2];
71  __IOM uint32_t DBGCLKSEL;
72  __IOM uint32_t HFCLKSEL;
73  uint32_t RESERVED8[2];
74  __IOM uint32_t LFACLKSEL;
75  __IOM uint32_t LFBCLKSEL;
76  __IOM uint32_t LFECLKSEL;
78  uint32_t RESERVED9[1];
79  __IM uint32_t STATUS;
80  __IM uint32_t HFCLKSTATUS;
81  uint32_t RESERVED10[1];
82  __IM uint32_t HFXOTRIMSTATUS;
83  __IM uint32_t IF;
84  __IOM uint32_t IFS;
85  __IOM uint32_t IFC;
86  __IOM uint32_t IEN;
87  __IOM uint32_t HFBUSCLKEN0;
89  uint32_t RESERVED11[3];
90  __IOM uint32_t HFPERCLKEN0;
92  uint32_t RESERVED12[7];
93  __IOM uint32_t LFACLKEN0;
94  uint32_t RESERVED13[1];
95  __IOM uint32_t LFBCLKEN0;
97  uint32_t RESERVED14[1];
98  __IOM uint32_t LFECLKEN0;
99  uint32_t RESERVED15[3];
100  __IOM uint32_t HFPRESC;
102  uint32_t RESERVED16[1];
103  __IOM uint32_t HFCOREPRESC;
104  __IOM uint32_t HFPERPRESC;
106  uint32_t RESERVED17[1];
107  __IOM uint32_t HFEXPPRESC;
109  uint32_t RESERVED18[2];
110  __IOM uint32_t LFAPRESC0;
111  uint32_t RESERVED19[1];
112  __IOM uint32_t LFBPRESC0;
113  uint32_t RESERVED20[1];
114  __IOM uint32_t LFEPRESC0;
116  uint32_t RESERVED21[3];
117  __IM uint32_t SYNCBUSY;
118  __IOM uint32_t FREEZE;
119  uint32_t RESERVED22[2];
120  __IOM uint32_t PCNTCTRL;
122  uint32_t RESERVED23[2];
123  __IOM uint32_t ADCCTRL;
125  uint32_t RESERVED24[4];
126  __IOM uint32_t ROUTEPEN;
127  __IOM uint32_t ROUTELOC0;
128  __IOM uint32_t ROUTELOC1;
129  uint32_t RESERVED25[1];
130  __IOM uint32_t LOCK;
131  __IOM uint32_t HFRCOSS;
132 } CMU_TypeDef;
134 /**************************************************************************/
139 /* Bit fields for CMU CTRL */
140 #define _CMU_CTRL_RESETVALUE 0x00300000UL
141 #define _CMU_CTRL_MASK 0x001103FFUL
142 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 0
143 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x1FUL
144 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
145 #define _CMU_CTRL_CLKOUTSEL0_DISABLED 0x00000000UL
146 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000001UL
147 #define _CMU_CTRL_CLKOUTSEL0_LFRCO 0x00000002UL
148 #define _CMU_CTRL_CLKOUTSEL0_LFXO 0x00000003UL
149 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000006UL
150 #define _CMU_CTRL_CLKOUTSEL0_HFEXPCLK 0x00000007UL
151 #define _CMU_CTRL_CLKOUTSEL0_ULFRCOQ 0x00000009UL
152 #define _CMU_CTRL_CLKOUTSEL0_LFRCOQ 0x0000000AUL
153 #define _CMU_CTRL_CLKOUTSEL0_LFXOQ 0x0000000BUL
154 #define _CMU_CTRL_CLKOUTSEL0_HFRCOQ 0x0000000CUL
155 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ 0x0000000DUL
156 #define _CMU_CTRL_CLKOUTSEL0_HFXOQ 0x0000000EUL
157 #define _CMU_CTRL_CLKOUTSEL0_HFSRCCLK 0x0000000FUL
158 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 0)
159 #define CMU_CTRL_CLKOUTSEL0_DISABLED (_CMU_CTRL_CLKOUTSEL0_DISABLED << 0)
160 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 0)
161 #define CMU_CTRL_CLKOUTSEL0_LFRCO (_CMU_CTRL_CLKOUTSEL0_LFRCO << 0)
162 #define CMU_CTRL_CLKOUTSEL0_LFXO (_CMU_CTRL_CLKOUTSEL0_LFXO << 0)
163 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 0)
164 #define CMU_CTRL_CLKOUTSEL0_HFEXPCLK (_CMU_CTRL_CLKOUTSEL0_HFEXPCLK << 0)
165 #define CMU_CTRL_CLKOUTSEL0_ULFRCOQ (_CMU_CTRL_CLKOUTSEL0_ULFRCOQ << 0)
166 #define CMU_CTRL_CLKOUTSEL0_LFRCOQ (_CMU_CTRL_CLKOUTSEL0_LFRCOQ << 0)
167 #define CMU_CTRL_CLKOUTSEL0_LFXOQ (_CMU_CTRL_CLKOUTSEL0_LFXOQ << 0)
168 #define CMU_CTRL_CLKOUTSEL0_HFRCOQ (_CMU_CTRL_CLKOUTSEL0_HFRCOQ << 0)
169 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ << 0)
170 #define CMU_CTRL_CLKOUTSEL0_HFXOQ (_CMU_CTRL_CLKOUTSEL0_HFXOQ << 0)
171 #define CMU_CTRL_CLKOUTSEL0_HFSRCCLK (_CMU_CTRL_CLKOUTSEL0_HFSRCCLK << 0)
172 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 5
173 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3E0UL
174 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
175 #define _CMU_CTRL_CLKOUTSEL1_DISABLED 0x00000000UL
176 #define _CMU_CTRL_CLKOUTSEL1_ULFRCO 0x00000001UL
177 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000002UL
178 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000003UL
179 #define _CMU_CTRL_CLKOUTSEL1_HFXO 0x00000006UL
180 #define _CMU_CTRL_CLKOUTSEL1_HFEXPCLK 0x00000007UL
181 #define _CMU_CTRL_CLKOUTSEL1_ULFRCOQ 0x00000009UL
182 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x0000000AUL
183 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x0000000BUL
184 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x0000000CUL
185 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x0000000DUL
186 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x0000000EUL
187 #define _CMU_CTRL_CLKOUTSEL1_HFSRCCLK 0x0000000FUL
188 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 5)
189 #define CMU_CTRL_CLKOUTSEL1_DISABLED (_CMU_CTRL_CLKOUTSEL1_DISABLED << 5)
190 #define CMU_CTRL_CLKOUTSEL1_ULFRCO (_CMU_CTRL_CLKOUTSEL1_ULFRCO << 5)
191 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 5)
192 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 5)
193 #define CMU_CTRL_CLKOUTSEL1_HFXO (_CMU_CTRL_CLKOUTSEL1_HFXO << 5)
194 #define CMU_CTRL_CLKOUTSEL1_HFEXPCLK (_CMU_CTRL_CLKOUTSEL1_HFEXPCLK << 5)
195 #define CMU_CTRL_CLKOUTSEL1_ULFRCOQ (_CMU_CTRL_CLKOUTSEL1_ULFRCOQ << 5)
196 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 5)
197 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 5)
198 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 5)
199 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 5)
200 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 5)
201 #define CMU_CTRL_CLKOUTSEL1_HFSRCCLK (_CMU_CTRL_CLKOUTSEL1_HFSRCCLK << 5)
202 #define CMU_CTRL_WSHFLE (0x1UL << 16)
203 #define _CMU_CTRL_WSHFLE_SHIFT 16
204 #define _CMU_CTRL_WSHFLE_MASK 0x10000UL
205 #define _CMU_CTRL_WSHFLE_DEFAULT 0x00000000UL
206 #define CMU_CTRL_WSHFLE_DEFAULT (_CMU_CTRL_WSHFLE_DEFAULT << 16)
207 #define CMU_CTRL_HFPERCLKEN (0x1UL << 20)
208 #define _CMU_CTRL_HFPERCLKEN_SHIFT 20
209 #define _CMU_CTRL_HFPERCLKEN_MASK 0x100000UL
210 #define _CMU_CTRL_HFPERCLKEN_DEFAULT 0x00000001UL
211 #define CMU_CTRL_HFPERCLKEN_DEFAULT (_CMU_CTRL_HFPERCLKEN_DEFAULT << 20)
213 /* Bit fields for CMU HFRCOCTRL */
214 #define _CMU_HFRCOCTRL_RESETVALUE 0xB1481F7FUL
215 #define _CMU_HFRCOCTRL_MASK 0xFFFF3F7FUL
216 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
217 #define _CMU_HFRCOCTRL_TUNING_MASK 0x7FUL
218 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x0000007FUL
219 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
220 #define _CMU_HFRCOCTRL_FINETUNING_SHIFT 8
221 #define _CMU_HFRCOCTRL_FINETUNING_MASK 0x3F00UL
222 #define _CMU_HFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL
223 #define CMU_HFRCOCTRL_FINETUNING_DEFAULT (_CMU_HFRCOCTRL_FINETUNING_DEFAULT << 8)
224 #define _CMU_HFRCOCTRL_FREQRANGE_SHIFT 16
225 #define _CMU_HFRCOCTRL_FREQRANGE_MASK 0x1F0000UL
226 #define _CMU_HFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL
227 #define CMU_HFRCOCTRL_FREQRANGE_DEFAULT (_CMU_HFRCOCTRL_FREQRANGE_DEFAULT << 16)
228 #define _CMU_HFRCOCTRL_CMPBIAS_SHIFT 21
229 #define _CMU_HFRCOCTRL_CMPBIAS_MASK 0xE00000UL
230 #define _CMU_HFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL
231 #define CMU_HFRCOCTRL_CMPBIAS_DEFAULT (_CMU_HFRCOCTRL_CMPBIAS_DEFAULT << 21)
232 #define CMU_HFRCOCTRL_LDOHP (0x1UL << 24)
233 #define _CMU_HFRCOCTRL_LDOHP_SHIFT 24
234 #define _CMU_HFRCOCTRL_LDOHP_MASK 0x1000000UL
235 #define _CMU_HFRCOCTRL_LDOHP_DEFAULT 0x00000001UL
236 #define CMU_HFRCOCTRL_LDOHP_DEFAULT (_CMU_HFRCOCTRL_LDOHP_DEFAULT << 24)
237 #define _CMU_HFRCOCTRL_CLKDIV_SHIFT 25
238 #define _CMU_HFRCOCTRL_CLKDIV_MASK 0x6000000UL
239 #define _CMU_HFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL
240 #define _CMU_HFRCOCTRL_CLKDIV_DIV1 0x00000000UL
241 #define _CMU_HFRCOCTRL_CLKDIV_DIV2 0x00000001UL
242 #define _CMU_HFRCOCTRL_CLKDIV_DIV4 0x00000002UL
243 #define CMU_HFRCOCTRL_CLKDIV_DEFAULT (_CMU_HFRCOCTRL_CLKDIV_DEFAULT << 25)
244 #define CMU_HFRCOCTRL_CLKDIV_DIV1 (_CMU_HFRCOCTRL_CLKDIV_DIV1 << 25)
245 #define CMU_HFRCOCTRL_CLKDIV_DIV2 (_CMU_HFRCOCTRL_CLKDIV_DIV2 << 25)
246 #define CMU_HFRCOCTRL_CLKDIV_DIV4 (_CMU_HFRCOCTRL_CLKDIV_DIV4 << 25)
247 #define CMU_HFRCOCTRL_FINETUNINGEN (0x1UL << 27)
248 #define _CMU_HFRCOCTRL_FINETUNINGEN_SHIFT 27
249 #define _CMU_HFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL
250 #define _CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL
251 #define CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_HFRCOCTRL_FINETUNINGEN_DEFAULT << 27)
252 #define _CMU_HFRCOCTRL_VREFTC_SHIFT 28
253 #define _CMU_HFRCOCTRL_VREFTC_MASK 0xF0000000UL
254 #define _CMU_HFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL
255 #define CMU_HFRCOCTRL_VREFTC_DEFAULT (_CMU_HFRCOCTRL_VREFTC_DEFAULT << 28)
257 /* Bit fields for CMU AUXHFRCOCTRL */
258 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0xB1481F7FUL
259 #define _CMU_AUXHFRCOCTRL_MASK 0xFFFF3F7FUL
260 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
261 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0x7FUL
262 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x0000007FUL
263 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
264 #define _CMU_AUXHFRCOCTRL_FINETUNING_SHIFT 8
265 #define _CMU_AUXHFRCOCTRL_FINETUNING_MASK 0x3F00UL
266 #define _CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT 0x0000001FUL
267 #define CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNING_DEFAULT << 8)
268 #define _CMU_AUXHFRCOCTRL_FREQRANGE_SHIFT 16
269 #define _CMU_AUXHFRCOCTRL_FREQRANGE_MASK 0x1F0000UL
270 #define _CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT 0x00000008UL
271 #define CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT (_CMU_AUXHFRCOCTRL_FREQRANGE_DEFAULT << 16)
272 #define _CMU_AUXHFRCOCTRL_CMPBIAS_SHIFT 21
273 #define _CMU_AUXHFRCOCTRL_CMPBIAS_MASK 0xE00000UL
274 #define _CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT 0x00000002UL
275 #define CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT (_CMU_AUXHFRCOCTRL_CMPBIAS_DEFAULT << 21)
276 #define CMU_AUXHFRCOCTRL_LDOHP (0x1UL << 24)
277 #define _CMU_AUXHFRCOCTRL_LDOHP_SHIFT 24
278 #define _CMU_AUXHFRCOCTRL_LDOHP_MASK 0x1000000UL
279 #define _CMU_AUXHFRCOCTRL_LDOHP_DEFAULT 0x00000001UL
280 #define CMU_AUXHFRCOCTRL_LDOHP_DEFAULT (_CMU_AUXHFRCOCTRL_LDOHP_DEFAULT << 24)
281 #define _CMU_AUXHFRCOCTRL_CLKDIV_SHIFT 25
282 #define _CMU_AUXHFRCOCTRL_CLKDIV_MASK 0x6000000UL
283 #define _CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT 0x00000000UL
284 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV1 0x00000000UL
285 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV2 0x00000001UL
286 #define _CMU_AUXHFRCOCTRL_CLKDIV_DIV4 0x00000002UL
287 #define CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT (_CMU_AUXHFRCOCTRL_CLKDIV_DEFAULT << 25)
288 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV1 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV1 << 25)
289 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV2 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV2 << 25)
290 #define CMU_AUXHFRCOCTRL_CLKDIV_DIV4 (_CMU_AUXHFRCOCTRL_CLKDIV_DIV4 << 25)
291 #define CMU_AUXHFRCOCTRL_FINETUNINGEN (0x1UL << 27)
292 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_SHIFT 27
293 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_MASK 0x8000000UL
294 #define _CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT 0x00000000UL
295 #define CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT (_CMU_AUXHFRCOCTRL_FINETUNINGEN_DEFAULT << 27)
296 #define _CMU_AUXHFRCOCTRL_VREFTC_SHIFT 28
297 #define _CMU_AUXHFRCOCTRL_VREFTC_MASK 0xF0000000UL
298 #define _CMU_AUXHFRCOCTRL_VREFTC_DEFAULT 0x0000000BUL
299 #define CMU_AUXHFRCOCTRL_VREFTC_DEFAULT (_CMU_AUXHFRCOCTRL_VREFTC_DEFAULT << 28)
301 /* Bit fields for CMU LFRCOCTRL */
302 #define _CMU_LFRCOCTRL_RESETVALUE 0x81060100UL
303 #define _CMU_LFRCOCTRL_MASK 0xF33701FFUL
304 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
305 #define _CMU_LFRCOCTRL_TUNING_MASK 0x1FFUL
306 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000100UL
307 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
308 #define CMU_LFRCOCTRL_ENVREF (0x1UL << 16)
309 #define _CMU_LFRCOCTRL_ENVREF_SHIFT 16
310 #define _CMU_LFRCOCTRL_ENVREF_MASK 0x10000UL
311 #define _CMU_LFRCOCTRL_ENVREF_DEFAULT 0x00000000UL
312 #define CMU_LFRCOCTRL_ENVREF_DEFAULT (_CMU_LFRCOCTRL_ENVREF_DEFAULT << 16)
313 #define CMU_LFRCOCTRL_ENCHOP (0x1UL << 17)
314 #define _CMU_LFRCOCTRL_ENCHOP_SHIFT 17
315 #define _CMU_LFRCOCTRL_ENCHOP_MASK 0x20000UL
316 #define _CMU_LFRCOCTRL_ENCHOP_DEFAULT 0x00000001UL
317 #define CMU_LFRCOCTRL_ENCHOP_DEFAULT (_CMU_LFRCOCTRL_ENCHOP_DEFAULT << 17)
318 #define CMU_LFRCOCTRL_ENDEM (0x1UL << 18)
319 #define _CMU_LFRCOCTRL_ENDEM_SHIFT 18
320 #define _CMU_LFRCOCTRL_ENDEM_MASK 0x40000UL
321 #define _CMU_LFRCOCTRL_ENDEM_DEFAULT 0x00000001UL
322 #define CMU_LFRCOCTRL_ENDEM_DEFAULT (_CMU_LFRCOCTRL_ENDEM_DEFAULT << 18)
323 #define _CMU_LFRCOCTRL_VREFUPDATE_SHIFT 20
324 #define _CMU_LFRCOCTRL_VREFUPDATE_MASK 0x300000UL
325 #define _CMU_LFRCOCTRL_VREFUPDATE_DEFAULT 0x00000000UL
326 #define _CMU_LFRCOCTRL_VREFUPDATE_32CYCLES 0x00000000UL
327 #define _CMU_LFRCOCTRL_VREFUPDATE_64CYCLES 0x00000001UL
328 #define _CMU_LFRCOCTRL_VREFUPDATE_128CYCLES 0x00000002UL
329 #define _CMU_LFRCOCTRL_VREFUPDATE_256CYCLES 0x00000003UL
330 #define CMU_LFRCOCTRL_VREFUPDATE_DEFAULT (_CMU_LFRCOCTRL_VREFUPDATE_DEFAULT << 20)
331 #define CMU_LFRCOCTRL_VREFUPDATE_32CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_32CYCLES << 20)
332 #define CMU_LFRCOCTRL_VREFUPDATE_64CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_64CYCLES << 20)
333 #define CMU_LFRCOCTRL_VREFUPDATE_128CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_128CYCLES << 20)
334 #define CMU_LFRCOCTRL_VREFUPDATE_256CYCLES (_CMU_LFRCOCTRL_VREFUPDATE_256CYCLES << 20)
335 #define _CMU_LFRCOCTRL_TIMEOUT_SHIFT 24
336 #define _CMU_LFRCOCTRL_TIMEOUT_MASK 0x3000000UL
337 #define _CMU_LFRCOCTRL_TIMEOUT_2CYCLES 0x00000000UL
338 #define _CMU_LFRCOCTRL_TIMEOUT_DEFAULT 0x00000001UL
339 #define _CMU_LFRCOCTRL_TIMEOUT_16CYCLES 0x00000001UL
340 #define _CMU_LFRCOCTRL_TIMEOUT_32CYCLES 0x00000002UL
341 #define CMU_LFRCOCTRL_TIMEOUT_2CYCLES (_CMU_LFRCOCTRL_TIMEOUT_2CYCLES << 24)
342 #define CMU_LFRCOCTRL_TIMEOUT_DEFAULT (_CMU_LFRCOCTRL_TIMEOUT_DEFAULT << 24)
343 #define CMU_LFRCOCTRL_TIMEOUT_16CYCLES (_CMU_LFRCOCTRL_TIMEOUT_16CYCLES << 24)
344 #define CMU_LFRCOCTRL_TIMEOUT_32CYCLES (_CMU_LFRCOCTRL_TIMEOUT_32CYCLES << 24)
345 #define _CMU_LFRCOCTRL_GMCCURTUNE_SHIFT 28
346 #define _CMU_LFRCOCTRL_GMCCURTUNE_MASK 0xF0000000UL
347 #define _CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT 0x00000008UL
348 #define CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT (_CMU_LFRCOCTRL_GMCCURTUNE_DEFAULT << 28)
350 /* Bit fields for CMU HFXOCTRL */
351 #define _CMU_HFXOCTRL_RESETVALUE 0x00000000UL
352 #define _CMU_HFXOCTRL_MASK 0x37000731UL
353 #define CMU_HFXOCTRL_MODE (0x1UL << 0)
354 #define _CMU_HFXOCTRL_MODE_SHIFT 0
355 #define _CMU_HFXOCTRL_MODE_MASK 0x1UL
356 #define _CMU_HFXOCTRL_MODE_DEFAULT 0x00000000UL
357 #define _CMU_HFXOCTRL_MODE_XTAL 0x00000000UL
358 #define _CMU_HFXOCTRL_MODE_EXTCLK 0x00000001UL
359 #define CMU_HFXOCTRL_MODE_DEFAULT (_CMU_HFXOCTRL_MODE_DEFAULT << 0)
360 #define CMU_HFXOCTRL_MODE_XTAL (_CMU_HFXOCTRL_MODE_XTAL << 0)
361 #define CMU_HFXOCTRL_MODE_EXTCLK (_CMU_HFXOCTRL_MODE_EXTCLK << 0)
362 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT 4
363 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK 0x30UL
364 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT 0x00000000UL
365 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD 0x00000000UL
366 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD 0x00000001UL
367 #define _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL 0x00000002UL
368 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_DEFAULT << 4)
369 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD << 4)
370 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD << 4)
371 #define CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MANUAL << 4)
372 #define CMU_HFXOCTRL_LOWPOWER (0x1UL << 8)
373 #define _CMU_HFXOCTRL_LOWPOWER_SHIFT 8
374 #define _CMU_HFXOCTRL_LOWPOWER_MASK 0x100UL
375 #define _CMU_HFXOCTRL_LOWPOWER_DEFAULT 0x00000000UL
376 #define CMU_HFXOCTRL_LOWPOWER_DEFAULT (_CMU_HFXOCTRL_LOWPOWER_DEFAULT << 8)
377 #define CMU_HFXOCTRL_XTI2GND (0x1UL << 9)
378 #define _CMU_HFXOCTRL_XTI2GND_SHIFT 9
379 #define _CMU_HFXOCTRL_XTI2GND_MASK 0x200UL
380 #define _CMU_HFXOCTRL_XTI2GND_DEFAULT 0x00000000UL
381 #define CMU_HFXOCTRL_XTI2GND_DEFAULT (_CMU_HFXOCTRL_XTI2GND_DEFAULT << 9)
382 #define CMU_HFXOCTRL_XTO2GND (0x1UL << 10)
383 #define _CMU_HFXOCTRL_XTO2GND_SHIFT 10
384 #define _CMU_HFXOCTRL_XTO2GND_MASK 0x400UL
385 #define _CMU_HFXOCTRL_XTO2GND_DEFAULT 0x00000000UL
386 #define CMU_HFXOCTRL_XTO2GND_DEFAULT (_CMU_HFXOCTRL_XTO2GND_DEFAULT << 10)
387 #define _CMU_HFXOCTRL_LFTIMEOUT_SHIFT 24
388 #define _CMU_HFXOCTRL_LFTIMEOUT_MASK 0x7000000UL
389 #define _CMU_HFXOCTRL_LFTIMEOUT_DEFAULT 0x00000000UL
390 #define _CMU_HFXOCTRL_LFTIMEOUT_0CYCLES 0x00000000UL
391 #define _CMU_HFXOCTRL_LFTIMEOUT_2CYCLES 0x00000001UL
392 #define _CMU_HFXOCTRL_LFTIMEOUT_4CYCLES 0x00000002UL
393 #define _CMU_HFXOCTRL_LFTIMEOUT_16CYCLES 0x00000003UL
394 #define _CMU_HFXOCTRL_LFTIMEOUT_32CYCLES 0x00000004UL
395 #define _CMU_HFXOCTRL_LFTIMEOUT_64CYCLES 0x00000005UL
396 #define _CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES 0x00000006UL
397 #define _CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES 0x00000007UL
398 #define CMU_HFXOCTRL_LFTIMEOUT_DEFAULT (_CMU_HFXOCTRL_LFTIMEOUT_DEFAULT << 24)
399 #define CMU_HFXOCTRL_LFTIMEOUT_0CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_0CYCLES << 24)
400 #define CMU_HFXOCTRL_LFTIMEOUT_2CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_2CYCLES << 24)
401 #define CMU_HFXOCTRL_LFTIMEOUT_4CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4CYCLES << 24)
402 #define CMU_HFXOCTRL_LFTIMEOUT_16CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_16CYCLES << 24)
403 #define CMU_HFXOCTRL_LFTIMEOUT_32CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_32CYCLES << 24)
404 #define CMU_HFXOCTRL_LFTIMEOUT_64CYCLES (_CMU_HFXOCTRL_LFTIMEOUT_64CYCLES << 24)
405 #define CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_1KCYCLES << 24)
406 #define CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES (_CMU_HFXOCTRL_LFTIMEOUT_4KCYCLES << 24)
407 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1 (0x1UL << 28)
408 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_SHIFT 28
409 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK 0x10000000UL
410 #define _CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT 0x00000000UL
411 #define CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT << 28)
412 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 (0x1UL << 29)
413 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_SHIFT 29
414 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK 0x20000000UL
415 #define _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT 0x00000000UL
416 #define CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT (_CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT << 29)
418 /* Bit fields for CMU HFXOSTARTUPCTRL */
419 #define _CMU_HFXOSTARTUPCTRL_RESETVALUE 0x00050020UL
420 #define _CMU_HFXOSTARTUPCTRL_MASK 0x000FF87FUL
421 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT 0
422 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK 0x7FUL
423 #define _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT 0x00000020UL
424 #define CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT << 0)
425 #define _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT 11
426 #define _CMU_HFXOSTARTUPCTRL_CTUNE_MASK 0xFF800UL
427 #define _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT 0x000000A0UL
428 #define CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT (_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT << 11)
430 /* Bit fields for CMU HFXOSTEADYSTATECTRL */
431 #define _CMU_HFXOSTEADYSTATECTRL_RESETVALUE 0xA30B4507UL
432 #define _CMU_HFXOSTEADYSTATECTRL_MASK 0xF70FFFFFUL
433 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT 0
434 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK 0x7FUL
435 #define _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT 0x00000007UL
436 #define CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT << 0)
437 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT 7
438 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK 0x780UL
439 #define _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT 0x0000000AUL
440 #define CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT << 7)
441 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT 11
442 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK 0xFF800UL
443 #define _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT 0x00000168UL
444 #define CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT << 11)
445 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_SHIFT 24
446 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_MASK 0x3000000UL
447 #define _CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT 0x00000003UL
448 #define CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGSELILOW_DEFAULT << 24)
449 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN (0x1UL << 26)
450 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_SHIFT 26
451 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_MASK 0x4000000UL
452 #define _CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT 0x00000000UL
453 #define CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_PEAKDETEN_DEFAULT << 26)
454 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT 28
455 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK 0xF0000000UL
456 #define _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT 0x0000000AUL
457 #define CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT (_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_DEFAULT << 28)
459 /* Bit fields for CMU HFXOTIMEOUTCTRL */
460 #define _CMU_HFXOTIMEOUTCTRL_RESETVALUE 0x0002A067UL
461 #define _CMU_HFXOTIMEOUTCTRL_MASK 0x000FF0FFUL
462 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT 0
463 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK 0xFUL
464 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES 0x00000000UL
465 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES 0x00000001UL
466 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES 0x00000002UL
467 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES 0x00000003UL
468 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES 0x00000004UL
469 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES 0x00000005UL
470 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES 0x00000006UL
471 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT 0x00000007UL
472 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES 0x00000007UL
473 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES 0x00000008UL
474 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES 0x00000009UL
475 #define _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES 0x0000000AUL
476 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES << 0)
477 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4CYCLES << 0)
478 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16CYCLES << 0)
479 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32CYCLES << 0)
480 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_256CYCLES << 0)
481 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_1KCYCLES << 0)
482 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2KCYCLES << 0)
483 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT << 0)
484 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_4KCYCLES << 0)
485 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_8KCYCLES << 0)
486 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_16KCYCLES << 0)
487 #define CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_32KCYCLES << 0)
488 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT 4
489 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK 0xF0UL
490 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES 0x00000000UL
491 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES 0x00000001UL
492 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES 0x00000002UL
493 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES 0x00000003UL
494 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES 0x00000004UL
495 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES 0x00000005UL
496 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT 0x00000006UL
497 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES 0x00000006UL
498 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES 0x00000007UL
499 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES 0x00000008UL
500 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES 0x00000009UL
501 #define _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES 0x0000000AUL
502 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES << 4)
503 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4CYCLES << 4)
504 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16CYCLES << 4)
505 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32CYCLES << 4)
506 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_256CYCLES << 4)
507 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_1KCYCLES << 4)
508 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT << 4)
509 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2KCYCLES << 4)
510 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_4KCYCLES << 4)
511 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_8KCYCLES << 4)
512 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_16KCYCLES << 4)
513 #define CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_32KCYCLES << 4)
514 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT 12
515 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK 0xF000UL
516 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES 0x00000000UL
517 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES 0x00000001UL
518 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES 0x00000002UL
519 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES 0x00000003UL
520 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES 0x00000004UL
521 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES 0x00000005UL
522 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES 0x00000006UL
523 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES 0x00000007UL
524 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES 0x00000008UL
525 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES 0x00000009UL
526 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT 0x0000000AUL
527 #define _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES 0x0000000AUL
528 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2CYCLES << 12)
529 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4CYCLES << 12)
530 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16CYCLES << 12)
531 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32CYCLES << 12)
532 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_256CYCLES << 12)
533 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_1KCYCLES << 12)
534 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_2KCYCLES << 12)
535 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_4KCYCLES << 12)
536 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_8KCYCLES << 12)
537 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_16KCYCLES << 12)
538 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT << 12)
539 #define CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_32KCYCLES << 12)
540 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT 16
541 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK 0xF0000UL
542 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES 0x00000000UL
543 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES 0x00000001UL
544 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT 0x00000002UL
545 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES 0x00000002UL
546 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES 0x00000003UL
547 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES 0x00000004UL
548 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES 0x00000005UL
549 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES 0x00000006UL
550 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES 0x00000007UL
551 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES 0x00000008UL
552 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES 0x00000009UL
553 #define _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES 0x0000000AUL
554 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2CYCLES << 16)
555 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4CYCLES << 16)
556 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT << 16)
557 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16CYCLES << 16)
558 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32CYCLES << 16)
559 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_256CYCLES << 16)
560 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_1KCYCLES << 16)
561 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_2KCYCLES << 16)
562 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_4KCYCLES << 16)
563 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_8KCYCLES << 16)
564 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_16KCYCLES << 16)
565 #define CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES (_CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_32KCYCLES << 16)
567 /* Bit fields for CMU LFXOCTRL */
568 #define _CMU_LFXOCTRL_RESETVALUE 0x07009000UL
569 #define _CMU_LFXOCTRL_MASK 0x0713DB7FUL
570 #define _CMU_LFXOCTRL_TUNING_SHIFT 0
571 #define _CMU_LFXOCTRL_TUNING_MASK 0x7FUL
572 #define _CMU_LFXOCTRL_TUNING_DEFAULT 0x00000000UL
573 #define CMU_LFXOCTRL_TUNING_DEFAULT (_CMU_LFXOCTRL_TUNING_DEFAULT << 0)
574 #define _CMU_LFXOCTRL_MODE_SHIFT 8
575 #define _CMU_LFXOCTRL_MODE_MASK 0x300UL
576 #define _CMU_LFXOCTRL_MODE_DEFAULT 0x00000000UL
577 #define _CMU_LFXOCTRL_MODE_XTAL 0x00000000UL
578 #define _CMU_LFXOCTRL_MODE_BUFEXTCLK 0x00000001UL
579 #define _CMU_LFXOCTRL_MODE_DIGEXTCLK 0x00000002UL
580 #define CMU_LFXOCTRL_MODE_DEFAULT (_CMU_LFXOCTRL_MODE_DEFAULT << 8)
581 #define CMU_LFXOCTRL_MODE_XTAL (_CMU_LFXOCTRL_MODE_XTAL << 8)
582 #define CMU_LFXOCTRL_MODE_BUFEXTCLK (_CMU_LFXOCTRL_MODE_BUFEXTCLK << 8)
583 #define CMU_LFXOCTRL_MODE_DIGEXTCLK (_CMU_LFXOCTRL_MODE_DIGEXTCLK << 8)
584 #define _CMU_LFXOCTRL_GAIN_SHIFT 11
585 #define _CMU_LFXOCTRL_GAIN_MASK 0x1800UL
586 #define _CMU_LFXOCTRL_GAIN_DEFAULT 0x00000002UL
587 #define CMU_LFXOCTRL_GAIN_DEFAULT (_CMU_LFXOCTRL_GAIN_DEFAULT << 11)
588 #define CMU_LFXOCTRL_HIGHAMPL (0x1UL << 14)
589 #define _CMU_LFXOCTRL_HIGHAMPL_SHIFT 14
590 #define _CMU_LFXOCTRL_HIGHAMPL_MASK 0x4000UL
591 #define _CMU_LFXOCTRL_HIGHAMPL_DEFAULT 0x00000000UL
592 #define CMU_LFXOCTRL_HIGHAMPL_DEFAULT (_CMU_LFXOCTRL_HIGHAMPL_DEFAULT << 14)
593 #define CMU_LFXOCTRL_AGC (0x1UL << 15)
594 #define _CMU_LFXOCTRL_AGC_SHIFT 15
595 #define _CMU_LFXOCTRL_AGC_MASK 0x8000UL
596 #define _CMU_LFXOCTRL_AGC_DEFAULT 0x00000001UL
597 #define CMU_LFXOCTRL_AGC_DEFAULT (_CMU_LFXOCTRL_AGC_DEFAULT << 15)
598 #define _CMU_LFXOCTRL_CUR_SHIFT 16
599 #define _CMU_LFXOCTRL_CUR_MASK 0x30000UL
600 #define _CMU_LFXOCTRL_CUR_DEFAULT 0x00000000UL
601 #define CMU_LFXOCTRL_CUR_DEFAULT (_CMU_LFXOCTRL_CUR_DEFAULT << 16)
602 #define CMU_LFXOCTRL_BUFCUR (0x1UL << 20)
603 #define _CMU_LFXOCTRL_BUFCUR_SHIFT 20
604 #define _CMU_LFXOCTRL_BUFCUR_MASK 0x100000UL
605 #define _CMU_LFXOCTRL_BUFCUR_DEFAULT 0x00000000UL
606 #define CMU_LFXOCTRL_BUFCUR_DEFAULT (_CMU_LFXOCTRL_BUFCUR_DEFAULT << 20)
607 #define _CMU_LFXOCTRL_TIMEOUT_SHIFT 24
608 #define _CMU_LFXOCTRL_TIMEOUT_MASK 0x7000000UL
609 #define _CMU_LFXOCTRL_TIMEOUT_2CYCLES 0x00000000UL
610 #define _CMU_LFXOCTRL_TIMEOUT_256CYCLES 0x00000001UL
611 #define _CMU_LFXOCTRL_TIMEOUT_1KCYCLES 0x00000002UL
612 #define _CMU_LFXOCTRL_TIMEOUT_2KCYCLES 0x00000003UL
613 #define _CMU_LFXOCTRL_TIMEOUT_4KCYCLES 0x00000004UL
614 #define _CMU_LFXOCTRL_TIMEOUT_8KCYCLES 0x00000005UL
615 #define _CMU_LFXOCTRL_TIMEOUT_16KCYCLES 0x00000006UL
616 #define _CMU_LFXOCTRL_TIMEOUT_DEFAULT 0x00000007UL
617 #define _CMU_LFXOCTRL_TIMEOUT_32KCYCLES 0x00000007UL
618 #define CMU_LFXOCTRL_TIMEOUT_2CYCLES (_CMU_LFXOCTRL_TIMEOUT_2CYCLES << 24)
619 #define CMU_LFXOCTRL_TIMEOUT_256CYCLES (_CMU_LFXOCTRL_TIMEOUT_256CYCLES << 24)
620 #define CMU_LFXOCTRL_TIMEOUT_1KCYCLES (_CMU_LFXOCTRL_TIMEOUT_1KCYCLES << 24)
621 #define CMU_LFXOCTRL_TIMEOUT_2KCYCLES (_CMU_LFXOCTRL_TIMEOUT_2KCYCLES << 24)
622 #define CMU_LFXOCTRL_TIMEOUT_4KCYCLES (_CMU_LFXOCTRL_TIMEOUT_4KCYCLES << 24)
623 #define CMU_LFXOCTRL_TIMEOUT_8KCYCLES (_CMU_LFXOCTRL_TIMEOUT_8KCYCLES << 24)
624 #define CMU_LFXOCTRL_TIMEOUT_16KCYCLES (_CMU_LFXOCTRL_TIMEOUT_16KCYCLES << 24)
625 #define CMU_LFXOCTRL_TIMEOUT_DEFAULT (_CMU_LFXOCTRL_TIMEOUT_DEFAULT << 24)
626 #define CMU_LFXOCTRL_TIMEOUT_32KCYCLES (_CMU_LFXOCTRL_TIMEOUT_32KCYCLES << 24)
628 /* Bit fields for CMU DPLLCTRL */
629 #define _CMU_DPLLCTRL_RESETVALUE 0x00000000UL
630 #define _CMU_DPLLCTRL_MASK 0x0000001FUL
631 #define CMU_DPLLCTRL_MODE (0x1UL << 0)
632 #define _CMU_DPLLCTRL_MODE_SHIFT 0
633 #define _CMU_DPLLCTRL_MODE_MASK 0x1UL
634 #define _CMU_DPLLCTRL_MODE_DEFAULT 0x00000000UL
635 #define _CMU_DPLLCTRL_MODE_FREQLL 0x00000000UL
636 #define _CMU_DPLLCTRL_MODE_PHASELL 0x00000001UL
637 #define CMU_DPLLCTRL_MODE_DEFAULT (_CMU_DPLLCTRL_MODE_DEFAULT << 0)
638 #define CMU_DPLLCTRL_MODE_FREQLL (_CMU_DPLLCTRL_MODE_FREQLL << 0)
639 #define CMU_DPLLCTRL_MODE_PHASELL (_CMU_DPLLCTRL_MODE_PHASELL << 0)
640 #define CMU_DPLLCTRL_EDGESEL (0x1UL << 1)
641 #define _CMU_DPLLCTRL_EDGESEL_SHIFT 1
642 #define _CMU_DPLLCTRL_EDGESEL_MASK 0x2UL
643 #define _CMU_DPLLCTRL_EDGESEL_DEFAULT 0x00000000UL
644 #define _CMU_DPLLCTRL_EDGESEL_FALL 0x00000000UL
645 #define _CMU_DPLLCTRL_EDGESEL_RISE 0x00000001UL
646 #define CMU_DPLLCTRL_EDGESEL_DEFAULT (_CMU_DPLLCTRL_EDGESEL_DEFAULT << 1)
647 #define CMU_DPLLCTRL_EDGESEL_FALL (_CMU_DPLLCTRL_EDGESEL_FALL << 1)
648 #define CMU_DPLLCTRL_EDGESEL_RISE (_CMU_DPLLCTRL_EDGESEL_RISE << 1)
649 #define CMU_DPLLCTRL_AUTORECOVER (0x1UL << 2)
650 #define _CMU_DPLLCTRL_AUTORECOVER_SHIFT 2
651 #define _CMU_DPLLCTRL_AUTORECOVER_MASK 0x4UL
652 #define _CMU_DPLLCTRL_AUTORECOVER_DEFAULT 0x00000000UL
653 #define CMU_DPLLCTRL_AUTORECOVER_DEFAULT (_CMU_DPLLCTRL_AUTORECOVER_DEFAULT << 2)
654 #define _CMU_DPLLCTRL_REFSEL_SHIFT 3
655 #define _CMU_DPLLCTRL_REFSEL_MASK 0x18UL
656 #define _CMU_DPLLCTRL_REFSEL_DEFAULT 0x00000000UL
657 #define _CMU_DPLLCTRL_REFSEL_HFXO 0x00000000UL
658 #define _CMU_DPLLCTRL_REFSEL_LFXO 0x00000001UL
659 #define _CMU_DPLLCTRL_REFSEL_CLKIN0 0x00000003UL
660 #define CMU_DPLLCTRL_REFSEL_DEFAULT (_CMU_DPLLCTRL_REFSEL_DEFAULT << 3)
661 #define CMU_DPLLCTRL_REFSEL_HFXO (_CMU_DPLLCTRL_REFSEL_HFXO << 3)
662 #define CMU_DPLLCTRL_REFSEL_LFXO (_CMU_DPLLCTRL_REFSEL_LFXO << 3)
663 #define CMU_DPLLCTRL_REFSEL_CLKIN0 (_CMU_DPLLCTRL_REFSEL_CLKIN0 << 3)
665 /* Bit fields for CMU DPLLCTRL1 */
666 #define _CMU_DPLLCTRL1_RESETVALUE 0x00000000UL
667 #define _CMU_DPLLCTRL1_MASK 0x0FFF0FFFUL
668 #define _CMU_DPLLCTRL1_M_SHIFT 0
669 #define _CMU_DPLLCTRL1_M_MASK 0xFFFUL
670 #define _CMU_DPLLCTRL1_M_DEFAULT 0x00000000UL
671 #define CMU_DPLLCTRL1_M_DEFAULT (_CMU_DPLLCTRL1_M_DEFAULT << 0)
672 #define _CMU_DPLLCTRL1_N_SHIFT 16
673 #define _CMU_DPLLCTRL1_N_MASK 0xFFF0000UL
674 #define _CMU_DPLLCTRL1_N_DEFAULT 0x00000000UL
675 #define CMU_DPLLCTRL1_N_DEFAULT (_CMU_DPLLCTRL1_N_DEFAULT << 16)
677 /* Bit fields for CMU CALCTRL */
678 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
679 #define _CMU_CALCTRL_MASK 0x0F0F01FFUL
680 #define _CMU_CALCTRL_UPSEL_SHIFT 0
681 #define _CMU_CALCTRL_UPSEL_MASK 0xFUL
682 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
683 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
684 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
685 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
686 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
687 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
688 #define _CMU_CALCTRL_UPSEL_PRS 0x00000005UL
689 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
690 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
691 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
692 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
693 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
694 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
695 #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 0)
696 #define _CMU_CALCTRL_DOWNSEL_SHIFT 4
697 #define _CMU_CALCTRL_DOWNSEL_MASK 0xF0UL
698 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL
699 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL
700 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL
701 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL
702 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL
703 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL
704 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL
705 #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000006UL
706 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 4)
707 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 4)
708 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 4)
709 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 4)
710 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 4)
711 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 4)
712 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 4)
713 #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 4)
714 #define CMU_CALCTRL_CONT (0x1UL << 8)
715 #define _CMU_CALCTRL_CONT_SHIFT 8
716 #define _CMU_CALCTRL_CONT_MASK 0x100UL
717 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL
718 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 8)
719 #define _CMU_CALCTRL_PRSUPSEL_SHIFT 16
720 #define _CMU_CALCTRL_PRSUPSEL_MASK 0xF0000UL
721 #define _CMU_CALCTRL_PRSUPSEL_DEFAULT 0x00000000UL
722 #define _CMU_CALCTRL_PRSUPSEL_PRSCH0 0x00000000UL
723 #define _CMU_CALCTRL_PRSUPSEL_PRSCH1 0x00000001UL
724 #define _CMU_CALCTRL_PRSUPSEL_PRSCH2 0x00000002UL
725 #define _CMU_CALCTRL_PRSUPSEL_PRSCH3 0x00000003UL
726 #define _CMU_CALCTRL_PRSUPSEL_PRSCH4 0x00000004UL
727 #define _CMU_CALCTRL_PRSUPSEL_PRSCH5 0x00000005UL
728 #define _CMU_CALCTRL_PRSUPSEL_PRSCH6 0x00000006UL
729 #define _CMU_CALCTRL_PRSUPSEL_PRSCH7 0x00000007UL
730 #define _CMU_CALCTRL_PRSUPSEL_PRSCH8 0x00000008UL
731 #define _CMU_CALCTRL_PRSUPSEL_PRSCH9 0x00000009UL
732 #define _CMU_CALCTRL_PRSUPSEL_PRSCH10 0x0000000AUL
733 #define _CMU_CALCTRL_PRSUPSEL_PRSCH11 0x0000000BUL
734 #define CMU_CALCTRL_PRSUPSEL_DEFAULT (_CMU_CALCTRL_PRSUPSEL_DEFAULT << 16)
735 #define CMU_CALCTRL_PRSUPSEL_PRSCH0 (_CMU_CALCTRL_PRSUPSEL_PRSCH0 << 16)
736 #define CMU_CALCTRL_PRSUPSEL_PRSCH1 (_CMU_CALCTRL_PRSUPSEL_PRSCH1 << 16)
737 #define CMU_CALCTRL_PRSUPSEL_PRSCH2 (_CMU_CALCTRL_PRSUPSEL_PRSCH2 << 16)
738 #define CMU_CALCTRL_PRSUPSEL_PRSCH3 (_CMU_CALCTRL_PRSUPSEL_PRSCH3 << 16)
739 #define CMU_CALCTRL_PRSUPSEL_PRSCH4 (_CMU_CALCTRL_PRSUPSEL_PRSCH4 << 16)
740 #define CMU_CALCTRL_PRSUPSEL_PRSCH5 (_CMU_CALCTRL_PRSUPSEL_PRSCH5 << 16)
741 #define CMU_CALCTRL_PRSUPSEL_PRSCH6 (_CMU_CALCTRL_PRSUPSEL_PRSCH6 << 16)
742 #define CMU_CALCTRL_PRSUPSEL_PRSCH7 (_CMU_CALCTRL_PRSUPSEL_PRSCH7 << 16)
743 #define CMU_CALCTRL_PRSUPSEL_PRSCH8 (_CMU_CALCTRL_PRSUPSEL_PRSCH8 << 16)
744 #define CMU_CALCTRL_PRSUPSEL_PRSCH9 (_CMU_CALCTRL_PRSUPSEL_PRSCH9 << 16)
745 #define CMU_CALCTRL_PRSUPSEL_PRSCH10 (_CMU_CALCTRL_PRSUPSEL_PRSCH10 << 16)
746 #define CMU_CALCTRL_PRSUPSEL_PRSCH11 (_CMU_CALCTRL_PRSUPSEL_PRSCH11 << 16)
747 #define _CMU_CALCTRL_PRSDOWNSEL_SHIFT 24
748 #define _CMU_CALCTRL_PRSDOWNSEL_MASK 0xF000000UL
749 #define _CMU_CALCTRL_PRSDOWNSEL_DEFAULT 0x00000000UL
750 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH0 0x00000000UL
751 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH1 0x00000001UL
752 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH2 0x00000002UL
753 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH3 0x00000003UL
754 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH4 0x00000004UL
755 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH5 0x00000005UL
756 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH6 0x00000006UL
757 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH7 0x00000007UL
758 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH8 0x00000008UL
759 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH9 0x00000009UL
760 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH10 0x0000000AUL
761 #define _CMU_CALCTRL_PRSDOWNSEL_PRSCH11 0x0000000BUL
762 #define CMU_CALCTRL_PRSDOWNSEL_DEFAULT (_CMU_CALCTRL_PRSDOWNSEL_DEFAULT << 24)
763 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH0 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH0 << 24)
764 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH1 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH1 << 24)
765 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH2 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH2 << 24)
766 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH3 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH3 << 24)
767 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH4 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH4 << 24)
768 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH5 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH5 << 24)
769 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH6 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH6 << 24)
770 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH7 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH7 << 24)
771 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH8 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH8 << 24)
772 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH9 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH9 << 24)
773 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH10 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH10 << 24)
774 #define CMU_CALCTRL_PRSDOWNSEL_PRSCH11 (_CMU_CALCTRL_PRSDOWNSEL_PRSCH11 << 24)
776 /* Bit fields for CMU CALCNT */
777 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
778 #define _CMU_CALCNT_MASK 0x000FFFFFUL
779 #define _CMU_CALCNT_CALCNT_SHIFT 0
780 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
781 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
782 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
784 /* Bit fields for CMU OSCENCMD */
785 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
786 #define _CMU_OSCENCMD_MASK 0x000033FFUL
787 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
788 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
789 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
790 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
791 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
792 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
793 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
794 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
795 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
796 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
797 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
798 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
799 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
800 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
801 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
802 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
803 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
804 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
805 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
806 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
807 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
808 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
809 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
810 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
811 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
812 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
813 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
814 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
815 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
816 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
817 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
818 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
819 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
820 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
821 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
822 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
823 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
824 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
825 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
826 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
827 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
828 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
829 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
830 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
831 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
832 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
833 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
834 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
835 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
836 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
837 #define CMU_OSCENCMD_DPLLEN (0x1UL << 12)
838 #define _CMU_OSCENCMD_DPLLEN_SHIFT 12
839 #define _CMU_OSCENCMD_DPLLEN_MASK 0x1000UL
840 #define _CMU_OSCENCMD_DPLLEN_DEFAULT 0x00000000UL
841 #define CMU_OSCENCMD_DPLLEN_DEFAULT (_CMU_OSCENCMD_DPLLEN_DEFAULT << 12)
842 #define CMU_OSCENCMD_DPLLDIS (0x1UL << 13)
843 #define _CMU_OSCENCMD_DPLLDIS_SHIFT 13
844 #define _CMU_OSCENCMD_DPLLDIS_MASK 0x2000UL
845 #define _CMU_OSCENCMD_DPLLDIS_DEFAULT 0x00000000UL
846 #define CMU_OSCENCMD_DPLLDIS_DEFAULT (_CMU_OSCENCMD_DPLLDIS_DEFAULT << 13)
848 /* Bit fields for CMU CMD */
849 #define _CMU_CMD_RESETVALUE 0x00000000UL
850 #define _CMU_CMD_MASK 0x00000033UL
851 #define CMU_CMD_CALSTART (0x1UL << 0)
852 #define _CMU_CMD_CALSTART_SHIFT 0
853 #define _CMU_CMD_CALSTART_MASK 0x1UL
854 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
855 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 0)
856 #define CMU_CMD_CALSTOP (0x1UL << 1)
857 #define _CMU_CMD_CALSTOP_SHIFT 1
858 #define _CMU_CMD_CALSTOP_MASK 0x2UL
859 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL
860 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 1)
861 #define CMU_CMD_HFXOPEAKDETSTART (0x1UL << 4)
862 #define _CMU_CMD_HFXOPEAKDETSTART_SHIFT 4
863 #define _CMU_CMD_HFXOPEAKDETSTART_MASK 0x10UL
864 #define _CMU_CMD_HFXOPEAKDETSTART_DEFAULT 0x00000000UL
865 #define CMU_CMD_HFXOPEAKDETSTART_DEFAULT (_CMU_CMD_HFXOPEAKDETSTART_DEFAULT << 4)
866 #define CMU_CMD_HFXOSHUNTOPTSTART (0x1UL << 5)
867 #define _CMU_CMD_HFXOSHUNTOPTSTART_SHIFT 5
868 #define _CMU_CMD_HFXOSHUNTOPTSTART_MASK 0x20UL
869 #define _CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT 0x00000000UL
870 #define CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT (_CMU_CMD_HFXOSHUNTOPTSTART_DEFAULT << 5)
872 /* Bit fields for CMU DBGCLKSEL */
873 #define _CMU_DBGCLKSEL_RESETVALUE 0x00000000UL
874 #define _CMU_DBGCLKSEL_MASK 0x00000001UL
875 #define _CMU_DBGCLKSEL_DBG_SHIFT 0
876 #define _CMU_DBGCLKSEL_DBG_MASK 0x1UL
877 #define _CMU_DBGCLKSEL_DBG_DEFAULT 0x00000000UL
878 #define _CMU_DBGCLKSEL_DBG_AUXHFRCO 0x00000000UL
879 #define _CMU_DBGCLKSEL_DBG_HFCLK 0x00000001UL
880 #define CMU_DBGCLKSEL_DBG_DEFAULT (_CMU_DBGCLKSEL_DBG_DEFAULT << 0)
881 #define CMU_DBGCLKSEL_DBG_AUXHFRCO (_CMU_DBGCLKSEL_DBG_AUXHFRCO << 0)
882 #define CMU_DBGCLKSEL_DBG_HFCLK (_CMU_DBGCLKSEL_DBG_HFCLK << 0)
884 /* Bit fields for CMU HFCLKSEL */
885 #define _CMU_HFCLKSEL_RESETVALUE 0x00000000UL
886 #define _CMU_HFCLKSEL_MASK 0x00000007UL
887 #define _CMU_HFCLKSEL_HF_SHIFT 0
888 #define _CMU_HFCLKSEL_HF_MASK 0x7UL
889 #define _CMU_HFCLKSEL_HF_DEFAULT 0x00000000UL
890 #define _CMU_HFCLKSEL_HF_HFRCO 0x00000001UL
891 #define _CMU_HFCLKSEL_HF_HFXO 0x00000002UL
892 #define _CMU_HFCLKSEL_HF_LFRCO 0x00000003UL
893 #define _CMU_HFCLKSEL_HF_LFXO 0x00000004UL
894 #define _CMU_HFCLKSEL_HF_HFRCODIV2 0x00000005UL
895 #define _CMU_HFCLKSEL_HF_CLKIN0 0x00000007UL
896 #define CMU_HFCLKSEL_HF_DEFAULT (_CMU_HFCLKSEL_HF_DEFAULT << 0)
897 #define CMU_HFCLKSEL_HF_HFRCO (_CMU_HFCLKSEL_HF_HFRCO << 0)
898 #define CMU_HFCLKSEL_HF_HFXO (_CMU_HFCLKSEL_HF_HFXO << 0)
899 #define CMU_HFCLKSEL_HF_LFRCO (_CMU_HFCLKSEL_HF_LFRCO << 0)
900 #define CMU_HFCLKSEL_HF_LFXO (_CMU_HFCLKSEL_HF_LFXO << 0)
901 #define CMU_HFCLKSEL_HF_HFRCODIV2 (_CMU_HFCLKSEL_HF_HFRCODIV2 << 0)
902 #define CMU_HFCLKSEL_HF_CLKIN0 (_CMU_HFCLKSEL_HF_CLKIN0 << 0)
904 /* Bit fields for CMU LFACLKSEL */
905 #define _CMU_LFACLKSEL_RESETVALUE 0x00000000UL
906 #define _CMU_LFACLKSEL_MASK 0x00000007UL
907 #define _CMU_LFACLKSEL_LFA_SHIFT 0
908 #define _CMU_LFACLKSEL_LFA_MASK 0x7UL
909 #define _CMU_LFACLKSEL_LFA_DEFAULT 0x00000000UL
910 #define _CMU_LFACLKSEL_LFA_DISABLED 0x00000000UL
911 #define _CMU_LFACLKSEL_LFA_LFRCO 0x00000001UL
912 #define _CMU_LFACLKSEL_LFA_LFXO 0x00000002UL
913 #define _CMU_LFACLKSEL_LFA_ULFRCO 0x00000004UL
914 #define CMU_LFACLKSEL_LFA_DEFAULT (_CMU_LFACLKSEL_LFA_DEFAULT << 0)
915 #define CMU_LFACLKSEL_LFA_DISABLED (_CMU_LFACLKSEL_LFA_DISABLED << 0)
916 #define CMU_LFACLKSEL_LFA_LFRCO (_CMU_LFACLKSEL_LFA_LFRCO << 0)
917 #define CMU_LFACLKSEL_LFA_LFXO (_CMU_LFACLKSEL_LFA_LFXO << 0)
918 #define CMU_LFACLKSEL_LFA_ULFRCO (_CMU_LFACLKSEL_LFA_ULFRCO << 0)
920 /* Bit fields for CMU LFBCLKSEL */
921 #define _CMU_LFBCLKSEL_RESETVALUE 0x00000000UL
922 #define _CMU_LFBCLKSEL_MASK 0x00000007UL
923 #define _CMU_LFBCLKSEL_LFB_SHIFT 0
924 #define _CMU_LFBCLKSEL_LFB_MASK 0x7UL
925 #define _CMU_LFBCLKSEL_LFB_DEFAULT 0x00000000UL
926 #define _CMU_LFBCLKSEL_LFB_DISABLED 0x00000000UL
927 #define _CMU_LFBCLKSEL_LFB_LFRCO 0x00000001UL
928 #define _CMU_LFBCLKSEL_LFB_LFXO 0x00000002UL
929 #define _CMU_LFBCLKSEL_LFB_HFCLKLE 0x00000003UL
930 #define _CMU_LFBCLKSEL_LFB_ULFRCO 0x00000004UL
931 #define CMU_LFBCLKSEL_LFB_DEFAULT (_CMU_LFBCLKSEL_LFB_DEFAULT << 0)
932 #define CMU_LFBCLKSEL_LFB_DISABLED (_CMU_LFBCLKSEL_LFB_DISABLED << 0)
933 #define CMU_LFBCLKSEL_LFB_LFRCO (_CMU_LFBCLKSEL_LFB_LFRCO << 0)
934 #define CMU_LFBCLKSEL_LFB_LFXO (_CMU_LFBCLKSEL_LFB_LFXO << 0)
935 #define CMU_LFBCLKSEL_LFB_HFCLKLE (_CMU_LFBCLKSEL_LFB_HFCLKLE << 0)
936 #define CMU_LFBCLKSEL_LFB_ULFRCO (_CMU_LFBCLKSEL_LFB_ULFRCO << 0)
938 /* Bit fields for CMU LFECLKSEL */
939 #define _CMU_LFECLKSEL_RESETVALUE 0x00000000UL
940 #define _CMU_LFECLKSEL_MASK 0x00000007UL
941 #define _CMU_LFECLKSEL_LFE_SHIFT 0
942 #define _CMU_LFECLKSEL_LFE_MASK 0x7UL
943 #define _CMU_LFECLKSEL_LFE_DEFAULT 0x00000000UL
944 #define _CMU_LFECLKSEL_LFE_DISABLED 0x00000000UL
945 #define _CMU_LFECLKSEL_LFE_LFRCO 0x00000001UL
946 #define _CMU_LFECLKSEL_LFE_LFXO 0x00000002UL
947 #define _CMU_LFECLKSEL_LFE_ULFRCO 0x00000004UL
948 #define CMU_LFECLKSEL_LFE_DEFAULT (_CMU_LFECLKSEL_LFE_DEFAULT << 0)
949 #define CMU_LFECLKSEL_LFE_DISABLED (_CMU_LFECLKSEL_LFE_DISABLED << 0)
950 #define CMU_LFECLKSEL_LFE_LFRCO (_CMU_LFECLKSEL_LFE_LFRCO << 0)
951 #define CMU_LFECLKSEL_LFE_LFXO (_CMU_LFECLKSEL_LFE_LFXO << 0)
952 #define CMU_LFECLKSEL_LFE_ULFRCO (_CMU_LFECLKSEL_LFE_ULFRCO << 0)
954 /* Bit fields for CMU STATUS */
955 #define _CMU_STATUS_RESETVALUE 0x00010003UL
956 #define _CMU_STATUS_MASK 0x3FE133FFUL
957 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
958 #define _CMU_STATUS_HFRCOENS_SHIFT 0
959 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
960 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
961 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
962 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
963 #define _CMU_STATUS_HFRCORDY_SHIFT 1
964 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
965 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
966 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
967 #define CMU_STATUS_HFXOENS (0x1UL << 2)
968 #define _CMU_STATUS_HFXOENS_SHIFT 2
969 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
970 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
971 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
972 #define CMU_STATUS_HFXORDY (0x1UL << 3)
973 #define _CMU_STATUS_HFXORDY_SHIFT 3
974 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
975 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
976 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
977 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
978 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
979 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
980 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
981 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
982 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
983 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
984 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
985 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
986 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
987 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
988 #define _CMU_STATUS_LFRCOENS_SHIFT 6
989 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
990 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
991 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
992 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
993 #define _CMU_STATUS_LFRCORDY_SHIFT 7
994 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
995 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
996 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
997 #define CMU_STATUS_LFXOENS (0x1UL << 8)
998 #define _CMU_STATUS_LFXOENS_SHIFT 8
999 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
1000 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
1001 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
1002 #define CMU_STATUS_LFXORDY (0x1UL << 9)
1003 #define _CMU_STATUS_LFXORDY_SHIFT 9
1004 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
1005 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
1006 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
1007 #define CMU_STATUS_DPLLENS (0x1UL << 12)
1008 #define _CMU_STATUS_DPLLENS_SHIFT 12
1009 #define _CMU_STATUS_DPLLENS_MASK 0x1000UL
1010 #define _CMU_STATUS_DPLLENS_DEFAULT 0x00000000UL
1011 #define CMU_STATUS_DPLLENS_DEFAULT (_CMU_STATUS_DPLLENS_DEFAULT << 12)
1012 #define CMU_STATUS_DPLLRDY (0x1UL << 13)
1013 #define _CMU_STATUS_DPLLRDY_SHIFT 13
1014 #define _CMU_STATUS_DPLLRDY_MASK 0x2000UL
1015 #define _CMU_STATUS_DPLLRDY_DEFAULT 0x00000000UL
1016 #define CMU_STATUS_DPLLRDY_DEFAULT (_CMU_STATUS_DPLLRDY_DEFAULT << 13)
1017 #define CMU_STATUS_CALRDY (0x1UL << 16)
1018 #define _CMU_STATUS_CALRDY_SHIFT 16
1019 #define _CMU_STATUS_CALRDY_MASK 0x10000UL
1020 #define _CMU_STATUS_CALRDY_DEFAULT 0x00000001UL
1021 #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 16)
1022 #define CMU_STATUS_HFXOREQ (0x1UL << 21)
1023 #define _CMU_STATUS_HFXOREQ_SHIFT 21
1024 #define _CMU_STATUS_HFXOREQ_MASK 0x200000UL
1025 #define _CMU_STATUS_HFXOREQ_DEFAULT 0x00000000UL
1026 #define CMU_STATUS_HFXOREQ_DEFAULT (_CMU_STATUS_HFXOREQ_DEFAULT << 21)
1027 #define CMU_STATUS_HFXOPEAKDETRDY (0x1UL << 22)
1028 #define _CMU_STATUS_HFXOPEAKDETRDY_SHIFT 22
1029 #define _CMU_STATUS_HFXOPEAKDETRDY_MASK 0x400000UL
1030 #define _CMU_STATUS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
1031 #define CMU_STATUS_HFXOPEAKDETRDY_DEFAULT (_CMU_STATUS_HFXOPEAKDETRDY_DEFAULT << 22)
1032 #define CMU_STATUS_HFXOSHUNTOPTRDY (0x1UL << 23)
1033 #define _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT 23
1034 #define _CMU_STATUS_HFXOSHUNTOPTRDY_MASK 0x800000UL
1035 #define _CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1036 #define CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_STATUS_HFXOSHUNTOPTRDY_DEFAULT << 23)
1037 #define CMU_STATUS_HFXOAMPHIGH (0x1UL << 24)
1038 #define _CMU_STATUS_HFXOAMPHIGH_SHIFT 24
1039 #define _CMU_STATUS_HFXOAMPHIGH_MASK 0x1000000UL
1040 #define _CMU_STATUS_HFXOAMPHIGH_DEFAULT 0x00000000UL
1041 #define CMU_STATUS_HFXOAMPHIGH_DEFAULT (_CMU_STATUS_HFXOAMPHIGH_DEFAULT << 24)
1042 #define CMU_STATUS_HFXOAMPLOW (0x1UL << 25)
1043 #define _CMU_STATUS_HFXOAMPLOW_SHIFT 25
1044 #define _CMU_STATUS_HFXOAMPLOW_MASK 0x2000000UL
1045 #define _CMU_STATUS_HFXOAMPLOW_DEFAULT 0x00000000UL
1046 #define CMU_STATUS_HFXOAMPLOW_DEFAULT (_CMU_STATUS_HFXOAMPLOW_DEFAULT << 25)
1047 #define CMU_STATUS_HFXOREGILOW (0x1UL << 26)
1048 #define _CMU_STATUS_HFXOREGILOW_SHIFT 26
1049 #define _CMU_STATUS_HFXOREGILOW_MASK 0x4000000UL
1050 #define _CMU_STATUS_HFXOREGILOW_DEFAULT 0x00000000UL
1051 #define CMU_STATUS_HFXOREGILOW_DEFAULT (_CMU_STATUS_HFXOREGILOW_DEFAULT << 26)
1052 #define CMU_STATUS_LFXOPHASE (0x1UL << 27)
1053 #define _CMU_STATUS_LFXOPHASE_SHIFT 27
1054 #define _CMU_STATUS_LFXOPHASE_MASK 0x8000000UL
1055 #define _CMU_STATUS_LFXOPHASE_DEFAULT 0x00000000UL
1056 #define CMU_STATUS_LFXOPHASE_DEFAULT (_CMU_STATUS_LFXOPHASE_DEFAULT << 27)
1057 #define CMU_STATUS_LFRCOPHASE (0x1UL << 28)
1058 #define _CMU_STATUS_LFRCOPHASE_SHIFT 28
1059 #define _CMU_STATUS_LFRCOPHASE_MASK 0x10000000UL
1060 #define _CMU_STATUS_LFRCOPHASE_DEFAULT 0x00000000UL
1061 #define CMU_STATUS_LFRCOPHASE_DEFAULT (_CMU_STATUS_LFRCOPHASE_DEFAULT << 28)
1062 #define CMU_STATUS_ULFRCOPHASE (0x1UL << 29)
1063 #define _CMU_STATUS_ULFRCOPHASE_SHIFT 29
1064 #define _CMU_STATUS_ULFRCOPHASE_MASK 0x20000000UL
1065 #define _CMU_STATUS_ULFRCOPHASE_DEFAULT 0x00000000UL
1066 #define CMU_STATUS_ULFRCOPHASE_DEFAULT (_CMU_STATUS_ULFRCOPHASE_DEFAULT << 29)
1068 /* Bit fields for CMU HFCLKSTATUS */
1069 #define _CMU_HFCLKSTATUS_RESETVALUE 0x00000001UL
1070 #define _CMU_HFCLKSTATUS_MASK 0x00000007UL
1071 #define _CMU_HFCLKSTATUS_SELECTED_SHIFT 0
1072 #define _CMU_HFCLKSTATUS_SELECTED_MASK 0x7UL
1073 #define _CMU_HFCLKSTATUS_SELECTED_DEFAULT 0x00000001UL
1074 #define _CMU_HFCLKSTATUS_SELECTED_HFRCO 0x00000001UL
1075 #define _CMU_HFCLKSTATUS_SELECTED_HFXO 0x00000002UL
1076 #define _CMU_HFCLKSTATUS_SELECTED_LFRCO 0x00000003UL
1077 #define _CMU_HFCLKSTATUS_SELECTED_LFXO 0x00000004UL
1078 #define _CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 0x00000005UL
1079 #define _CMU_HFCLKSTATUS_SELECTED_CLKIN0 0x00000007UL
1080 #define CMU_HFCLKSTATUS_SELECTED_DEFAULT (_CMU_HFCLKSTATUS_SELECTED_DEFAULT << 0)
1081 #define CMU_HFCLKSTATUS_SELECTED_HFRCO (_CMU_HFCLKSTATUS_SELECTED_HFRCO << 0)
1082 #define CMU_HFCLKSTATUS_SELECTED_HFXO (_CMU_HFCLKSTATUS_SELECTED_HFXO << 0)
1083 #define CMU_HFCLKSTATUS_SELECTED_LFRCO (_CMU_HFCLKSTATUS_SELECTED_LFRCO << 0)
1084 #define CMU_HFCLKSTATUS_SELECTED_LFXO (_CMU_HFCLKSTATUS_SELECTED_LFXO << 0)
1085 #define CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 (_CMU_HFCLKSTATUS_SELECTED_HFRCODIV2 << 0)
1086 #define CMU_HFCLKSTATUS_SELECTED_CLKIN0 (_CMU_HFCLKSTATUS_SELECTED_CLKIN0 << 0)
1088 /* Bit fields for CMU HFXOTRIMSTATUS */
1089 #define _CMU_HFXOTRIMSTATUS_RESETVALUE 0x00000500UL
1090 #define _CMU_HFXOTRIMSTATUS_MASK 0x000007FFUL
1091 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_SHIFT 0
1092 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK 0x7FUL
1093 #define _CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT 0x00000000UL
1094 #define CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_DEFAULT << 0)
1095 #define _CMU_HFXOTRIMSTATUS_REGISH_SHIFT 7
1096 #define _CMU_HFXOTRIMSTATUS_REGISH_MASK 0x780UL
1097 #define _CMU_HFXOTRIMSTATUS_REGISH_DEFAULT 0x0000000AUL
1098 #define CMU_HFXOTRIMSTATUS_REGISH_DEFAULT (_CMU_HFXOTRIMSTATUS_REGISH_DEFAULT << 7)
1100 /* Bit fields for CMU IF */
1101 #define _CMU_IF_RESETVALUE 0x00000001UL
1102 #define _CMU_IF_MASK 0xB803FF7FUL
1103 #define CMU_IF_HFRCORDY (0x1UL << 0)
1104 #define _CMU_IF_HFRCORDY_SHIFT 0
1105 #define _CMU_IF_HFRCORDY_MASK 0x1UL
1106 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
1107 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
1108 #define CMU_IF_HFXORDY (0x1UL << 1)
1109 #define _CMU_IF_HFXORDY_SHIFT 1
1110 #define _CMU_IF_HFXORDY_MASK 0x2UL
1111 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
1112 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
1113 #define CMU_IF_LFRCORDY (0x1UL << 2)
1114 #define _CMU_IF_LFRCORDY_SHIFT 2
1115 #define _CMU_IF_LFRCORDY_MASK 0x4UL
1116 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
1117 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
1118 #define CMU_IF_LFXORDY (0x1UL << 3)
1119 #define _CMU_IF_LFXORDY_SHIFT 3
1120 #define _CMU_IF_LFXORDY_MASK 0x8UL
1121 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
1122 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
1123 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
1124 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
1125 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
1126 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
1127 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
1128 #define CMU_IF_CALRDY (0x1UL << 5)
1129 #define _CMU_IF_CALRDY_SHIFT 5
1130 #define _CMU_IF_CALRDY_MASK 0x20UL
1131 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
1132 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
1133 #define CMU_IF_CALOF (0x1UL << 6)
1134 #define _CMU_IF_CALOF_SHIFT 6
1135 #define _CMU_IF_CALOF_MASK 0x40UL
1136 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL
1137 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)
1138 #define CMU_IF_HFXODISERR (0x1UL << 8)
1139 #define _CMU_IF_HFXODISERR_SHIFT 8
1140 #define _CMU_IF_HFXODISERR_MASK 0x100UL
1141 #define _CMU_IF_HFXODISERR_DEFAULT 0x00000000UL
1142 #define CMU_IF_HFXODISERR_DEFAULT (_CMU_IF_HFXODISERR_DEFAULT << 8)
1143 #define CMU_IF_HFXOAUTOSW (0x1UL << 9)
1144 #define _CMU_IF_HFXOAUTOSW_SHIFT 9
1145 #define _CMU_IF_HFXOAUTOSW_MASK 0x200UL
1146 #define _CMU_IF_HFXOAUTOSW_DEFAULT 0x00000000UL
1147 #define CMU_IF_HFXOAUTOSW_DEFAULT (_CMU_IF_HFXOAUTOSW_DEFAULT << 9)
1148 #define CMU_IF_HFXOPEAKDETERR (0x1UL << 10)
1149 #define _CMU_IF_HFXOPEAKDETERR_SHIFT 10
1150 #define _CMU_IF_HFXOPEAKDETERR_MASK 0x400UL
1151 #define _CMU_IF_HFXOPEAKDETERR_DEFAULT 0x00000000UL
1152 #define CMU_IF_HFXOPEAKDETERR_DEFAULT (_CMU_IF_HFXOPEAKDETERR_DEFAULT << 10)
1153 #define CMU_IF_HFXOPEAKDETRDY (0x1UL << 11)
1154 #define _CMU_IF_HFXOPEAKDETRDY_SHIFT 11
1155 #define _CMU_IF_HFXOPEAKDETRDY_MASK 0x800UL
1156 #define _CMU_IF_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
1157 #define CMU_IF_HFXOPEAKDETRDY_DEFAULT (_CMU_IF_HFXOPEAKDETRDY_DEFAULT << 11)
1158 #define CMU_IF_HFXOSHUNTOPTRDY (0x1UL << 12)
1159 #define _CMU_IF_HFXOSHUNTOPTRDY_SHIFT 12
1160 #define _CMU_IF_HFXOSHUNTOPTRDY_MASK 0x1000UL
1161 #define _CMU_IF_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1162 #define CMU_IF_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IF_HFXOSHUNTOPTRDY_DEFAULT << 12)
1163 #define CMU_IF_HFRCODIS (0x1UL << 13)
1164 #define _CMU_IF_HFRCODIS_SHIFT 13
1165 #define _CMU_IF_HFRCODIS_MASK 0x2000UL
1166 #define _CMU_IF_HFRCODIS_DEFAULT 0x00000000UL
1167 #define CMU_IF_HFRCODIS_DEFAULT (_CMU_IF_HFRCODIS_DEFAULT << 13)
1168 #define CMU_IF_LFTIMEOUTERR (0x1UL << 14)
1169 #define _CMU_IF_LFTIMEOUTERR_SHIFT 14
1170 #define _CMU_IF_LFTIMEOUTERR_MASK 0x4000UL
1171 #define _CMU_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL
1172 #define CMU_IF_LFTIMEOUTERR_DEFAULT (_CMU_IF_LFTIMEOUTERR_DEFAULT << 14)
1173 #define CMU_IF_DPLLRDY (0x1UL << 15)
1174 #define _CMU_IF_DPLLRDY_SHIFT 15
1175 #define _CMU_IF_DPLLRDY_MASK 0x8000UL
1176 #define _CMU_IF_DPLLRDY_DEFAULT 0x00000000UL
1177 #define CMU_IF_DPLLRDY_DEFAULT (_CMU_IF_DPLLRDY_DEFAULT << 15)
1178 #define CMU_IF_DPLLLOCKFAILLOW (0x1UL << 16)
1179 #define _CMU_IF_DPLLLOCKFAILLOW_SHIFT 16
1180 #define _CMU_IF_DPLLLOCKFAILLOW_MASK 0x10000UL
1181 #define _CMU_IF_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL
1182 #define CMU_IF_DPLLLOCKFAILLOW_DEFAULT (_CMU_IF_DPLLLOCKFAILLOW_DEFAULT << 16)
1183 #define CMU_IF_DPLLLOCKFAILHIGH (0x1UL << 17)
1184 #define _CMU_IF_DPLLLOCKFAILHIGH_SHIFT 17
1185 #define _CMU_IF_DPLLLOCKFAILHIGH_MASK 0x20000UL
1186 #define _CMU_IF_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL
1187 #define CMU_IF_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IF_DPLLLOCKFAILHIGH_DEFAULT << 17)
1188 #define CMU_IF_LFXOEDGE (0x1UL << 27)
1189 #define _CMU_IF_LFXOEDGE_SHIFT 27
1190 #define _CMU_IF_LFXOEDGE_MASK 0x8000000UL
1191 #define _CMU_IF_LFXOEDGE_DEFAULT 0x00000000UL
1192 #define CMU_IF_LFXOEDGE_DEFAULT (_CMU_IF_LFXOEDGE_DEFAULT << 27)
1193 #define CMU_IF_LFRCOEDGE (0x1UL << 28)
1194 #define _CMU_IF_LFRCOEDGE_SHIFT 28
1195 #define _CMU_IF_LFRCOEDGE_MASK 0x10000000UL
1196 #define _CMU_IF_LFRCOEDGE_DEFAULT 0x00000000UL
1197 #define CMU_IF_LFRCOEDGE_DEFAULT (_CMU_IF_LFRCOEDGE_DEFAULT << 28)
1198 #define CMU_IF_ULFRCOEDGE (0x1UL << 29)
1199 #define _CMU_IF_ULFRCOEDGE_SHIFT 29
1200 #define _CMU_IF_ULFRCOEDGE_MASK 0x20000000UL
1201 #define _CMU_IF_ULFRCOEDGE_DEFAULT 0x00000000UL
1202 #define CMU_IF_ULFRCOEDGE_DEFAULT (_CMU_IF_ULFRCOEDGE_DEFAULT << 29)
1203 #define CMU_IF_CMUERR (0x1UL << 31)
1204 #define _CMU_IF_CMUERR_SHIFT 31
1205 #define _CMU_IF_CMUERR_MASK 0x80000000UL
1206 #define _CMU_IF_CMUERR_DEFAULT 0x00000000UL
1207 #define CMU_IF_CMUERR_DEFAULT (_CMU_IF_CMUERR_DEFAULT << 31)
1209 /* Bit fields for CMU IFS */
1210 #define _CMU_IFS_RESETVALUE 0x00000000UL
1211 #define _CMU_IFS_MASK 0xB803FF7FUL
1212 #define CMU_IFS_HFRCORDY (0x1UL << 0)
1213 #define _CMU_IFS_HFRCORDY_SHIFT 0
1214 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
1215 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
1216 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
1217 #define CMU_IFS_HFXORDY (0x1UL << 1)
1218 #define _CMU_IFS_HFXORDY_SHIFT 1
1219 #define _CMU_IFS_HFXORDY_MASK 0x2UL
1220 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
1221 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
1222 #define CMU_IFS_LFRCORDY (0x1UL << 2)
1223 #define _CMU_IFS_LFRCORDY_SHIFT 2
1224 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
1225 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
1226 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
1227 #define CMU_IFS_LFXORDY (0x1UL << 3)
1228 #define _CMU_IFS_LFXORDY_SHIFT 3
1229 #define _CMU_IFS_LFXORDY_MASK 0x8UL
1230 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
1231 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
1232 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
1233 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
1234 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
1235 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
1236 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
1237 #define CMU_IFS_CALRDY (0x1UL << 5)
1238 #define _CMU_IFS_CALRDY_SHIFT 5
1239 #define _CMU_IFS_CALRDY_MASK 0x20UL
1240 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
1241 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
1242 #define CMU_IFS_CALOF (0x1UL << 6)
1243 #define _CMU_IFS_CALOF_SHIFT 6
1244 #define _CMU_IFS_CALOF_MASK 0x40UL
1245 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL
1246 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)
1247 #define CMU_IFS_HFXODISERR (0x1UL << 8)
1248 #define _CMU_IFS_HFXODISERR_SHIFT 8
1249 #define _CMU_IFS_HFXODISERR_MASK 0x100UL
1250 #define _CMU_IFS_HFXODISERR_DEFAULT 0x00000000UL
1251 #define CMU_IFS_HFXODISERR_DEFAULT (_CMU_IFS_HFXODISERR_DEFAULT << 8)
1252 #define CMU_IFS_HFXOAUTOSW (0x1UL << 9)
1253 #define _CMU_IFS_HFXOAUTOSW_SHIFT 9
1254 #define _CMU_IFS_HFXOAUTOSW_MASK 0x200UL
1255 #define _CMU_IFS_HFXOAUTOSW_DEFAULT 0x00000000UL
1256 #define CMU_IFS_HFXOAUTOSW_DEFAULT (_CMU_IFS_HFXOAUTOSW_DEFAULT << 9)
1257 #define CMU_IFS_HFXOPEAKDETERR (0x1UL << 10)
1258 #define _CMU_IFS_HFXOPEAKDETERR_SHIFT 10
1259 #define _CMU_IFS_HFXOPEAKDETERR_MASK 0x400UL
1260 #define _CMU_IFS_HFXOPEAKDETERR_DEFAULT 0x00000000UL
1261 #define CMU_IFS_HFXOPEAKDETERR_DEFAULT (_CMU_IFS_HFXOPEAKDETERR_DEFAULT << 10)
1262 #define CMU_IFS_HFXOPEAKDETRDY (0x1UL << 11)
1263 #define _CMU_IFS_HFXOPEAKDETRDY_SHIFT 11
1264 #define _CMU_IFS_HFXOPEAKDETRDY_MASK 0x800UL
1265 #define _CMU_IFS_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
1266 #define CMU_IFS_HFXOPEAKDETRDY_DEFAULT (_CMU_IFS_HFXOPEAKDETRDY_DEFAULT << 11)
1267 #define CMU_IFS_HFXOSHUNTOPTRDY (0x1UL << 12)
1268 #define _CMU_IFS_HFXOSHUNTOPTRDY_SHIFT 12
1269 #define _CMU_IFS_HFXOSHUNTOPTRDY_MASK 0x1000UL
1270 #define _CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1271 #define CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFS_HFXOSHUNTOPTRDY_DEFAULT << 12)
1272 #define CMU_IFS_HFRCODIS (0x1UL << 13)
1273 #define _CMU_IFS_HFRCODIS_SHIFT 13
1274 #define _CMU_IFS_HFRCODIS_MASK 0x2000UL
1275 #define _CMU_IFS_HFRCODIS_DEFAULT 0x00000000UL
1276 #define CMU_IFS_HFRCODIS_DEFAULT (_CMU_IFS_HFRCODIS_DEFAULT << 13)
1277 #define CMU_IFS_LFTIMEOUTERR (0x1UL << 14)
1278 #define _CMU_IFS_LFTIMEOUTERR_SHIFT 14
1279 #define _CMU_IFS_LFTIMEOUTERR_MASK 0x4000UL
1280 #define _CMU_IFS_LFTIMEOUTERR_DEFAULT 0x00000000UL
1281 #define CMU_IFS_LFTIMEOUTERR_DEFAULT (_CMU_IFS_LFTIMEOUTERR_DEFAULT << 14)
1282 #define CMU_IFS_DPLLRDY (0x1UL << 15)
1283 #define _CMU_IFS_DPLLRDY_SHIFT 15
1284 #define _CMU_IFS_DPLLRDY_MASK 0x8000UL
1285 #define _CMU_IFS_DPLLRDY_DEFAULT 0x00000000UL
1286 #define CMU_IFS_DPLLRDY_DEFAULT (_CMU_IFS_DPLLRDY_DEFAULT << 15)
1287 #define CMU_IFS_DPLLLOCKFAILLOW (0x1UL << 16)
1288 #define _CMU_IFS_DPLLLOCKFAILLOW_SHIFT 16
1289 #define _CMU_IFS_DPLLLOCKFAILLOW_MASK 0x10000UL
1290 #define _CMU_IFS_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL
1291 #define CMU_IFS_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFS_DPLLLOCKFAILLOW_DEFAULT << 16)
1292 #define CMU_IFS_DPLLLOCKFAILHIGH (0x1UL << 17)
1293 #define _CMU_IFS_DPLLLOCKFAILHIGH_SHIFT 17
1294 #define _CMU_IFS_DPLLLOCKFAILHIGH_MASK 0x20000UL
1295 #define _CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL
1296 #define CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFS_DPLLLOCKFAILHIGH_DEFAULT << 17)
1297 #define CMU_IFS_LFXOEDGE (0x1UL << 27)
1298 #define _CMU_IFS_LFXOEDGE_SHIFT 27
1299 #define _CMU_IFS_LFXOEDGE_MASK 0x8000000UL
1300 #define _CMU_IFS_LFXOEDGE_DEFAULT 0x00000000UL
1301 #define CMU_IFS_LFXOEDGE_DEFAULT (_CMU_IFS_LFXOEDGE_DEFAULT << 27)
1302 #define CMU_IFS_LFRCOEDGE (0x1UL << 28)
1303 #define _CMU_IFS_LFRCOEDGE_SHIFT 28
1304 #define _CMU_IFS_LFRCOEDGE_MASK 0x10000000UL
1305 #define _CMU_IFS_LFRCOEDGE_DEFAULT 0x00000000UL
1306 #define CMU_IFS_LFRCOEDGE_DEFAULT (_CMU_IFS_LFRCOEDGE_DEFAULT << 28)
1307 #define CMU_IFS_ULFRCOEDGE (0x1UL << 29)
1308 #define _CMU_IFS_ULFRCOEDGE_SHIFT 29
1309 #define _CMU_IFS_ULFRCOEDGE_MASK 0x20000000UL
1310 #define _CMU_IFS_ULFRCOEDGE_DEFAULT 0x00000000UL
1311 #define CMU_IFS_ULFRCOEDGE_DEFAULT (_CMU_IFS_ULFRCOEDGE_DEFAULT << 29)
1312 #define CMU_IFS_CMUERR (0x1UL << 31)
1313 #define _CMU_IFS_CMUERR_SHIFT 31
1314 #define _CMU_IFS_CMUERR_MASK 0x80000000UL
1315 #define _CMU_IFS_CMUERR_DEFAULT 0x00000000UL
1316 #define CMU_IFS_CMUERR_DEFAULT (_CMU_IFS_CMUERR_DEFAULT << 31)
1318 /* Bit fields for CMU IFC */
1319 #define _CMU_IFC_RESETVALUE 0x00000000UL
1320 #define _CMU_IFC_MASK 0xB803FF7FUL
1321 #define CMU_IFC_HFRCORDY (0x1UL << 0)
1322 #define _CMU_IFC_HFRCORDY_SHIFT 0
1323 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
1324 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
1325 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
1326 #define CMU_IFC_HFXORDY (0x1UL << 1)
1327 #define _CMU_IFC_HFXORDY_SHIFT 1
1328 #define _CMU_IFC_HFXORDY_MASK 0x2UL
1329 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
1330 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
1331 #define CMU_IFC_LFRCORDY (0x1UL << 2)
1332 #define _CMU_IFC_LFRCORDY_SHIFT 2
1333 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
1334 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
1335 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
1336 #define CMU_IFC_LFXORDY (0x1UL << 3)
1337 #define _CMU_IFC_LFXORDY_SHIFT 3
1338 #define _CMU_IFC_LFXORDY_MASK 0x8UL
1339 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
1340 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
1341 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
1342 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
1343 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
1344 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
1345 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
1346 #define CMU_IFC_CALRDY (0x1UL << 5)
1347 #define _CMU_IFC_CALRDY_SHIFT 5
1348 #define _CMU_IFC_CALRDY_MASK 0x20UL
1349 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
1350 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
1351 #define CMU_IFC_CALOF (0x1UL << 6)
1352 #define _CMU_IFC_CALOF_SHIFT 6
1353 #define _CMU_IFC_CALOF_MASK 0x40UL
1354 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL
1355 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)
1356 #define CMU_IFC_HFXODISERR (0x1UL << 8)
1357 #define _CMU_IFC_HFXODISERR_SHIFT 8
1358 #define _CMU_IFC_HFXODISERR_MASK 0x100UL
1359 #define _CMU_IFC_HFXODISERR_DEFAULT 0x00000000UL
1360 #define CMU_IFC_HFXODISERR_DEFAULT (_CMU_IFC_HFXODISERR_DEFAULT << 8)
1361 #define CMU_IFC_HFXOAUTOSW (0x1UL << 9)
1362 #define _CMU_IFC_HFXOAUTOSW_SHIFT 9
1363 #define _CMU_IFC_HFXOAUTOSW_MASK 0x200UL
1364 #define _CMU_IFC_HFXOAUTOSW_DEFAULT 0x00000000UL
1365 #define CMU_IFC_HFXOAUTOSW_DEFAULT (_CMU_IFC_HFXOAUTOSW_DEFAULT << 9)
1366 #define CMU_IFC_HFXOPEAKDETERR (0x1UL << 10)
1367 #define _CMU_IFC_HFXOPEAKDETERR_SHIFT 10
1368 #define _CMU_IFC_HFXOPEAKDETERR_MASK 0x400UL
1369 #define _CMU_IFC_HFXOPEAKDETERR_DEFAULT 0x00000000UL
1370 #define CMU_IFC_HFXOPEAKDETERR_DEFAULT (_CMU_IFC_HFXOPEAKDETERR_DEFAULT << 10)
1371 #define CMU_IFC_HFXOPEAKDETRDY (0x1UL << 11)
1372 #define _CMU_IFC_HFXOPEAKDETRDY_SHIFT 11
1373 #define _CMU_IFC_HFXOPEAKDETRDY_MASK 0x800UL
1374 #define _CMU_IFC_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
1375 #define CMU_IFC_HFXOPEAKDETRDY_DEFAULT (_CMU_IFC_HFXOPEAKDETRDY_DEFAULT << 11)
1376 #define CMU_IFC_HFXOSHUNTOPTRDY (0x1UL << 12)
1377 #define _CMU_IFC_HFXOSHUNTOPTRDY_SHIFT 12
1378 #define _CMU_IFC_HFXOSHUNTOPTRDY_MASK 0x1000UL
1379 #define _CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1380 #define CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IFC_HFXOSHUNTOPTRDY_DEFAULT << 12)
1381 #define CMU_IFC_HFRCODIS (0x1UL << 13)
1382 #define _CMU_IFC_HFRCODIS_SHIFT 13
1383 #define _CMU_IFC_HFRCODIS_MASK 0x2000UL
1384 #define _CMU_IFC_HFRCODIS_DEFAULT 0x00000000UL
1385 #define CMU_IFC_HFRCODIS_DEFAULT (_CMU_IFC_HFRCODIS_DEFAULT << 13)
1386 #define CMU_IFC_LFTIMEOUTERR (0x1UL << 14)
1387 #define _CMU_IFC_LFTIMEOUTERR_SHIFT 14
1388 #define _CMU_IFC_LFTIMEOUTERR_MASK 0x4000UL
1389 #define _CMU_IFC_LFTIMEOUTERR_DEFAULT 0x00000000UL
1390 #define CMU_IFC_LFTIMEOUTERR_DEFAULT (_CMU_IFC_LFTIMEOUTERR_DEFAULT << 14)
1391 #define CMU_IFC_DPLLRDY (0x1UL << 15)
1392 #define _CMU_IFC_DPLLRDY_SHIFT 15
1393 #define _CMU_IFC_DPLLRDY_MASK 0x8000UL
1394 #define _CMU_IFC_DPLLRDY_DEFAULT 0x00000000UL
1395 #define CMU_IFC_DPLLRDY_DEFAULT (_CMU_IFC_DPLLRDY_DEFAULT << 15)
1396 #define CMU_IFC_DPLLLOCKFAILLOW (0x1UL << 16)
1397 #define _CMU_IFC_DPLLLOCKFAILLOW_SHIFT 16
1398 #define _CMU_IFC_DPLLLOCKFAILLOW_MASK 0x10000UL
1399 #define _CMU_IFC_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL
1400 #define CMU_IFC_DPLLLOCKFAILLOW_DEFAULT (_CMU_IFC_DPLLLOCKFAILLOW_DEFAULT << 16)
1401 #define CMU_IFC_DPLLLOCKFAILHIGH (0x1UL << 17)
1402 #define _CMU_IFC_DPLLLOCKFAILHIGH_SHIFT 17
1403 #define _CMU_IFC_DPLLLOCKFAILHIGH_MASK 0x20000UL
1404 #define _CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL
1405 #define CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IFC_DPLLLOCKFAILHIGH_DEFAULT << 17)
1406 #define CMU_IFC_LFXOEDGE (0x1UL << 27)
1407 #define _CMU_IFC_LFXOEDGE_SHIFT 27
1408 #define _CMU_IFC_LFXOEDGE_MASK 0x8000000UL
1409 #define _CMU_IFC_LFXOEDGE_DEFAULT 0x00000000UL
1410 #define CMU_IFC_LFXOEDGE_DEFAULT (_CMU_IFC_LFXOEDGE_DEFAULT << 27)
1411 #define CMU_IFC_LFRCOEDGE (0x1UL << 28)
1412 #define _CMU_IFC_LFRCOEDGE_SHIFT 28
1413 #define _CMU_IFC_LFRCOEDGE_MASK 0x10000000UL
1414 #define _CMU_IFC_LFRCOEDGE_DEFAULT 0x00000000UL
1415 #define CMU_IFC_LFRCOEDGE_DEFAULT (_CMU_IFC_LFRCOEDGE_DEFAULT << 28)
1416 #define CMU_IFC_ULFRCOEDGE (0x1UL << 29)
1417 #define _CMU_IFC_ULFRCOEDGE_SHIFT 29
1418 #define _CMU_IFC_ULFRCOEDGE_MASK 0x20000000UL
1419 #define _CMU_IFC_ULFRCOEDGE_DEFAULT 0x00000000UL
1420 #define CMU_IFC_ULFRCOEDGE_DEFAULT (_CMU_IFC_ULFRCOEDGE_DEFAULT << 29)
1421 #define CMU_IFC_CMUERR (0x1UL << 31)
1422 #define _CMU_IFC_CMUERR_SHIFT 31
1423 #define _CMU_IFC_CMUERR_MASK 0x80000000UL
1424 #define _CMU_IFC_CMUERR_DEFAULT 0x00000000UL
1425 #define CMU_IFC_CMUERR_DEFAULT (_CMU_IFC_CMUERR_DEFAULT << 31)
1427 /* Bit fields for CMU IEN */
1428 #define _CMU_IEN_RESETVALUE 0x00000000UL
1429 #define _CMU_IEN_MASK 0xB803FF7FUL
1430 #define CMU_IEN_HFRCORDY (0x1UL << 0)
1431 #define _CMU_IEN_HFRCORDY_SHIFT 0
1432 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
1433 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
1434 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
1435 #define CMU_IEN_HFXORDY (0x1UL << 1)
1436 #define _CMU_IEN_HFXORDY_SHIFT 1
1437 #define _CMU_IEN_HFXORDY_MASK 0x2UL
1438 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
1439 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
1440 #define CMU_IEN_LFRCORDY (0x1UL << 2)
1441 #define _CMU_IEN_LFRCORDY_SHIFT 2
1442 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
1443 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
1444 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
1445 #define CMU_IEN_LFXORDY (0x1UL << 3)
1446 #define _CMU_IEN_LFXORDY_SHIFT 3
1447 #define _CMU_IEN_LFXORDY_MASK 0x8UL
1448 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
1449 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
1450 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
1451 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
1452 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
1453 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
1454 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
1455 #define CMU_IEN_CALRDY (0x1UL << 5)
1456 #define _CMU_IEN_CALRDY_SHIFT 5
1457 #define _CMU_IEN_CALRDY_MASK 0x20UL
1458 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
1459 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
1460 #define CMU_IEN_CALOF (0x1UL << 6)
1461 #define _CMU_IEN_CALOF_SHIFT 6
1462 #define _CMU_IEN_CALOF_MASK 0x40UL
1463 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL
1464 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)
1465 #define CMU_IEN_HFXODISERR (0x1UL << 8)
1466 #define _CMU_IEN_HFXODISERR_SHIFT 8
1467 #define _CMU_IEN_HFXODISERR_MASK 0x100UL
1468 #define _CMU_IEN_HFXODISERR_DEFAULT 0x00000000UL
1469 #define CMU_IEN_HFXODISERR_DEFAULT (_CMU_IEN_HFXODISERR_DEFAULT << 8)
1470 #define CMU_IEN_HFXOAUTOSW (0x1UL << 9)
1471 #define _CMU_IEN_HFXOAUTOSW_SHIFT 9
1472 #define _CMU_IEN_HFXOAUTOSW_MASK 0x200UL
1473 #define _CMU_IEN_HFXOAUTOSW_DEFAULT 0x00000000UL
1474 #define CMU_IEN_HFXOAUTOSW_DEFAULT (_CMU_IEN_HFXOAUTOSW_DEFAULT << 9)
1475 #define CMU_IEN_HFXOPEAKDETERR (0x1UL << 10)
1476 #define _CMU_IEN_HFXOPEAKDETERR_SHIFT 10
1477 #define _CMU_IEN_HFXOPEAKDETERR_MASK 0x400UL
1478 #define _CMU_IEN_HFXOPEAKDETERR_DEFAULT 0x00000000UL
1479 #define CMU_IEN_HFXOPEAKDETERR_DEFAULT (_CMU_IEN_HFXOPEAKDETERR_DEFAULT << 10)
1480 #define CMU_IEN_HFXOPEAKDETRDY (0x1UL << 11)
1481 #define _CMU_IEN_HFXOPEAKDETRDY_SHIFT 11
1482 #define _CMU_IEN_HFXOPEAKDETRDY_MASK 0x800UL
1483 #define _CMU_IEN_HFXOPEAKDETRDY_DEFAULT 0x00000000UL
1484 #define CMU_IEN_HFXOPEAKDETRDY_DEFAULT (_CMU_IEN_HFXOPEAKDETRDY_DEFAULT << 11)
1485 #define CMU_IEN_HFXOSHUNTOPTRDY (0x1UL << 12)
1486 #define _CMU_IEN_HFXOSHUNTOPTRDY_SHIFT 12
1487 #define _CMU_IEN_HFXOSHUNTOPTRDY_MASK 0x1000UL
1488 #define _CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT 0x00000000UL
1489 #define CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT (_CMU_IEN_HFXOSHUNTOPTRDY_DEFAULT << 12)
1490 #define CMU_IEN_HFRCODIS (0x1UL << 13)
1491 #define _CMU_IEN_HFRCODIS_SHIFT 13
1492 #define _CMU_IEN_HFRCODIS_MASK 0x2000UL
1493 #define _CMU_IEN_HFRCODIS_DEFAULT 0x00000000UL
1494 #define CMU_IEN_HFRCODIS_DEFAULT (_CMU_IEN_HFRCODIS_DEFAULT << 13)
1495 #define CMU_IEN_LFTIMEOUTERR (0x1UL << 14)
1496 #define _CMU_IEN_LFTIMEOUTERR_SHIFT 14
1497 #define _CMU_IEN_LFTIMEOUTERR_MASK 0x4000UL
1498 #define _CMU_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL
1499 #define CMU_IEN_LFTIMEOUTERR_DEFAULT (_CMU_IEN_LFTIMEOUTERR_DEFAULT << 14)
1500 #define CMU_IEN_DPLLRDY (0x1UL << 15)
1501 #define _CMU_IEN_DPLLRDY_SHIFT 15
1502 #define _CMU_IEN_DPLLRDY_MASK 0x8000UL
1503 #define _CMU_IEN_DPLLRDY_DEFAULT 0x00000000UL
1504 #define CMU_IEN_DPLLRDY_DEFAULT (_CMU_IEN_DPLLRDY_DEFAULT << 15)
1505 #define CMU_IEN_DPLLLOCKFAILLOW (0x1UL << 16)
1506 #define _CMU_IEN_DPLLLOCKFAILLOW_SHIFT 16
1507 #define _CMU_IEN_DPLLLOCKFAILLOW_MASK 0x10000UL
1508 #define _CMU_IEN_DPLLLOCKFAILLOW_DEFAULT 0x00000000UL
1509 #define CMU_IEN_DPLLLOCKFAILLOW_DEFAULT (_CMU_IEN_DPLLLOCKFAILLOW_DEFAULT << 16)
1510 #define CMU_IEN_DPLLLOCKFAILHIGH (0x1UL << 17)
1511 #define _CMU_IEN_DPLLLOCKFAILHIGH_SHIFT 17
1512 #define _CMU_IEN_DPLLLOCKFAILHIGH_MASK 0x20000UL
1513 #define _CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT 0x00000000UL
1514 #define CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT (_CMU_IEN_DPLLLOCKFAILHIGH_DEFAULT << 17)
1515 #define CMU_IEN_LFXOEDGE (0x1UL << 27)
1516 #define _CMU_IEN_LFXOEDGE_SHIFT 27
1517 #define _CMU_IEN_LFXOEDGE_MASK 0x8000000UL
1518 #define _CMU_IEN_LFXOEDGE_DEFAULT 0x00000000UL
1519 #define CMU_IEN_LFXOEDGE_DEFAULT (_CMU_IEN_LFXOEDGE_DEFAULT << 27)
1520 #define CMU_IEN_LFRCOEDGE (0x1UL << 28)
1521 #define _CMU_IEN_LFRCOEDGE_SHIFT 28
1522 #define _CMU_IEN_LFRCOEDGE_MASK 0x10000000UL
1523 #define _CMU_IEN_LFRCOEDGE_DEFAULT 0x00000000UL
1524 #define CMU_IEN_LFRCOEDGE_DEFAULT (_CMU_IEN_LFRCOEDGE_DEFAULT << 28)
1525 #define CMU_IEN_ULFRCOEDGE (0x1UL << 29)
1526 #define _CMU_IEN_ULFRCOEDGE_SHIFT 29
1527 #define _CMU_IEN_ULFRCOEDGE_MASK 0x20000000UL
1528 #define _CMU_IEN_ULFRCOEDGE_DEFAULT 0x00000000UL
1529 #define CMU_IEN_ULFRCOEDGE_DEFAULT (_CMU_IEN_ULFRCOEDGE_DEFAULT << 29)
1530 #define CMU_IEN_CMUERR (0x1UL << 31)
1531 #define _CMU_IEN_CMUERR_SHIFT 31
1532 #define _CMU_IEN_CMUERR_MASK 0x80000000UL
1533 #define _CMU_IEN_CMUERR_DEFAULT 0x00000000UL
1534 #define CMU_IEN_CMUERR_DEFAULT (_CMU_IEN_CMUERR_DEFAULT << 31)
1536 /* Bit fields for CMU HFBUSCLKEN0 */
1537 #define _CMU_HFBUSCLKEN0_RESETVALUE 0x00000000UL
1538 #define _CMU_HFBUSCLKEN0_MASK 0x0000007FUL
1539 #define CMU_HFBUSCLKEN0_CRYPTO0 (0x1UL << 0)
1540 #define CMU_HFBUSCLKEN0_CRYPTO CMU_HFBUSCLKEN0_CRYPTO0
1541 #define _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT 0
1542 #define _CMU_HFBUSCLKEN0_CRYPTO0_MASK 0x1UL
1543 #define _CMU_HFBUSCLKEN0_CRYPTO_SHIFT _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT
1544 #define _CMU_HFBUSCLKEN0_CRYPTO_MASK _CMU_HFBUSCLKEN0_CRYPTO0_MASK
1545 #define _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT 0x00000000UL
1546 #define _CMU_HFBUSCLKEN0_CRYPTO_DEFAULT _CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT
1547 #define CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT << 0)
1548 #define CMU_HFBUSCLKEN0_CRYPTO_DEFAULT CMU_HFBUSCLKEN0_CRYPTO0_DEFAULT
1549 #define CMU_HFBUSCLKEN0_CRYPTO1 (0x1UL << 1)
1550 #define _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT 1
1551 #define _CMU_HFBUSCLKEN0_CRYPTO1_MASK 0x2UL
1552 #define _CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT 0x00000000UL
1553 #define CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT (_CMU_HFBUSCLKEN0_CRYPTO1_DEFAULT << 1)
1554 #define CMU_HFBUSCLKEN0_LE (0x1UL << 2)
1555 #define _CMU_HFBUSCLKEN0_LE_SHIFT 2
1556 #define _CMU_HFBUSCLKEN0_LE_MASK 0x4UL
1557 #define _CMU_HFBUSCLKEN0_LE_DEFAULT 0x00000000UL
1558 #define CMU_HFBUSCLKEN0_LE_DEFAULT (_CMU_HFBUSCLKEN0_LE_DEFAULT << 2)
1559 #define CMU_HFBUSCLKEN0_GPIO (0x1UL << 3)
1560 #define _CMU_HFBUSCLKEN0_GPIO_SHIFT 3
1561 #define _CMU_HFBUSCLKEN0_GPIO_MASK 0x8UL
1562 #define _CMU_HFBUSCLKEN0_GPIO_DEFAULT 0x00000000UL
1563 #define CMU_HFBUSCLKEN0_GPIO_DEFAULT (_CMU_HFBUSCLKEN0_GPIO_DEFAULT << 3)
1564 #define CMU_HFBUSCLKEN0_PRS (0x1UL << 4)
1565 #define _CMU_HFBUSCLKEN0_PRS_SHIFT 4
1566 #define _CMU_HFBUSCLKEN0_PRS_MASK 0x10UL
1567 #define _CMU_HFBUSCLKEN0_PRS_DEFAULT 0x00000000UL
1568 #define CMU_HFBUSCLKEN0_PRS_DEFAULT (_CMU_HFBUSCLKEN0_PRS_DEFAULT << 4)
1569 #define CMU_HFBUSCLKEN0_LDMA (0x1UL << 5)
1570 #define _CMU_HFBUSCLKEN0_LDMA_SHIFT 5
1571 #define _CMU_HFBUSCLKEN0_LDMA_MASK 0x20UL
1572 #define _CMU_HFBUSCLKEN0_LDMA_DEFAULT 0x00000000UL
1573 #define CMU_HFBUSCLKEN0_LDMA_DEFAULT (_CMU_HFBUSCLKEN0_LDMA_DEFAULT << 5)
1574 #define CMU_HFBUSCLKEN0_GPCRC (0x1UL << 6)
1575 #define _CMU_HFBUSCLKEN0_GPCRC_SHIFT 6
1576 #define _CMU_HFBUSCLKEN0_GPCRC_MASK 0x40UL
1577 #define _CMU_HFBUSCLKEN0_GPCRC_DEFAULT 0x00000000UL
1578 #define CMU_HFBUSCLKEN0_GPCRC_DEFAULT (_CMU_HFBUSCLKEN0_GPCRC_DEFAULT << 6)
1580 /* Bit fields for CMU HFPERCLKEN0 */
1581 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
1582 #define _CMU_HFPERCLKEN0_MASK 0x0000FFFFUL
1583 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0)
1584 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0
1585 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL
1586 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
1587 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0)
1588 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1)
1589 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1
1590 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL
1591 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
1592 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1)
1593 #define CMU_HFPERCLKEN0_WTIMER0 (0x1UL << 2)
1594 #define _CMU_HFPERCLKEN0_WTIMER0_SHIFT 2
1595 #define _CMU_HFPERCLKEN0_WTIMER0_MASK 0x4UL
1596 #define _CMU_HFPERCLKEN0_WTIMER0_DEFAULT 0x00000000UL
1597 #define CMU_HFPERCLKEN0_WTIMER0_DEFAULT (_CMU_HFPERCLKEN0_WTIMER0_DEFAULT << 2)
1598 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 3)
1599 #define _CMU_HFPERCLKEN0_USART0_SHIFT 3
1600 #define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL
1601 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
1602 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3)
1603 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 4)
1604 #define _CMU_HFPERCLKEN0_USART1_SHIFT 4
1605 #define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL
1606 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
1607 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4)
1608 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 5)
1609 #define _CMU_HFPERCLKEN0_USART2_SHIFT 5
1610 #define _CMU_HFPERCLKEN0_USART2_MASK 0x20UL
1611 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL
1612 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 5)
1613 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 6)
1614 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 6
1615 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x40UL
1616 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
1617 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 6)
1618 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 7)
1619 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 7
1620 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x80UL
1621 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL
1622 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 7)
1623 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 8)
1624 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 8
1625 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x100UL
1626 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
1627 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 8)
1628 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 9)
1629 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 9
1630 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x200UL
1631 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
1632 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 9)
1633 #define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 10)
1634 #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 10
1635 #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x400UL
1636 #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL
1637 #define CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT (_CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT << 10)
1638 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 11)
1639 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 11
1640 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x800UL
1641 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
1642 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 11)
1643 #define CMU_HFPERCLKEN0_VDAC0 (0x1UL << 12)
1644 #define _CMU_HFPERCLKEN0_VDAC0_SHIFT 12
1645 #define _CMU_HFPERCLKEN0_VDAC0_MASK 0x1000UL
1646 #define _CMU_HFPERCLKEN0_VDAC0_DEFAULT 0x00000000UL
1647 #define CMU_HFPERCLKEN0_VDAC0_DEFAULT (_CMU_HFPERCLKEN0_VDAC0_DEFAULT << 12)
1648 #define CMU_HFPERCLKEN0_CSEN (0x1UL << 13)
1649 #define _CMU_HFPERCLKEN0_CSEN_SHIFT 13
1650 #define _CMU_HFPERCLKEN0_CSEN_MASK 0x2000UL
1651 #define _CMU_HFPERCLKEN0_CSEN_DEFAULT 0x00000000UL
1652 #define CMU_HFPERCLKEN0_CSEN_DEFAULT (_CMU_HFPERCLKEN0_CSEN_DEFAULT << 13)
1653 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 14)
1654 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 14
1655 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x4000UL
1656 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL
1657 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 14)
1658 #define CMU_HFPERCLKEN0_TRNG0 (0x1UL << 15)
1659 #define _CMU_HFPERCLKEN0_TRNG0_SHIFT 15
1660 #define _CMU_HFPERCLKEN0_TRNG0_MASK 0x8000UL
1661 #define _CMU_HFPERCLKEN0_TRNG0_DEFAULT 0x00000000UL
1662 #define CMU_HFPERCLKEN0_TRNG0_DEFAULT (_CMU_HFPERCLKEN0_TRNG0_DEFAULT << 15)
1664 /* Bit fields for CMU LFACLKEN0 */
1665 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
1666 #define _CMU_LFACLKEN0_MASK 0x00000003UL
1667 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 0)
1668 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 0
1669 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x1UL
1670 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
1671 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 0)
1672 #define CMU_LFACLKEN0_LESENSE (0x1UL << 1)
1673 #define _CMU_LFACLKEN0_LESENSE_SHIFT 1
1674 #define _CMU_LFACLKEN0_LESENSE_MASK 0x2UL
1675 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL
1676 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 1)
1678 /* Bit fields for CMU LFBCLKEN0 */
1679 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
1680 #define _CMU_LFBCLKEN0_MASK 0x00000007UL
1681 #define CMU_LFBCLKEN0_SYSTICK (0x1UL << 0)
1682 #define _CMU_LFBCLKEN0_SYSTICK_SHIFT 0
1683 #define _CMU_LFBCLKEN0_SYSTICK_MASK 0x1UL
1684 #define _CMU_LFBCLKEN0_SYSTICK_DEFAULT 0x00000000UL
1685 #define CMU_LFBCLKEN0_SYSTICK_DEFAULT (_CMU_LFBCLKEN0_SYSTICK_DEFAULT << 0)
1686 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 1)
1687 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 1
1688 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x2UL
1689 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
1690 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 1)
1691 #define CMU_LFBCLKEN0_CSEN (0x1UL << 2)
1692 #define _CMU_LFBCLKEN0_CSEN_SHIFT 2
1693 #define _CMU_LFBCLKEN0_CSEN_MASK 0x4UL
1694 #define _CMU_LFBCLKEN0_CSEN_DEFAULT 0x00000000UL
1695 #define CMU_LFBCLKEN0_CSEN_DEFAULT (_CMU_LFBCLKEN0_CSEN_DEFAULT << 2)
1697 /* Bit fields for CMU LFECLKEN0 */
1698 #define _CMU_LFECLKEN0_RESETVALUE 0x00000000UL
1699 #define _CMU_LFECLKEN0_MASK 0x00000001UL
1700 #define CMU_LFECLKEN0_RTCC (0x1UL << 0)
1701 #define _CMU_LFECLKEN0_RTCC_SHIFT 0
1702 #define _CMU_LFECLKEN0_RTCC_MASK 0x1UL
1703 #define _CMU_LFECLKEN0_RTCC_DEFAULT 0x00000000UL
1704 #define CMU_LFECLKEN0_RTCC_DEFAULT (_CMU_LFECLKEN0_RTCC_DEFAULT << 0)
1706 /* Bit fields for CMU HFPRESC */
1707 #define _CMU_HFPRESC_RESETVALUE 0x00000000UL
1708 #define _CMU_HFPRESC_MASK 0x01001F00UL
1709 #define _CMU_HFPRESC_PRESC_SHIFT 8
1710 #define _CMU_HFPRESC_PRESC_MASK 0x1F00UL
1711 #define _CMU_HFPRESC_PRESC_DEFAULT 0x00000000UL
1712 #define _CMU_HFPRESC_PRESC_NODIVISION 0x00000000UL
1713 #define CMU_HFPRESC_PRESC_DEFAULT (_CMU_HFPRESC_PRESC_DEFAULT << 8)
1714 #define CMU_HFPRESC_PRESC_NODIVISION (_CMU_HFPRESC_PRESC_NODIVISION << 8)
1715 #define _CMU_HFPRESC_HFCLKLEPRESC_SHIFT 24
1716 #define _CMU_HFPRESC_HFCLKLEPRESC_MASK 0x1000000UL
1717 #define _CMU_HFPRESC_HFCLKLEPRESC_DEFAULT 0x00000000UL
1718 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV2 0x00000000UL
1719 #define _CMU_HFPRESC_HFCLKLEPRESC_DIV4 0x00000001UL
1720 #define CMU_HFPRESC_HFCLKLEPRESC_DEFAULT (_CMU_HFPRESC_HFCLKLEPRESC_DEFAULT << 24)
1721 #define CMU_HFPRESC_HFCLKLEPRESC_DIV2 (_CMU_HFPRESC_HFCLKLEPRESC_DIV2 << 24)
1722 #define CMU_HFPRESC_HFCLKLEPRESC_DIV4 (_CMU_HFPRESC_HFCLKLEPRESC_DIV4 << 24)
1724 /* Bit fields for CMU HFCOREPRESC */
1725 #define _CMU_HFCOREPRESC_RESETVALUE 0x00000000UL
1726 #define _CMU_HFCOREPRESC_MASK 0x0001FF00UL
1727 #define _CMU_HFCOREPRESC_PRESC_SHIFT 8
1728 #define _CMU_HFCOREPRESC_PRESC_MASK 0x1FF00UL
1729 #define _CMU_HFCOREPRESC_PRESC_DEFAULT 0x00000000UL
1730 #define _CMU_HFCOREPRESC_PRESC_NODIVISION 0x00000000UL
1731 #define CMU_HFCOREPRESC_PRESC_DEFAULT (_CMU_HFCOREPRESC_PRESC_DEFAULT << 8)
1732 #define CMU_HFCOREPRESC_PRESC_NODIVISION (_CMU_HFCOREPRESC_PRESC_NODIVISION << 8)
1734 /* Bit fields for CMU HFPERPRESC */
1735 #define _CMU_HFPERPRESC_RESETVALUE 0x00000000UL
1736 #define _CMU_HFPERPRESC_MASK 0x0001FF00UL
1737 #define _CMU_HFPERPRESC_PRESC_SHIFT 8
1738 #define _CMU_HFPERPRESC_PRESC_MASK 0x1FF00UL
1739 #define _CMU_HFPERPRESC_PRESC_DEFAULT 0x00000000UL
1740 #define _CMU_HFPERPRESC_PRESC_NODIVISION 0x00000000UL
1741 #define CMU_HFPERPRESC_PRESC_DEFAULT (_CMU_HFPERPRESC_PRESC_DEFAULT << 8)
1742 #define CMU_HFPERPRESC_PRESC_NODIVISION (_CMU_HFPERPRESC_PRESC_NODIVISION << 8)
1744 /* Bit fields for CMU HFEXPPRESC */
1745 #define _CMU_HFEXPPRESC_RESETVALUE 0x00000000UL
1746 #define _CMU_HFEXPPRESC_MASK 0x00001F00UL
1747 #define _CMU_HFEXPPRESC_PRESC_SHIFT 8
1748 #define _CMU_HFEXPPRESC_PRESC_MASK 0x1F00UL
1749 #define _CMU_HFEXPPRESC_PRESC_DEFAULT 0x00000000UL
1750 #define _CMU_HFEXPPRESC_PRESC_NODIVISION 0x00000000UL
1751 #define CMU_HFEXPPRESC_PRESC_DEFAULT (_CMU_HFEXPPRESC_PRESC_DEFAULT << 8)
1752 #define CMU_HFEXPPRESC_PRESC_NODIVISION (_CMU_HFEXPPRESC_PRESC_NODIVISION << 8)
1754 /* Bit fields for CMU LFAPRESC0 */
1755 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
1756 #define _CMU_LFAPRESC0_MASK 0x0000003FUL
1757 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 0
1758 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xFUL
1759 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
1760 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
1761 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
1762 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
1763 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
1764 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
1765 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
1766 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
1767 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
1768 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
1769 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
1770 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
1771 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
1772 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
1773 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
1774 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
1775 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 0)
1776 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 0)
1777 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 0)
1778 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 0)
1779 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 0)
1780 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 0)
1781 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 0)
1782 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 0)
1783 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 0)
1784 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 0)
1785 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 0)
1786 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 0)
1787 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 0)
1788 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 0)
1789 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 0)
1790 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 0)
1791 #define _CMU_LFAPRESC0_LESENSE_SHIFT 4
1792 #define _CMU_LFAPRESC0_LESENSE_MASK 0x30UL
1793 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL
1794 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL
1795 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL
1796 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL
1797 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 4)
1798 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 4)
1799 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 4)
1800 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 4)
1802 /* Bit fields for CMU LFBPRESC0 */
1803 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
1804 #define _CMU_LFBPRESC0_MASK 0x0000033FUL
1805 #define _CMU_LFBPRESC0_SYSTICK_SHIFT 0
1806 #define _CMU_LFBPRESC0_SYSTICK_MASK 0xFUL
1807 #define _CMU_LFBPRESC0_SYSTICK_DIV1 0x00000000UL
1808 #define CMU_LFBPRESC0_SYSTICK_DIV1 (_CMU_LFBPRESC0_SYSTICK_DIV1 << 0)
1809 #define _CMU_LFBPRESC0_LEUART0_SHIFT 4
1810 #define _CMU_LFBPRESC0_LEUART0_MASK 0x30UL
1811 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
1812 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
1813 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
1814 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
1815 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 4)
1816 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 4)
1817 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 4)
1818 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 4)
1819 #define _CMU_LFBPRESC0_CSEN_SHIFT 8
1820 #define _CMU_LFBPRESC0_CSEN_MASK 0x300UL
1821 #define _CMU_LFBPRESC0_CSEN_DIV16 0x00000000UL
1822 #define _CMU_LFBPRESC0_CSEN_DIV32 0x00000001UL
1823 #define _CMU_LFBPRESC0_CSEN_DIV64 0x00000002UL
1824 #define _CMU_LFBPRESC0_CSEN_DIV128 0x00000003UL
1825 #define CMU_LFBPRESC0_CSEN_DIV16 (_CMU_LFBPRESC0_CSEN_DIV16 << 8)
1826 #define CMU_LFBPRESC0_CSEN_DIV32 (_CMU_LFBPRESC0_CSEN_DIV32 << 8)
1827 #define CMU_LFBPRESC0_CSEN_DIV64 (_CMU_LFBPRESC0_CSEN_DIV64 << 8)
1828 #define CMU_LFBPRESC0_CSEN_DIV128 (_CMU_LFBPRESC0_CSEN_DIV128 << 8)
1830 /* Bit fields for CMU LFEPRESC0 */
1831 #define _CMU_LFEPRESC0_RESETVALUE 0x00000000UL
1832 #define _CMU_LFEPRESC0_MASK 0x00000003UL
1833 #define _CMU_LFEPRESC0_RTCC_SHIFT 0
1834 #define _CMU_LFEPRESC0_RTCC_MASK 0x3UL
1835 #define _CMU_LFEPRESC0_RTCC_DIV1 0x00000000UL
1836 #define _CMU_LFEPRESC0_RTCC_DIV2 0x00000001UL
1837 #define _CMU_LFEPRESC0_RTCC_DIV4 0x00000002UL
1838 #define CMU_LFEPRESC0_RTCC_DIV1 (_CMU_LFEPRESC0_RTCC_DIV1 << 0)
1839 #define CMU_LFEPRESC0_RTCC_DIV2 (_CMU_LFEPRESC0_RTCC_DIV2 << 0)
1840 #define CMU_LFEPRESC0_RTCC_DIV4 (_CMU_LFEPRESC0_RTCC_DIV4 << 0)
1842 /* Bit fields for CMU SYNCBUSY */
1843 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
1844 #define _CMU_SYNCBUSY_MASK 0x3F050055UL
1845 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
1846 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
1847 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
1848 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
1849 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
1850 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
1851 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
1852 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
1853 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
1854 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
1855 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
1856 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
1857 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
1858 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
1859 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
1860 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
1861 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
1862 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
1863 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
1864 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
1865 #define CMU_SYNCBUSY_LFECLKEN0 (0x1UL << 16)
1866 #define _CMU_SYNCBUSY_LFECLKEN0_SHIFT 16
1867 #define _CMU_SYNCBUSY_LFECLKEN0_MASK 0x10000UL
1868 #define _CMU_SYNCBUSY_LFECLKEN0_DEFAULT 0x00000000UL
1869 #define CMU_SYNCBUSY_LFECLKEN0_DEFAULT (_CMU_SYNCBUSY_LFECLKEN0_DEFAULT << 16)
1870 #define CMU_SYNCBUSY_LFEPRESC0 (0x1UL << 18)
1871 #define _CMU_SYNCBUSY_LFEPRESC0_SHIFT 18
1872 #define _CMU_SYNCBUSY_LFEPRESC0_MASK 0x40000UL
1873 #define _CMU_SYNCBUSY_LFEPRESC0_DEFAULT 0x00000000UL
1874 #define CMU_SYNCBUSY_LFEPRESC0_DEFAULT (_CMU_SYNCBUSY_LFEPRESC0_DEFAULT << 18)
1875 #define CMU_SYNCBUSY_HFRCOBSY (0x1UL << 24)
1876 #define _CMU_SYNCBUSY_HFRCOBSY_SHIFT 24
1877 #define _CMU_SYNCBUSY_HFRCOBSY_MASK 0x1000000UL
1878 #define _CMU_SYNCBUSY_HFRCOBSY_DEFAULT 0x00000000UL
1879 #define CMU_SYNCBUSY_HFRCOBSY_DEFAULT (_CMU_SYNCBUSY_HFRCOBSY_DEFAULT << 24)
1880 #define CMU_SYNCBUSY_AUXHFRCOBSY (0x1UL << 25)
1881 #define _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT 25
1882 #define _CMU_SYNCBUSY_AUXHFRCOBSY_MASK 0x2000000UL
1883 #define _CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT 0x00000000UL
1884 #define CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT (_CMU_SYNCBUSY_AUXHFRCOBSY_DEFAULT << 25)
1885 #define CMU_SYNCBUSY_LFRCOBSY (0x1UL << 26)
1886 #define _CMU_SYNCBUSY_LFRCOBSY_SHIFT 26
1887 #define _CMU_SYNCBUSY_LFRCOBSY_MASK 0x4000000UL
1888 #define _CMU_SYNCBUSY_LFRCOBSY_DEFAULT 0x00000000UL
1889 #define CMU_SYNCBUSY_LFRCOBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOBSY_DEFAULT << 26)
1890 #define CMU_SYNCBUSY_LFRCOVREFBSY (0x1UL << 27)
1891 #define _CMU_SYNCBUSY_LFRCOVREFBSY_SHIFT 27
1892 #define _CMU_SYNCBUSY_LFRCOVREFBSY_MASK 0x8000000UL
1893 #define _CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT 0x00000000UL
1894 #define CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT (_CMU_SYNCBUSY_LFRCOVREFBSY_DEFAULT << 27)
1895 #define CMU_SYNCBUSY_HFXOBSY (0x1UL << 28)
1896 #define _CMU_SYNCBUSY_HFXOBSY_SHIFT 28
1897 #define _CMU_SYNCBUSY_HFXOBSY_MASK 0x10000000UL
1898 #define _CMU_SYNCBUSY_HFXOBSY_DEFAULT 0x00000000UL
1899 #define CMU_SYNCBUSY_HFXOBSY_DEFAULT (_CMU_SYNCBUSY_HFXOBSY_DEFAULT << 28)
1900 #define CMU_SYNCBUSY_LFXOBSY (0x1UL << 29)
1901 #define _CMU_SYNCBUSY_LFXOBSY_SHIFT 29
1902 #define _CMU_SYNCBUSY_LFXOBSY_MASK 0x20000000UL
1903 #define _CMU_SYNCBUSY_LFXOBSY_DEFAULT 0x00000000UL
1904 #define CMU_SYNCBUSY_LFXOBSY_DEFAULT (_CMU_SYNCBUSY_LFXOBSY_DEFAULT << 29)
1906 /* Bit fields for CMU FREEZE */
1907 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
1908 #define _CMU_FREEZE_MASK 0x00000001UL
1909 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
1910 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
1911 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
1912 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
1913 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
1914 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
1915 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
1916 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
1917 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
1919 /* Bit fields for CMU PCNTCTRL */
1920 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
1921 #define _CMU_PCNTCTRL_MASK 0x00000003UL
1922 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
1923 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
1924 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
1925 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
1926 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
1927 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
1928 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
1929 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
1930 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
1931 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
1932 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
1933 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
1934 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
1935 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
1937 /* Bit fields for CMU ADCCTRL */
1938 #define _CMU_ADCCTRL_RESETVALUE 0x00000000UL
1939 #define _CMU_ADCCTRL_MASK 0x00000130UL
1940 #define _CMU_ADCCTRL_ADC0CLKSEL_SHIFT 4
1941 #define _CMU_ADCCTRL_ADC0CLKSEL_MASK 0x30UL
1942 #define _CMU_ADCCTRL_ADC0CLKSEL_DEFAULT 0x00000000UL
1943 #define _CMU_ADCCTRL_ADC0CLKSEL_DISABLED 0x00000000UL
1944 #define _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO 0x00000001UL
1945 #define _CMU_ADCCTRL_ADC0CLKSEL_HFXO 0x00000002UL
1946 #define _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK 0x00000003UL
1947 #define CMU_ADCCTRL_ADC0CLKSEL_DEFAULT (_CMU_ADCCTRL_ADC0CLKSEL_DEFAULT << 4)
1948 #define CMU_ADCCTRL_ADC0CLKSEL_DISABLED (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << 4)
1949 #define CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << 4)
1950 #define CMU_ADCCTRL_ADC0CLKSEL_HFXO (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << 4)
1951 #define CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << 4)
1952 #define CMU_ADCCTRL_ADC0CLKINV (0x1UL << 8)
1953 #define _CMU_ADCCTRL_ADC0CLKINV_SHIFT 8
1954 #define _CMU_ADCCTRL_ADC0CLKINV_MASK 0x100UL
1955 #define _CMU_ADCCTRL_ADC0CLKINV_DEFAULT 0x00000000UL
1956 #define CMU_ADCCTRL_ADC0CLKINV_DEFAULT (_CMU_ADCCTRL_ADC0CLKINV_DEFAULT << 8)
1958 /* Bit fields for CMU ROUTEPEN */
1959 #define _CMU_ROUTEPEN_RESETVALUE 0x00000000UL
1960 #define _CMU_ROUTEPEN_MASK 0x10000003UL
1961 #define CMU_ROUTEPEN_CLKOUT0PEN (0x1UL << 0)
1962 #define _CMU_ROUTEPEN_CLKOUT0PEN_SHIFT 0
1963 #define _CMU_ROUTEPEN_CLKOUT0PEN_MASK 0x1UL
1964 #define _CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT 0x00000000UL
1965 #define CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT0PEN_DEFAULT << 0)
1966 #define CMU_ROUTEPEN_CLKOUT1PEN (0x1UL << 1)
1967 #define _CMU_ROUTEPEN_CLKOUT1PEN_SHIFT 1
1968 #define _CMU_ROUTEPEN_CLKOUT1PEN_MASK 0x2UL
1969 #define _CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT 0x00000000UL
1970 #define CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT (_CMU_ROUTEPEN_CLKOUT1PEN_DEFAULT << 1)
1971 #define CMU_ROUTEPEN_CLKIN0PEN (0x1UL << 28)
1972 #define _CMU_ROUTEPEN_CLKIN0PEN_SHIFT 28
1973 #define _CMU_ROUTEPEN_CLKIN0PEN_MASK 0x10000000UL
1974 #define _CMU_ROUTEPEN_CLKIN0PEN_DEFAULT 0x00000000UL
1975 #define CMU_ROUTEPEN_CLKIN0PEN_DEFAULT (_CMU_ROUTEPEN_CLKIN0PEN_DEFAULT << 28)
1977 /* Bit fields for CMU ROUTELOC0 */
1978 #define _CMU_ROUTELOC0_RESETVALUE 0x00000000UL
1979 #define _CMU_ROUTELOC0_MASK 0x00000707UL
1980 #define _CMU_ROUTELOC0_CLKOUT0LOC_SHIFT 0
1981 #define _CMU_ROUTELOC0_CLKOUT0LOC_MASK 0x7UL
1982 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC0 0x00000000UL
1983 #define _CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT 0x00000000UL
1984 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC1 0x00000001UL
1985 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC2 0x00000002UL
1986 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC3 0x00000003UL
1987 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC4 0x00000004UL
1988 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC5 0x00000005UL
1989 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC6 0x00000006UL
1990 #define _CMU_ROUTELOC0_CLKOUT0LOC_LOC7 0x00000007UL
1991 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC0 << 0)
1992 #define CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT0LOC_DEFAULT << 0)
1993 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC1 << 0)
1994 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC2 << 0)
1995 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC3 << 0)
1996 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC4 << 0)
1997 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC5 << 0)
1998 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC6 << 0)
1999 #define CMU_ROUTELOC0_CLKOUT0LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT0LOC_LOC7 << 0)
2000 #define _CMU_ROUTELOC0_CLKOUT1LOC_SHIFT 8
2001 #define _CMU_ROUTELOC0_CLKOUT1LOC_MASK 0x700UL
2002 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC0 0x00000000UL
2003 #define _CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT 0x00000000UL
2004 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC1 0x00000001UL
2005 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC2 0x00000002UL
2006 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC3 0x00000003UL
2007 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC4 0x00000004UL
2008 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC5 0x00000005UL
2009 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC6 0x00000006UL
2010 #define _CMU_ROUTELOC0_CLKOUT1LOC_LOC7 0x00000007UL
2011 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC0 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC0 << 8)
2012 #define CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT (_CMU_ROUTELOC0_CLKOUT1LOC_DEFAULT << 8)
2013 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC1 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC1 << 8)
2014 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC2 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC2 << 8)
2015 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC3 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC3 << 8)
2016 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC4 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC4 << 8)
2017 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC5 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC5 << 8)
2018 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC6 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC6 << 8)
2019 #define CMU_ROUTELOC0_CLKOUT1LOC_LOC7 (_CMU_ROUTELOC0_CLKOUT1LOC_LOC7 << 8)
2021 /* Bit fields for CMU ROUTELOC1 */
2022 #define _CMU_ROUTELOC1_RESETVALUE 0x00000000UL
2023 #define _CMU_ROUTELOC1_MASK 0x00000007UL
2024 #define _CMU_ROUTELOC1_CLKIN0LOC_SHIFT 0
2025 #define _CMU_ROUTELOC1_CLKIN0LOC_MASK 0x7UL
2026 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC0 0x00000000UL
2027 #define _CMU_ROUTELOC1_CLKIN0LOC_DEFAULT 0x00000000UL
2028 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC1 0x00000001UL
2029 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC2 0x00000002UL
2030 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC3 0x00000003UL
2031 #define _CMU_ROUTELOC1_CLKIN0LOC_LOC4 0x00000004UL
2032 #define CMU_ROUTELOC1_CLKIN0LOC_LOC0 (_CMU_ROUTELOC1_CLKIN0LOC_LOC0 << 0)
2033 #define CMU_ROUTELOC1_CLKIN0LOC_DEFAULT (_CMU_ROUTELOC1_CLKIN0LOC_DEFAULT << 0)
2034 #define CMU_ROUTELOC1_CLKIN0LOC_LOC1 (_CMU_ROUTELOC1_CLKIN0LOC_LOC1 << 0)
2035 #define CMU_ROUTELOC1_CLKIN0LOC_LOC2 (_CMU_ROUTELOC1_CLKIN0LOC_LOC2 << 0)
2036 #define CMU_ROUTELOC1_CLKIN0LOC_LOC3 (_CMU_ROUTELOC1_CLKIN0LOC_LOC3 << 0)
2037 #define CMU_ROUTELOC1_CLKIN0LOC_LOC4 (_CMU_ROUTELOC1_CLKIN0LOC_LOC4 << 0)
2039 /* Bit fields for CMU LOCK */
2040 #define _CMU_LOCK_RESETVALUE 0x00000000UL
2041 #define _CMU_LOCK_MASK 0x0000FFFFUL
2042 #define _CMU_LOCK_LOCKKEY_SHIFT 0
2043 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
2044 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
2045 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
2046 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
2047 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
2048 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
2049 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
2050 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
2051 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
2052 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
2053 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
2055 /* Bit fields for CMU HFRCOSS */
2056 #define _CMU_HFRCOSS_RESETVALUE 0x00000000UL
2057 #define _CMU_HFRCOSS_MASK 0x00001F07UL
2058 #define _CMU_HFRCOSS_SSAMP_SHIFT 0
2059 #define _CMU_HFRCOSS_SSAMP_MASK 0x7UL
2060 #define _CMU_HFRCOSS_SSAMP_DEFAULT 0x00000000UL
2061 #define CMU_HFRCOSS_SSAMP_DEFAULT (_CMU_HFRCOSS_SSAMP_DEFAULT << 0)
2062 #define _CMU_HFRCOSS_SSINV_SHIFT 8
2063 #define _CMU_HFRCOSS_SSINV_MASK 0x1F00UL
2064 #define _CMU_HFRCOSS_SSINV_DEFAULT 0x00000000UL
2065 #define CMU_HFRCOSS_SSINV_DEFAULT (_CMU_HFRCOSS_SSINV_DEFAULT << 8)
__IOM uint32_t LFECLKEN0
__IOM uint32_t DBGCLKSEL
__IOM uint32_t LFACLKSEL
__IOM uint32_t CALCTRL
__IOM uint32_t HFCOREPRESC
__IOM uint32_t HFRCOSS
__IOM uint32_t ROUTELOC1
__IOM uint32_t HFEXPPRESC
__IOM uint32_t HFXOCTRL
__IM uint32_t IF
__IOM uint32_t IEN
__IOM uint32_t LFACLKEN0
__IOM uint32_t HFXOSTEADYSTATECTRL
__IOM uint32_t DPLLCTRL1
__IOM uint32_t PCNTCTRL
__IOM uint32_t LFAPRESC0
__IOM uint32_t IFC
__IOM uint32_t ROUTELOC0
__IOM uint32_t HFBUSCLKEN0
__IOM uint32_t CTRL
__IOM uint32_t LFBPRESC0
__IOM uint32_t HFCLKSEL
__IOM uint32_t DPLLCTRL
__IOM uint32_t AUXHFRCOCTRL
__IOM uint32_t OSCENCMD
__IOM uint32_t FREEZE
__IM uint32_t STATUS
__IOM uint32_t LFBCLKEN0
__IOM uint32_t CALCNT
__IOM uint32_t HFPERCLKEN0
__IOM uint32_t ROUTEPEN
__IOM uint32_t IFS
__IOM uint32_t LFXOCTRL
__IM uint32_t HFXOTRIMSTATUS
__IOM uint32_t HFRCOCTRL
__IOM uint32_t LFEPRESC0
__IM uint32_t HFCLKSTATUS
__IOM uint32_t HFXOTIMEOUTCTRL
__IOM uint32_t CMD
__IOM uint32_t HFPRESC
__IOM uint32_t HFPERPRESC
__IM uint32_t SYNCBUSY
__IOM uint32_t HFXOSTARTUPCTRL
__IOM uint32_t ADCCTRL
__IOM uint32_t LFRCOCTRL
__IOM uint32_t LFBCLKSEL
__IOM uint32_t LOCK
__IOM uint32_t LFECLKSEL