Detailed Description

Macros
#define	_CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL

#define	_CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL

#define	_CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL

#define	_CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL

#define	_CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL

#define	_CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL

#define	_CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL

#define	_CMU_AUXHFRCOCTRL_BAND_SHIFT 8

#define	_CMU_AUXHFRCOCTRL_MASK 0x000007FFUL

#define	_CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL

#define	_CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL

#define	_CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL

#define	_CMU_AUXHFRCOCTRL_TUNING_SHIFT 0

#define	_CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL

#define	_CMU_CALCNT_CALCNT_MASK 0xFFFFFUL

#define	_CMU_CALCNT_CALCNT_SHIFT 0

#define	_CMU_CALCNT_MASK 0x000FFFFFUL

#define	_CMU_CALCNT_RESETVALUE 0x00000000UL

#define	_CMU_CALCTRL_CONT_DEFAULT 0x00000000UL

#define	_CMU_CALCTRL_CONT_MASK 0x40UL

#define	_CMU_CALCTRL_CONT_SHIFT 6

#define	_CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL

#define	_CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL

#define	_CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL

#define	_CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL

#define	_CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL

#define	_CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL

#define	_CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL

#define	_CMU_CALCTRL_DOWNSEL_MASK 0x38UL

#define	_CMU_CALCTRL_DOWNSEL_SHIFT 3

#define	_CMU_CALCTRL_MASK 0x0000007FUL

#define	_CMU_CALCTRL_RESETVALUE 0x00000000UL

#define	_CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL

#define	_CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL

#define	_CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL

#define	_CMU_CALCTRL_UPSEL_HFXO 0x00000000UL

#define	_CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL

#define	_CMU_CALCTRL_UPSEL_LFXO 0x00000001UL

#define	_CMU_CALCTRL_UPSEL_MASK 0x7UL

#define	_CMU_CALCTRL_UPSEL_SHIFT 0

#define	_CMU_CMD_CALSTART_DEFAULT 0x00000000UL

#define	_CMU_CMD_CALSTART_MASK 0x8UL

#define	_CMU_CMD_CALSTART_SHIFT 3

#define	_CMU_CMD_CALSTOP_DEFAULT 0x00000000UL

#define	_CMU_CMD_CALSTOP_MASK 0x10UL

#define	_CMU_CMD_CALSTOP_SHIFT 4

#define	_CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL

#define	_CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL

#define	_CMU_CMD_HFCLKSEL_HFXO 0x00000002UL

#define	_CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL

#define	_CMU_CMD_HFCLKSEL_LFXO 0x00000004UL

#define	_CMU_CMD_HFCLKSEL_MASK 0x7UL

#define	_CMU_CMD_HFCLKSEL_SHIFT 0

#define	_CMU_CMD_MASK 0x0000001FUL

#define	_CMU_CMD_RESETVALUE 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL

#define	_CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL

#define	_CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL

#define	_CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL

#define	_CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL

#define	_CMU_CTRL_CLKOUTSEL0_SHIFT 20

#define	_CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL

#define	_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL

#define	_CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL

#define	_CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL

#define	_CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL

#define	_CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL

#define	_CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL

#define	_CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL

#define	_CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL

#define	_CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL

#define	_CMU_CTRL_CLKOUTSEL1_SHIFT 23

#define	_CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL

#define	_CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL

#define	_CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL

#define	_CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL

#define	_CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL

#define	_CMU_CTRL_HFXOBOOST_MASK 0xCUL

#define	_CMU_CTRL_HFXOBOOST_SHIFT 2

#define	_CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL

#define	_CMU_CTRL_HFXOBUFCUR_MASK 0x60UL

#define	_CMU_CTRL_HFXOBUFCUR_SHIFT 5

#define	_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL

#define	_CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7

#define	_CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL

#define	_CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL

#define	_CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL

#define	_CMU_CTRL_HFXOMODE_MASK 0x3UL

#define	_CMU_CTRL_HFXOMODE_SHIFT 0

#define	_CMU_CTRL_HFXOMODE_XTAL 0x00000000UL

#define	_CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL

#define	_CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL

#define	_CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL

#define	_CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL

#define	_CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL

#define	_CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL

#define	_CMU_CTRL_HFXOTIMEOUT_SHIFT 9

#define	_CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL

#define	_CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL

#define	_CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL

#define	_CMU_CTRL_LFXOBOOST_MASK 0x2000UL

#define	_CMU_CTRL_LFXOBOOST_SHIFT 13

#define	_CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL

#define	_CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL

#define	_CMU_CTRL_LFXOBUFCUR_SHIFT 17

#define	_CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL

#define	_CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL

#define	_CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL

#define	_CMU_CTRL_LFXOMODE_MASK 0x1800UL

#define	_CMU_CTRL_LFXOMODE_SHIFT 11

#define	_CMU_CTRL_LFXOMODE_XTAL 0x00000000UL

#define	_CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL

#define	_CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL

#define	_CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL

#define	_CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL

#define	_CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL

#define	_CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL

#define	_CMU_CTRL_LFXOTIMEOUT_SHIFT 18

#define	_CMU_CTRL_MASK 0x07FE3EEFUL

#define	_CMU_CTRL_RESETVALUE 0x000C262CUL

#define	_CMU_FREEZE_MASK 0x00000001UL

#define	_CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL

#define	_CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL

#define	_CMU_FREEZE_REGFREEZE_MASK 0x1UL

#define	_CMU_FREEZE_REGFREEZE_SHIFT 0

#define	_CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL

#define	_CMU_FREEZE_RESETVALUE 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL

#define	_CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL

#define	_CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8

#define	_CMU_HFCORECLKDIV_MASK 0x0000010FUL

#define	_CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL

#define	_CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_AES_MASK 0x1UL

#define	_CMU_HFCORECLKEN0_AES_SHIFT 0

#define	_CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_DMA_MASK 0x2UL

#define	_CMU_HFCORECLKEN0_DMA_SHIFT 1

#define	_CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL

#define	_CMU_HFCORECLKEN0_LE_MASK 0x4UL

#define	_CMU_HFCORECLKEN0_LE_SHIFT 2

#define	_CMU_HFCORECLKEN0_MASK 0x00000007UL

#define	_CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL

#define	_CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0

#define	_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL

#define	_CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL

#define	_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8

#define	_CMU_HFPERCLKDIV_MASK 0x0000010FUL

#define	_CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL

#define	_CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_ACMP0_MASK 0x4UL

#define	_CMU_HFPERCLKEN0_ACMP0_SHIFT 2

#define	_CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_ADC0_MASK 0x400UL

#define	_CMU_HFPERCLKEN0_ADC0_SHIFT 10

#define	_CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_GPIO_MASK 0x80UL

#define	_CMU_HFPERCLKEN0_GPIO_SHIFT 7

#define	_CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_I2C0_MASK 0x800UL

#define	_CMU_HFPERCLKEN0_I2C0_SHIFT 11

#define	_CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_IDAC0_MASK 0x40UL

#define	_CMU_HFPERCLKEN0_IDAC0_SHIFT 6

#define	_CMU_HFPERCLKEN0_MASK 0x00000DDFUL

#define	_CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_PRS_MASK 0x10UL

#define	_CMU_HFPERCLKEN0_PRS_SHIFT 4

#define	_CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL

#define	_CMU_HFPERCLKEN0_TIMER0_SHIFT 0

#define	_CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL

#define	_CMU_HFPERCLKEN0_TIMER1_SHIFT 1

#define	_CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_USART1_MASK 0x8UL

#define	_CMU_HFPERCLKEN0_USART1_SHIFT 3

#define	_CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL

#define	_CMU_HFPERCLKEN0_VCMP_MASK 0x100UL

#define	_CMU_HFPERCLKEN0_VCMP_SHIFT 8

#define	_CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL

#define	_CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL

#define	_CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL

#define	_CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL

#define	_CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL

#define	_CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL

#define	_CMU_HFRCOCTRL_BAND_MASK 0x700UL

#define	_CMU_HFRCOCTRL_BAND_SHIFT 8

#define	_CMU_HFRCOCTRL_MASK 0x0001F7FFUL

#define	_CMU_HFRCOCTRL_RESETVALUE 0x00000380UL

#define	_CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL

#define	_CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL

#define	_CMU_HFRCOCTRL_SUDELAY_SHIFT 12

#define	_CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL

#define	_CMU_HFRCOCTRL_TUNING_MASK 0xFFUL

#define	_CMU_HFRCOCTRL_TUNING_SHIFT 0

#define	_CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IEN_AUXHFRCORDY_SHIFT 4

#define	_CMU_IEN_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IEN_CALOF_MASK 0x40UL

#define	_CMU_IEN_CALOF_SHIFT 6

#define	_CMU_IEN_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_CALRDY_MASK 0x20UL

#define	_CMU_IEN_CALRDY_SHIFT 5

#define	_CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_HFRCORDY_MASK 0x1UL

#define	_CMU_IEN_HFRCORDY_SHIFT 0

#define	_CMU_IEN_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_HFXORDY_MASK 0x2UL

#define	_CMU_IEN_HFXORDY_SHIFT 1

#define	_CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_LFRCORDY_MASK 0x4UL

#define	_CMU_IEN_LFRCORDY_SHIFT 2

#define	_CMU_IEN_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IEN_LFXORDY_MASK 0x8UL

#define	_CMU_IEN_LFXORDY_SHIFT 3

#define	_CMU_IEN_MASK 0x0000007FUL

#define	_CMU_IEN_RESETVALUE 0x00000000UL

#define	_CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IF_AUXHFRCORDY_SHIFT 4

#define	_CMU_IF_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IF_CALOF_MASK 0x40UL

#define	_CMU_IF_CALOF_SHIFT 6

#define	_CMU_IF_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IF_CALRDY_MASK 0x20UL

#define	_CMU_IF_CALRDY_SHIFT 5

#define	_CMU_IF_HFRCORDY_DEFAULT 0x00000001UL

#define	_CMU_IF_HFRCORDY_MASK 0x1UL

#define	_CMU_IF_HFRCORDY_SHIFT 0

#define	_CMU_IF_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_HFXORDY_MASK 0x2UL

#define	_CMU_IF_HFXORDY_SHIFT 1

#define	_CMU_IF_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_LFRCORDY_MASK 0x4UL

#define	_CMU_IF_LFRCORDY_SHIFT 2

#define	_CMU_IF_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IF_LFXORDY_MASK 0x8UL

#define	_CMU_IF_LFXORDY_SHIFT 3

#define	_CMU_IF_MASK 0x0000007FUL

#define	_CMU_IF_RESETVALUE 0x00000001UL

#define	_CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IFC_AUXHFRCORDY_SHIFT 4

#define	_CMU_IFC_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IFC_CALOF_MASK 0x40UL

#define	_CMU_IFC_CALOF_SHIFT 6

#define	_CMU_IFC_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_CALRDY_MASK 0x20UL

#define	_CMU_IFC_CALRDY_SHIFT 5

#define	_CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_HFRCORDY_MASK 0x1UL

#define	_CMU_IFC_HFRCORDY_SHIFT 0

#define	_CMU_IFC_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_HFXORDY_MASK 0x2UL

#define	_CMU_IFC_HFXORDY_SHIFT 1

#define	_CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_LFRCORDY_MASK 0x4UL

#define	_CMU_IFC_LFRCORDY_SHIFT 2

#define	_CMU_IFC_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFC_LFXORDY_MASK 0x8UL

#define	_CMU_IFC_LFXORDY_SHIFT 3

#define	_CMU_IFC_MASK 0x0000007FUL

#define	_CMU_IFC_RESETVALUE 0x00000000UL

#define	_CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_AUXHFRCORDY_MASK 0x10UL

#define	_CMU_IFS_AUXHFRCORDY_SHIFT 4

#define	_CMU_IFS_CALOF_DEFAULT 0x00000000UL

#define	_CMU_IFS_CALOF_MASK 0x40UL

#define	_CMU_IFS_CALOF_SHIFT 6

#define	_CMU_IFS_CALRDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_CALRDY_MASK 0x20UL

#define	_CMU_IFS_CALRDY_SHIFT 5

#define	_CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_HFRCORDY_MASK 0x1UL

#define	_CMU_IFS_HFRCORDY_SHIFT 0

#define	_CMU_IFS_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_HFXORDY_MASK 0x2UL

#define	_CMU_IFS_HFXORDY_SHIFT 1

#define	_CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_LFRCORDY_MASK 0x4UL

#define	_CMU_IFS_LFRCORDY_SHIFT 2

#define	_CMU_IFS_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_IFS_LFXORDY_MASK 0x8UL

#define	_CMU_IFS_LFXORDY_SHIFT 3

#define	_CMU_IFS_MASK 0x0000007FUL

#define	_CMU_IFS_RESETVALUE 0x00000000UL

#define	_CMU_LFACLKEN0_MASK 0x00000001UL

#define	_CMU_LFACLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL

#define	_CMU_LFACLKEN0_RTC_MASK 0x1UL

#define	_CMU_LFACLKEN0_RTC_SHIFT 0

#define	_CMU_LFAPRESC0_MASK 0x0000000FUL

#define	_CMU_LFAPRESC0_RESETVALUE 0x00000000UL

#define	_CMU_LFAPRESC0_RTC_DIV1 0x00000000UL

#define	_CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL

#define	_CMU_LFAPRESC0_RTC_DIV128 0x00000007UL

#define	_CMU_LFAPRESC0_RTC_DIV16 0x00000004UL

#define	_CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL

#define	_CMU_LFAPRESC0_RTC_DIV2 0x00000001UL

#define	_CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL

#define	_CMU_LFAPRESC0_RTC_DIV256 0x00000008UL

#define	_CMU_LFAPRESC0_RTC_DIV32 0x00000005UL

#define	_CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL

#define	_CMU_LFAPRESC0_RTC_DIV4 0x00000002UL

#define	_CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL

#define	_CMU_LFAPRESC0_RTC_DIV512 0x00000009UL

#define	_CMU_LFAPRESC0_RTC_DIV64 0x00000006UL

#define	_CMU_LFAPRESC0_RTC_DIV8 0x00000003UL

#define	_CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL

#define	_CMU_LFAPRESC0_RTC_MASK 0xFUL

#define	_CMU_LFAPRESC0_RTC_SHIFT 0

#define	_CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL

#define	_CMU_LFBCLKEN0_LEUART0_MASK 0x1UL

#define	_CMU_LFBCLKEN0_LEUART0_SHIFT 0

#define	_CMU_LFBCLKEN0_MASK 0x00000001UL

#define	_CMU_LFBCLKEN0_RESETVALUE 0x00000000UL

#define	_CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL

#define	_CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL

#define	_CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL

#define	_CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL

#define	_CMU_LFBPRESC0_LEUART0_MASK 0x3UL

#define	_CMU_LFBPRESC0_LEUART0_SHIFT 0

#define	_CMU_LFBPRESC0_MASK 0x00000003UL

#define	_CMU_LFBPRESC0_RESETVALUE 0x00000000UL

#define	_CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL

#define	_CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL

#define	_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL

#define	_CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL

#define	_CMU_LFCLKSEL_LFA_LFXO 0x00000002UL

#define	_CMU_LFCLKSEL_LFA_MASK 0x3UL

#define	_CMU_LFCLKSEL_LFA_SHIFT 0

#define	_CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL

#define	_CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL

#define	_CMU_LFCLKSEL_LFAE_MASK 0x10000UL

#define	_CMU_LFCLKSEL_LFAE_SHIFT 16

#define	_CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL

#define	_CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL

#define	_CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL

#define	_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL

#define	_CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL

#define	_CMU_LFCLKSEL_LFB_LFXO 0x00000002UL

#define	_CMU_LFCLKSEL_LFB_MASK 0xCUL

#define	_CMU_LFCLKSEL_LFB_SHIFT 2

#define	_CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL

#define	_CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL

#define	_CMU_LFCLKSEL_LFBE_MASK 0x100000UL

#define	_CMU_LFCLKSEL_LFBE_SHIFT 20

#define	_CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL

#define	_CMU_LFCLKSEL_MASK 0x0011000FUL

#define	_CMU_LFCLKSEL_RESETVALUE 0x00000005UL

#define	_CMU_LFRCOCTRL_MASK 0x0000007FUL

#define	_CMU_LFRCOCTRL_RESETVALUE 0x00000040UL

#define	_CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL

#define	_CMU_LFRCOCTRL_TUNING_MASK 0x7FUL

#define	_CMU_LFRCOCTRL_TUNING_SHIFT 0

#define	_CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL

#define	_CMU_LOCK_LOCKKEY_LOCK 0x00000000UL

#define	_CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL

#define	_CMU_LOCK_LOCKKEY_MASK 0xFFFFUL

#define	_CMU_LOCK_LOCKKEY_SHIFT 0

#define	_CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL

#define	_CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL

#define	_CMU_LOCK_MASK 0x0000FFFFUL

#define	_CMU_LOCK_RESETVALUE 0x00000000UL

#define	_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL

#define	_CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5

#define	_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL

#define	_CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4

#define	_CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_HFRCODIS_MASK 0x2UL

#define	_CMU_OSCENCMD_HFRCODIS_SHIFT 1

#define	_CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_HFRCOEN_MASK 0x1UL

#define	_CMU_OSCENCMD_HFRCOEN_SHIFT 0

#define	_CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_HFXODIS_MASK 0x8UL

#define	_CMU_OSCENCMD_HFXODIS_SHIFT 3

#define	_CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_HFXOEN_MASK 0x4UL

#define	_CMU_OSCENCMD_HFXOEN_SHIFT 2

#define	_CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_LFRCODIS_MASK 0x80UL

#define	_CMU_OSCENCMD_LFRCODIS_SHIFT 7

#define	_CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_LFRCOEN_MASK 0x40UL

#define	_CMU_OSCENCMD_LFRCOEN_SHIFT 6

#define	_CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_LFXODIS_MASK 0x200UL

#define	_CMU_OSCENCMD_LFXODIS_SHIFT 9

#define	_CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL

#define	_CMU_OSCENCMD_LFXOEN_MASK 0x100UL

#define	_CMU_OSCENCMD_LFXOEN_SHIFT 8

#define	_CMU_OSCENCMD_MASK 0x000003FFUL

#define	_CMU_OSCENCMD_RESETVALUE 0x00000000UL

#define	_CMU_PCNTCTRL_MASK 0x00000003UL

#define	_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL

#define	_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL

#define	_CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1

#define	_CMU_PCNTCTRL_RESETVALUE 0x00000000UL

#define	_CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL

#define	_CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL

#define	_CMU_ROUTE_CLKOUT0PEN_SHIFT 0

#define	_CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL

#define	_CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL

#define	_CMU_ROUTE_CLKOUT1PEN_SHIFT 1

#define	_CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL

#define	_CMU_ROUTE_LOCATION_LOC0 0x00000000UL

#define	_CMU_ROUTE_LOCATION_LOC1 0x00000001UL

#define	_CMU_ROUTE_LOCATION_LOC2 0x00000002UL

#define	_CMU_ROUTE_LOCATION_MASK 0x1CUL

#define	_CMU_ROUTE_LOCATION_SHIFT 2

#define	_CMU_ROUTE_MASK 0x0000001FUL

#define	_CMU_ROUTE_RESETVALUE 0x00000000UL

#define	_CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL

#define	_CMU_STATUS_AUXHFRCOENS_MASK 0x10UL

#define	_CMU_STATUS_AUXHFRCOENS_SHIFT 4

#define	_CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_AUXHFRCORDY_MASK 0x20UL

#define	_CMU_STATUS_AUXHFRCORDY_SHIFT 5

#define	_CMU_STATUS_CALBSY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_CALBSY_MASK 0x4000UL

#define	_CMU_STATUS_CALBSY_SHIFT 14

#define	_CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL

#define	_CMU_STATUS_HFRCOENS_MASK 0x1UL

#define	_CMU_STATUS_HFRCOENS_SHIFT 0

#define	_CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL

#define	_CMU_STATUS_HFRCORDY_MASK 0x2UL

#define	_CMU_STATUS_HFRCORDY_SHIFT 1

#define	_CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL

#define	_CMU_STATUS_HFRCOSEL_MASK 0x400UL

#define	_CMU_STATUS_HFRCOSEL_SHIFT 10

#define	_CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL

#define	_CMU_STATUS_HFXOENS_MASK 0x4UL

#define	_CMU_STATUS_HFXOENS_SHIFT 2

#define	_CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_HFXORDY_MASK 0x8UL

#define	_CMU_STATUS_HFXORDY_SHIFT 3

#define	_CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL

#define	_CMU_STATUS_HFXOSEL_MASK 0x800UL

#define	_CMU_STATUS_HFXOSEL_SHIFT 11

#define	_CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFRCOENS_MASK 0x40UL

#define	_CMU_STATUS_LFRCOENS_SHIFT 6

#define	_CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFRCORDY_MASK 0x80UL

#define	_CMU_STATUS_LFRCORDY_SHIFT 7

#define	_CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFRCOSEL_MASK 0x1000UL

#define	_CMU_STATUS_LFRCOSEL_SHIFT 12

#define	_CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFXOENS_MASK 0x100UL

#define	_CMU_STATUS_LFXOENS_SHIFT 8

#define	_CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFXORDY_MASK 0x200UL

#define	_CMU_STATUS_LFXORDY_SHIFT 9

#define	_CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL

#define	_CMU_STATUS_LFXOSEL_MASK 0x2000UL

#define	_CMU_STATUS_LFXOSEL_SHIFT 13

#define	_CMU_STATUS_MASK 0x00007FFFUL

#define	_CMU_STATUS_RESETVALUE 0x00000403UL

#define	_CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL

#define	_CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL

#define	_CMU_SYNCBUSY_LFACLKEN0_SHIFT 0

#define	_CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL

#define	_CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL

#define	_CMU_SYNCBUSY_LFAPRESC0_SHIFT 2

#define	_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL

#define	_CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL

#define	_CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4

#define	_CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL

#define	_CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL

#define	_CMU_SYNCBUSY_LFBPRESC0_SHIFT 6

#define	_CMU_SYNCBUSY_MASK 0x00000055UL

#define	_CMU_SYNCBUSY_RESETVALUE 0x00000000UL

#define	CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)

#define	CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)

#define	CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)

#define	CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)

#define	CMU_CALCTRL_CONT (0x1UL << 6)

#define	CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6)

#define	CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)

#define	CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)

#define	CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)

#define	CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)

#define	CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3)

#define	CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)

#define	CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3)

#define	CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)

#define	CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)

#define	CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)

#define	CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)

#define	CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)

#define	CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)

#define	CMU_CMD_CALSTART (0x1UL << 3)

#define	CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)

#define	CMU_CMD_CALSTOP (0x1UL << 4)

#define	CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4)

#define	CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)

#define	CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)

#define	CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)

#define	CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)

#define	CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)

#define	CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)

#define	CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)

#define	CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)

#define	CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)

#define	CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)

#define	CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)

#define	CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)

#define	CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)

#define	CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)

#define	CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)

#define	CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)

#define	CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)

#define	CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)

#define	CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)

#define	CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)

#define	CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)

#define	CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)

#define	CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)

#define	CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)

#define	CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)

#define	CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)

#define	CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)

#define	CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)

#define	CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)

#define	CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)

#define	CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)

#define	CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)

#define	CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)

#define	CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)

#define	CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)

#define	CMU_CTRL_LFXOBOOST (0x1UL << 13)

#define	CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)

#define	CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)

#define	CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)

#define	CMU_CTRL_LFXOBUFCUR (0x1UL << 17)

#define	CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)

#define	CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)

#define	CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)

#define	CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)

#define	CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)

#define	CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)

#define	CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)

#define	CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)

#define	CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)

#define	CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)

#define	CMU_FREEZE_REGFREEZE (0x1UL << 0)

#define	CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)

#define	CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)

#define	CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)

#define	CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8)

#define	CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8)

#define	CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)

#define	CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)

#define	CMU_HFCORECLKEN0_AES (0x1UL << 0)

#define	CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)

#define	CMU_HFCORECLKEN0_DMA (0x1UL << 1)

#define	CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)

#define	CMU_HFCORECLKEN0_LE (0x1UL << 2)

#define	CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)

#define	CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)

#define	CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)

#define	CMU_HFPERCLKEN0_ACMP0 (0x1UL << 2)

#define	CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 2)

#define	CMU_HFPERCLKEN0_ADC0 (0x1UL << 10)

#define	CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10)

#define	CMU_HFPERCLKEN0_GPIO (0x1UL << 7)

#define	CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 7)

#define	CMU_HFPERCLKEN0_I2C0 (0x1UL << 11)

#define	CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)

#define	CMU_HFPERCLKEN0_IDAC0 (0x1UL << 6)

#define	CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 6)

#define	CMU_HFPERCLKEN0_PRS (0x1UL << 4)

#define	CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 4)

#define	CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0)

#define	CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0)

#define	CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1)

#define	CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1)

#define	CMU_HFPERCLKEN0_USART1 (0x1UL << 3)

#define	CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3)

#define	CMU_HFPERCLKEN0_VCMP (0x1UL << 8)

#define	CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 8)

#define	CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)

#define	CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)

#define	CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)

#define	CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)

#define	CMU_IEN_AUXHFRCORDY (0x1UL << 4)

#define	CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)

#define	CMU_IEN_CALOF (0x1UL << 6)

#define	CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)

#define	CMU_IEN_CALRDY (0x1UL << 5)

#define	CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)

#define	CMU_IEN_HFRCORDY (0x1UL << 0)

#define	CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)

#define	CMU_IEN_HFXORDY (0x1UL << 1)

#define	CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)

#define	CMU_IEN_LFRCORDY (0x1UL << 2)

#define	CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)

#define	CMU_IEN_LFXORDY (0x1UL << 3)

#define	CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)

#define	CMU_IF_AUXHFRCORDY (0x1UL << 4)

#define	CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)

#define	CMU_IF_CALOF (0x1UL << 6)

#define	CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)

#define	CMU_IF_CALRDY (0x1UL << 5)

#define	CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)

#define	CMU_IF_HFRCORDY (0x1UL << 0)

#define	CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)

#define	CMU_IF_HFXORDY (0x1UL << 1)

#define	CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)

#define	CMU_IF_LFRCORDY (0x1UL << 2)

#define	CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)

#define	CMU_IF_LFXORDY (0x1UL << 3)

#define	CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)

#define	CMU_IFC_AUXHFRCORDY (0x1UL << 4)

#define	CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)

#define	CMU_IFC_CALOF (0x1UL << 6)

#define	CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)

#define	CMU_IFC_CALRDY (0x1UL << 5)

#define	CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)

#define	CMU_IFC_HFRCORDY (0x1UL << 0)

#define	CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)

#define	CMU_IFC_HFXORDY (0x1UL << 1)

#define	CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)

#define	CMU_IFC_LFRCORDY (0x1UL << 2)

#define	CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)

#define	CMU_IFC_LFXORDY (0x1UL << 3)

#define	CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)

#define	CMU_IFS_AUXHFRCORDY (0x1UL << 4)

#define	CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)

#define	CMU_IFS_CALOF (0x1UL << 6)

#define	CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)

#define	CMU_IFS_CALRDY (0x1UL << 5)

#define	CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)

#define	CMU_IFS_HFRCORDY (0x1UL << 0)

#define	CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)

#define	CMU_IFS_HFXORDY (0x1UL << 1)

#define	CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)

#define	CMU_IFS_LFRCORDY (0x1UL << 2)

#define	CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)

#define	CMU_IFS_LFXORDY (0x1UL << 3)

#define	CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)

#define	CMU_LFACLKEN0_RTC (0x1UL << 0)

#define	CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0)

#define	CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0)

#define	CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0)

#define	CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0)

#define	CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0)

#define	CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)

#define	CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0)

#define	CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0)

#define	CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0)

#define	CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0)

#define	CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)

#define	CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0)

#define	CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0)

#define	CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0)

#define	CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0)

#define	CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0)

#define	CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0)

#define	CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)

#define	CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)

#define	CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)

#define	CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)

#define	CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)

#define	CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)

#define	CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)

#define	CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)

#define	CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)

#define	CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)

#define	CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)

#define	CMU_LFCLKSEL_LFAE (0x1UL << 16)

#define	CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)

#define	CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16)

#define	CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)

#define	CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)

#define	CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)

#define	CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)

#define	CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)

#define	CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)

#define	CMU_LFCLKSEL_LFBE (0x1UL << 20)

#define	CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)

#define	CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20)

#define	CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)

#define	CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)

#define	CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)

#define	CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)

#define	CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)

#define	CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)

#define	CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)

#define	CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)

#define	CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)

#define	CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)

#define	CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)

#define	CMU_OSCENCMD_HFRCODIS (0x1UL << 1)

#define	CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)

#define	CMU_OSCENCMD_HFRCOEN (0x1UL << 0)

#define	CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)

#define	CMU_OSCENCMD_HFXODIS (0x1UL << 3)

#define	CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)

#define	CMU_OSCENCMD_HFXOEN (0x1UL << 2)

#define	CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)

#define	CMU_OSCENCMD_LFRCODIS (0x1UL << 7)

#define	CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)

#define	CMU_OSCENCMD_LFRCOEN (0x1UL << 6)

#define	CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)

#define	CMU_OSCENCMD_LFXODIS (0x1UL << 9)

#define	CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)

#define	CMU_OSCENCMD_LFXOEN (0x1UL << 8)

#define	CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)

#define	CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)

#define	CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)

#define	CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)

#define	CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)

#define	CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)

#define	CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)

#define	CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)

#define	CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)

#define	CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)

#define	CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)

#define	CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)

#define	CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)

#define	CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)

#define	CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2)

#define	CMU_STATUS_AUXHFRCOENS (0x1UL << 4)

#define	CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)

#define	CMU_STATUS_AUXHFRCORDY (0x1UL << 5)

#define	CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)

#define	CMU_STATUS_CALBSY (0x1UL << 14)

#define	CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)

#define	CMU_STATUS_HFRCOENS (0x1UL << 0)

#define	CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)

#define	CMU_STATUS_HFRCORDY (0x1UL << 1)

#define	CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)

#define	CMU_STATUS_HFRCOSEL (0x1UL << 10)

#define	CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)

#define	CMU_STATUS_HFXOENS (0x1UL << 2)

#define	CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)

#define	CMU_STATUS_HFXORDY (0x1UL << 3)

#define	CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)

#define	CMU_STATUS_HFXOSEL (0x1UL << 11)

#define	CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)

#define	CMU_STATUS_LFRCOENS (0x1UL << 6)

#define	CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)

#define	CMU_STATUS_LFRCORDY (0x1UL << 7)

#define	CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)

#define	CMU_STATUS_LFRCOSEL (0x1UL << 12)

#define	CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)

#define	CMU_STATUS_LFXOENS (0x1UL << 8)

#define	CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)

#define	CMU_STATUS_LFXORDY (0x1UL << 9)

#define	CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)

#define	CMU_STATUS_LFXOSEL (0x1UL << 13)

#define	CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)

#define	CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)

#define	CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)

#define	CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)

#define	CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)

#define	CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)

#define	CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)

#define	CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)

#define	CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)

Macro Definition Documentation

#define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL

Mode 11MHZ for CMU_AUXHFRCOCTRL

Definition at line 323 of file efm32zg_cmu.h.

#define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL

Mode 14MHZ for CMU_AUXHFRCOCTRL

Definition at line 322 of file efm32zg_cmu.h.

#define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL

Mode 1MHZ for CMU_AUXHFRCOCTRL

Definition at line 325 of file efm32zg_cmu.h.

#define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL

Mode 21MHZ for CMU_AUXHFRCOCTRL

Definition at line 326 of file efm32zg_cmu.h.

#define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL

Mode 7MHZ for CMU_AUXHFRCOCTRL

Definition at line 324 of file efm32zg_cmu.h.

#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 321 of file efm32zg_cmu.h.

#define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL

Bit mask for CMU_BAND

Definition at line 320 of file efm32zg_cmu.h.

Referenced by CMU_AUXHFRCOBandGet(), and CMU_AUXHFRCOBandSet().

#define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8

Shift value for CMU_BAND

Definition at line 319 of file efm32zg_cmu.h.

Referenced by CMU_AUXHFRCOBandGet(), and CMU_AUXHFRCOBandSet().

#define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL

Mask for CMU_AUXHFRCOCTRL

Definition at line 314 of file efm32zg_cmu.h.

#define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL

Default value for CMU_AUXHFRCOCTRL

Definition at line 313 of file efm32zg_cmu.h.

#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 317 of file efm32zg_cmu.h.

#define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL

Bit mask for CMU_TUNING

Definition at line 316 of file efm32zg_cmu.h.

Referenced by CMU_AUXHFRCOBandSet(), CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0

Shift value for CMU_TUNING

Definition at line 315 of file efm32zg_cmu.h.

Referenced by CMU_AUXHFRCOBandSet(), CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CALCNT

Definition at line 378 of file efm32zg_cmu.h.

#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL

Bit mask for CMU_CALCNT

Definition at line 377 of file efm32zg_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define _CMU_CALCNT_CALCNT_SHIFT 0

Shift value for CMU_CALCNT

Definition at line 376 of file efm32zg_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define _CMU_CALCNT_MASK 0x000FFFFFUL

Mask for CMU_CALCNT

Definition at line 375 of file efm32zg_cmu.h.

#define _CMU_CALCNT_RESETVALUE 0x00000000UL

Default value for CMU_CALCNT

Definition at line 374 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 370 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_CONT_MASK 0x40UL

Bit mask for CMU_CONT

Definition at line 369 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_CONT_SHIFT 6

Shift value for CMU_CONT

Definition at line 368 of file efm32zg_cmu.h.

Referenced by CMU_CalibrateCont(), and CMU_CalibrateCountGet().

#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL

Mode AUXHFRCO for CMU_CALCTRL

Definition at line 359 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 353 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL

Mode HFCLK for CMU_CALCTRL

Definition at line 354 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL

Mode HFRCO for CMU_CALCTRL

Definition at line 357 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL

Mode HFXO for CMU_CALCTRL

Definition at line 355 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL

Mode LFRCO for CMU_CALCTRL

Definition at line 358 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL

Mode LFXO for CMU_CALCTRL

Definition at line 356 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL

Bit mask for CMU_DOWNSEL

Definition at line 352 of file efm32zg_cmu.h.

Referenced by CMU_CalibrateConfig().

#define _CMU_CALCTRL_DOWNSEL_SHIFT 3

Shift value for CMU_DOWNSEL

Definition at line 351 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_MASK 0x0000007FUL

Mask for CMU_CALCTRL

Definition at line 336 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_RESETVALUE 0x00000000UL

Default value for CMU_CALCTRL

Definition at line 335 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL

Mode AUXHFRCO for CMU_CALCTRL

Definition at line 344 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 339 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL

Mode HFRCO for CMU_CALCTRL

Definition at line 342 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL

Mode HFXO for CMU_CALCTRL

Definition at line 340 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL

Mode LFRCO for CMU_CALCTRL

Definition at line 343 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL

Mode LFXO for CMU_CALCTRL

Definition at line 341 of file efm32zg_cmu.h.

#define _CMU_CALCTRL_UPSEL_MASK 0x7UL

Bit mask for CMU_UPSEL

Definition at line 338 of file efm32zg_cmu.h.

Referenced by CMU_CalibrateConfig().

#define _CMU_CALCTRL_UPSEL_SHIFT 0

Shift value for CMU_UPSEL

Definition at line 337 of file efm32zg_cmu.h.

#define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 453 of file efm32zg_cmu.h.

#define _CMU_CMD_CALSTART_MASK 0x8UL

Bit mask for CMU_CALSTART

Definition at line 452 of file efm32zg_cmu.h.

#define _CMU_CMD_CALSTART_SHIFT 3

Shift value for CMU_CALSTART

Definition at line 451 of file efm32zg_cmu.h.

#define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 458 of file efm32zg_cmu.h.

#define _CMU_CMD_CALSTOP_MASK 0x10UL

Bit mask for CMU_CALSTOP

Definition at line 457 of file efm32zg_cmu.h.

#define _CMU_CMD_CALSTOP_SHIFT 4

Shift value for CMU_CALSTOP

Definition at line 456 of file efm32zg_cmu.h.

#define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 440 of file efm32zg_cmu.h.

#define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL

Mode HFRCO for CMU_CMD

Definition at line 441 of file efm32zg_cmu.h.

#define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL

Mode HFXO for CMU_CMD

Definition at line 442 of file efm32zg_cmu.h.

#define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL

Mode LFRCO for CMU_CMD

Definition at line 443 of file efm32zg_cmu.h.

#define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL

Mode LFXO for CMU_CMD

Definition at line 444 of file efm32zg_cmu.h.

#define _CMU_CMD_HFCLKSEL_MASK 0x7UL

Bit mask for CMU_HFCLKSEL

Definition at line 439 of file efm32zg_cmu.h.

#define _CMU_CMD_HFCLKSEL_SHIFT 0

Shift value for CMU_HFCLKSEL

Definition at line 438 of file efm32zg_cmu.h.

#define _CMU_CMD_MASK 0x0000001FUL

Mask for CMU_CMD

Definition at line 437 of file efm32zg_cmu.h.

#define _CMU_CMD_RESETVALUE 0x00000000UL

Default value for CMU_CMD

Definition at line 436 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL

Mode AUXHFRCO for CMU_CTRL

Definition at line 177 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 169 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL

Mode HFCLK16 for CMU_CTRL

Definition at line 175 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL

Mode HFCLK2 for CMU_CTRL

Definition at line 172 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL

Mode HFCLK4 for CMU_CTRL

Definition at line 173 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL

Mode HFCLK8 for CMU_CTRL

Definition at line 174 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL

Mode HFRCO for CMU_CTRL

Definition at line 170 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL

Mode HFXO for CMU_CTRL

Definition at line 171 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL

Bit mask for CMU_CLKOUTSEL0

Definition at line 168 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_SHIFT 20

Shift value for CMU_CLKOUTSEL0

Definition at line 167 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL

Mode ULFRCO for CMU_CTRL

Definition at line 176 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL

Mode AUXHFRCOQ for CMU_CTRL

Definition at line 197 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 189 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL

Mode HFCLK for CMU_CTRL

Definition at line 192 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL

Mode HFRCOQ for CMU_CTRL

Definition at line 196 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL

Mode HFXOQ for CMU_CTRL

Definition at line 194 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL

Mode LFRCO for CMU_CTRL

Definition at line 190 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL

Mode LFRCOQ for CMU_CTRL

Definition at line 195 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL

Mode LFXO for CMU_CTRL

Definition at line 191 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL

Mode LFXOQ for CMU_CTRL

Definition at line 193 of file efm32zg_cmu.h.

#define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL

Bit mask for CMU_CLKOUTSEL1

Definition at line 188 of file efm32zg_cmu.h.

Referenced by adcDeInit().

#define _CMU_CTRL_CLKOUTSEL1_SHIFT 23

Shift value for CMU_CLKOUTSEL1

Definition at line 187 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL

Mode 100PCENT for CMU_CTRL

Definition at line 104 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL

Mode 50PCENT for CMU_CTRL

Definition at line 100 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL

Mode 70PCENT for CMU_CTRL

Definition at line 101 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL

Mode 80PCENT for CMU_CTRL

Definition at line 102 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL

Mode DEFAULT for CMU_CTRL

Definition at line 103 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOBOOST_MASK 0xCUL

Bit mask for CMU_HFXOBOOST

Definition at line 99 of file efm32zg_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_CTRL_HFXOBOOST_SHIFT 2

Shift value for CMU_HFXOBOOST

Definition at line 98 of file efm32zg_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL

Mode DEFAULT for CMU_CTRL

Definition at line 112 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL

Bit mask for CMU_HFXOBUFCUR

Definition at line 111 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_CTRL_HFXOBUFCUR_SHIFT 5

Shift value for CMU_HFXOBUFCUR

Definition at line 110 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 117 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL

Bit mask for CMU_HFXOGLITCHDETEN

Definition at line 116 of file efm32zg_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7

Shift value for CMU_HFXOGLITCHDETEN

Definition at line 115 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL

Mode BUFEXTCLK for CMU_CTRL

Definition at line 92 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 90 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL

Mode DIGEXTCLK for CMU_CTRL

Definition at line 93 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOMODE_MASK 0x3UL

Bit mask for CMU_HFXOMODE

Definition at line 89 of file efm32zg_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_CTRL_HFXOMODE_SHIFT 0

Shift value for CMU_HFXOMODE

Definition at line 88 of file efm32zg_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL

Mode XTAL for CMU_CTRL

Definition at line 91 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL

Mode 16KCYCLES for CMU_CTRL

Definition at line 125 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL

Mode 1KCYCLES for CMU_CTRL

Definition at line 123 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL

Mode 256CYCLES for CMU_CTRL

Definition at line 122 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL

Mode 8CYCLES for CMU_CTRL

Definition at line 121 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL

Mode DEFAULT for CMU_CTRL

Definition at line 124 of file efm32zg_cmu.h.

#define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL

Bit mask for CMU_HFXOTIMEOUT

Definition at line 120 of file efm32zg_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9

Shift value for CMU_HFXOTIMEOUT

Definition at line 119 of file efm32zg_cmu.h.

Referenced by CMU_HFXOInit().

#define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL

Mode 100PCENT for CMU_CTRL

Definition at line 146 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL

Mode 70PCENT for CMU_CTRL

Definition at line 144 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL

Mode DEFAULT for CMU_CTRL

Definition at line 145 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL

Bit mask for CMU_LFXOBOOST

Definition at line 143 of file efm32zg_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_CTRL_LFXOBOOST_SHIFT 13

Shift value for CMU_LFXOBOOST

Definition at line 142 of file efm32zg_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 153 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL

Bit mask for CMU_LFXOBUFCUR

Definition at line 152 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOBUFCUR_SHIFT 17

Shift value for CMU_LFXOBUFCUR

Definition at line 151 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL

Mode BUFEXTCLK for CMU_CTRL

Definition at line 135 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 133 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL

Mode DIGEXTCLK for CMU_CTRL

Definition at line 136 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOMODE_MASK 0x1800UL

Bit mask for CMU_LFXOMODE

Definition at line 132 of file efm32zg_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_CTRL_LFXOMODE_SHIFT 11

Shift value for CMU_LFXOMODE

Definition at line 131 of file efm32zg_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL

Mode XTAL for CMU_CTRL

Definition at line 134 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL

Mode 16KCYCLES for CMU_CTRL

Definition at line 159 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL

Mode 1KCYCLES for CMU_CTRL

Definition at line 158 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL

Mode 32KCYCLES for CMU_CTRL

Definition at line 161 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL

Mode 8CYCLES for CMU_CTRL

Definition at line 157 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL

Mode DEFAULT for CMU_CTRL

Definition at line 160 of file efm32zg_cmu.h.

#define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL

Bit mask for CMU_LFXOTIMEOUT

Definition at line 156 of file efm32zg_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18

Shift value for CMU_LFXOTIMEOUT

Definition at line 155 of file efm32zg_cmu.h.

Referenced by CMU_LFXOInit().

#define _CMU_CTRL_MASK 0x07FE3EEFUL

Mask for CMU_CTRL

Definition at line 87 of file efm32zg_cmu.h.

#define _CMU_CTRL_RESETVALUE 0x000C262CUL

Default value for CMU_CTRL

Definition at line 86 of file efm32zg_cmu.h.

#define _CMU_FREEZE_MASK 0x00000001UL

Mask for CMU_FREEZE

Definition at line 841 of file efm32zg_cmu.h.

#define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_FREEZE

Definition at line 845 of file efm32zg_cmu.h.

#define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL

Mode FREEZE for CMU_FREEZE

Definition at line 847 of file efm32zg_cmu.h.

#define _CMU_FREEZE_REGFREEZE_MASK 0x1UL

Bit mask for CMU_REGFREEZE

Definition at line 844 of file efm32zg_cmu.h.

#define _CMU_FREEZE_REGFREEZE_SHIFT 0

Shift value for CMU_REGFREEZE

Definition at line 843 of file efm32zg_cmu.h.

#define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL

Mode UPDATE for CMU_FREEZE

Definition at line 846 of file efm32zg_cmu.h.

#define _CMU_FREEZE_RESETVALUE 0x00000000UL

Default value for CMU_FREEZE

Definition at line 840 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFCORECLKDIV

Definition at line 213 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL

Mode HFCLK for CMU_HFCORECLKDIV

Definition at line 214 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL

Mode HFCLK128 for CMU_HFCORECLKDIV

Definition at line 221 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL

Mode HFCLK16 for CMU_HFCORECLKDIV

Definition at line 218 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL

Mode HFCLK2 for CMU_HFCORECLKDIV

Definition at line 215 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL

Mode HFCLK256 for CMU_HFCORECLKDIV

Definition at line 222 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL

Mode HFCLK32 for CMU_HFCORECLKDIV

Definition at line 219 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL

Mode HFCLK4 for CMU_HFCORECLKDIV

Definition at line 216 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL

Mode HFCLK512 for CMU_HFCORECLKDIV

Definition at line 223 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL

Mode HFCLK64 for CMU_HFCORECLKDIV

Definition at line 220 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL

Mode HFCLK8 for CMU_HFCORECLKDIV

Definition at line 217 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL

Bit mask for CMU_HFCORECLKDIV

Definition at line 212 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), and SystemCoreClockGet().

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0

Shift value for CMU_HFCORECLKDIV

Definition at line 211 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), and SystemCoreClockGet().

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFCORECLKDIV

Definition at line 238 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL

Mode DIV2 for CMU_HFCORECLKDIV

Definition at line 239 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL

Mode DIV4 for CMU_HFCORECLKDIV

Definition at line 240 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL

Bit mask for CMU_HFCORECLKLEDIV

Definition at line 237 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8

Shift value for CMU_HFCORECLKLEDIV

Definition at line 236 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_MASK 0x0000010FUL

Mask for CMU_HFCORECLKDIV

Definition at line 210 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL

Default value for CMU_HFCORECLKDIV

Definition at line 209 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 748 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_AES_MASK 0x1UL

Bit mask for CMU_AES

Definition at line 747 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_AES_SHIFT 0

Shift value for CMU_AES

Definition at line 746 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 753 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL

Bit mask for CMU_DMA

Definition at line 752 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_DMA_SHIFT 1

Shift value for CMU_DMA

Definition at line 751 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 758 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_LE_MASK 0x4UL

Bit mask for CMU_LE

Definition at line 757 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_LE_SHIFT 2

Shift value for CMU_LE

Definition at line 756 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_HFCORECLKEN0_MASK 0x00000007UL

Mask for CMU_HFCORECLKEN0

Definition at line 744 of file efm32zg_cmu.h.

#define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL

Default value for CMU_HFCORECLKEN0

Definition at line 743 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKDIV

Definition at line 250 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL

Mode HFCLK for CMU_HFPERCLKDIV

Definition at line 251 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL

Mode HFCLK128 for CMU_HFPERCLKDIV

Definition at line 258 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL

Mode HFCLK16 for CMU_HFPERCLKDIV

Definition at line 255 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL

Mode HFCLK2 for CMU_HFPERCLKDIV

Definition at line 252 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL

Mode HFCLK256 for CMU_HFPERCLKDIV

Definition at line 259 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL

Mode HFCLK32 for CMU_HFPERCLKDIV

Definition at line 256 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL

Mode HFCLK4 for CMU_HFPERCLKDIV

Definition at line 253 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL

Mode HFCLK512 for CMU_HFPERCLKDIV

Definition at line 260 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL

Mode HFCLK64 for CMU_HFPERCLKDIV

Definition at line 257 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL

Mode HFCLK8 for CMU_HFPERCLKDIV

Definition at line 254 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL

Bit mask for CMU_HFPERCLKDIV

Definition at line 249 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), and CMU_ClockFreqGet().

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0

Shift value for CMU_HFPERCLKDIV

Definition at line 248 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), and CMU_ClockFreqGet().

#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL

Mode DEFAULT for CMU_HFPERCLKDIV

Definition at line 275 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL

Bit mask for CMU_HFPERCLKEN

Definition at line 274 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8

Shift value for CMU_HFPERCLKEN

Definition at line 273 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_MASK 0x0000010FUL

Mask for CMU_HFPERCLKDIV

Definition at line 247 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL

Default value for CMU_HFPERCLKDIV

Definition at line 246 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 777 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP0_MASK 0x4UL

Bit mask for CMU_ACMP0

Definition at line 776 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_ACMP0_SHIFT 2

Shift value for CMU_ACMP0

Definition at line 775 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 807 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_ADC0_MASK 0x400UL

Bit mask for CMU_ADC0

Definition at line 806 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_ADC0_SHIFT 10

Shift value for CMU_ADC0

Definition at line 805 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 797 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_GPIO_MASK 0x80UL

Bit mask for CMU_GPIO

Definition at line 796 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_GPIO_SHIFT 7

Shift value for CMU_GPIO

Definition at line 795 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 812 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL

Bit mask for CMU_I2C0

Definition at line 811 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_I2C0_SHIFT 11

Shift value for CMU_I2C0

Definition at line 810 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 792 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_IDAC0_MASK 0x40UL

Bit mask for CMU_IDAC0

Definition at line 791 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_IDAC0_SHIFT 6

Shift value for CMU_IDAC0

Definition at line 790 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_MASK 0x00000DDFUL

Mask for CMU_HFPERCLKEN0

Definition at line 763 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 787 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_PRS_MASK 0x10UL

Bit mask for CMU_PRS

Definition at line 786 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_PRS_SHIFT 4

Shift value for CMU_PRS

Definition at line 785 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL

Default value for CMU_HFPERCLKEN0

Definition at line 762 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 767 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL

Bit mask for CMU_TIMER0

Definition at line 766 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0

Shift value for CMU_TIMER0

Definition at line 765 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 772 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL

Bit mask for CMU_TIMER1

Definition at line 771 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1

Shift value for CMU_TIMER1

Definition at line 770 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 782 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_USART1_MASK 0x8UL

Bit mask for CMU_USART1

Definition at line 781 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_USART1_SHIFT 3

Shift value for CMU_USART1

Definition at line 780 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 802 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_VCMP_MASK 0x100UL

Bit mask for CMU_VCMP

Definition at line 801 of file efm32zg_cmu.h.

#define _CMU_HFPERCLKEN0_VCMP_SHIFT 8

Shift value for CMU_VCMP

Definition at line 800 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL

Mode 11MHZ for CMU_HFRCOCTRL

Definition at line 289 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL

Mode 14MHZ for CMU_HFRCOCTRL

Definition at line 291 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL

Mode 1MHZ for CMU_HFRCOCTRL

Definition at line 287 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL

Mode 21MHZ for CMU_HFRCOCTRL

Definition at line 292 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL

Mode 7MHZ for CMU_HFRCOCTRL

Definition at line 288 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 290 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_BAND_MASK 0x700UL

Bit mask for CMU_BAND

Definition at line 286 of file efm32zg_cmu.h.

Referenced by CMU_HFRCOBandGet(), CMU_HFRCOBandSet(), and SystemHFClockGet().

#define _CMU_HFRCOCTRL_BAND_SHIFT 8

Shift value for CMU_BAND

Definition at line 285 of file efm32zg_cmu.h.

Referenced by CMU_HFRCOBandGet(), and CMU_HFRCOBandSet().

#define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL

Mask for CMU_HFRCOCTRL

Definition at line 280 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL

Default value for CMU_HFRCOCTRL

Definition at line 279 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 301 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL

Bit mask for CMU_SUDELAY

Definition at line 300 of file efm32zg_cmu.h.

Referenced by CMU_HFRCOStartupDelayGet(), and CMU_HFRCOStartupDelaySet().

#define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12

Shift value for CMU_SUDELAY

Definition at line 299 of file efm32zg_cmu.h.

Referenced by CMU_HFRCOStartupDelayGet(), and CMU_HFRCOStartupDelaySet().

#define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 283 of file efm32zg_cmu.h.

#define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL

Bit mask for CMU_TUNING

Definition at line 282 of file efm32zg_cmu.h.

Referenced by CMU_HFRCOBandSet(), CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_HFRCOCTRL_TUNING_SHIFT 0

Shift value for CMU_TUNING

Definition at line 281 of file efm32zg_cmu.h.

Referenced by CMU_HFRCOBandSet(), CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 729 of file efm32zg_cmu.h.

#define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 728 of file efm32zg_cmu.h.

#define _CMU_IEN_AUXHFRCORDY_SHIFT 4

Shift value for CMU_AUXHFRCORDY

Definition at line 727 of file efm32zg_cmu.h.

#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 739 of file efm32zg_cmu.h.

#define _CMU_IEN_CALOF_MASK 0x40UL

Bit mask for CMU_CALOF

Definition at line 738 of file efm32zg_cmu.h.

#define _CMU_IEN_CALOF_SHIFT 6

Shift value for CMU_CALOF

Definition at line 737 of file efm32zg_cmu.h.

#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 734 of file efm32zg_cmu.h.

#define _CMU_IEN_CALRDY_MASK 0x20UL

Bit mask for CMU_CALRDY

Definition at line 733 of file efm32zg_cmu.h.

#define _CMU_IEN_CALRDY_SHIFT 5

Shift value for CMU_CALRDY

Definition at line 732 of file efm32zg_cmu.h.

#define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 709 of file efm32zg_cmu.h.

#define _CMU_IEN_HFRCORDY_MASK 0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 708 of file efm32zg_cmu.h.

#define _CMU_IEN_HFRCORDY_SHIFT 0

Shift value for CMU_HFRCORDY

Definition at line 707 of file efm32zg_cmu.h.

#define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 714 of file efm32zg_cmu.h.

#define _CMU_IEN_HFXORDY_MASK 0x2UL

Bit mask for CMU_HFXORDY

Definition at line 713 of file efm32zg_cmu.h.

#define _CMU_IEN_HFXORDY_SHIFT 1

Shift value for CMU_HFXORDY

Definition at line 712 of file efm32zg_cmu.h.

#define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 719 of file efm32zg_cmu.h.

#define _CMU_IEN_LFRCORDY_MASK 0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 718 of file efm32zg_cmu.h.

#define _CMU_IEN_LFRCORDY_SHIFT 2

Shift value for CMU_LFRCORDY

Definition at line 717 of file efm32zg_cmu.h.

#define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 724 of file efm32zg_cmu.h.

#define _CMU_IEN_LFXORDY_MASK 0x8UL

Bit mask for CMU_LFXORDY

Definition at line 723 of file efm32zg_cmu.h.

#define _CMU_IEN_LFXORDY_SHIFT 3

Shift value for CMU_LFXORDY

Definition at line 722 of file efm32zg_cmu.h.

#define _CMU_IEN_MASK 0x0000007FUL

Mask for CMU_IEN

Definition at line 705 of file efm32zg_cmu.h.

#define _CMU_IEN_RESETVALUE 0x00000000UL

Default value for CMU_IEN

Definition at line 704 of file efm32zg_cmu.h.

#define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 612 of file efm32zg_cmu.h.

#define _CMU_IF_AUXHFRCORDY_MASK 0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 611 of file efm32zg_cmu.h.

#define _CMU_IF_AUXHFRCORDY_SHIFT 4

Shift value for CMU_AUXHFRCORDY

Definition at line 610 of file efm32zg_cmu.h.

#define _CMU_IF_CALOF_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 622 of file efm32zg_cmu.h.

#define _CMU_IF_CALOF_MASK 0x40UL

Bit mask for CMU_CALOF

Definition at line 621 of file efm32zg_cmu.h.

#define _CMU_IF_CALOF_SHIFT 6

Shift value for CMU_CALOF

Definition at line 620 of file efm32zg_cmu.h.

#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 617 of file efm32zg_cmu.h.

#define _CMU_IF_CALRDY_MASK 0x20UL

Bit mask for CMU_CALRDY

Definition at line 616 of file efm32zg_cmu.h.

#define _CMU_IF_CALRDY_SHIFT 5

Shift value for CMU_CALRDY

Definition at line 615 of file efm32zg_cmu.h.

#define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL

Mode DEFAULT for CMU_IF

Definition at line 592 of file efm32zg_cmu.h.

#define _CMU_IF_HFRCORDY_MASK 0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 591 of file efm32zg_cmu.h.

#define _CMU_IF_HFRCORDY_SHIFT 0

Shift value for CMU_HFRCORDY

Definition at line 590 of file efm32zg_cmu.h.

#define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 597 of file efm32zg_cmu.h.

#define _CMU_IF_HFXORDY_MASK 0x2UL

Bit mask for CMU_HFXORDY

Definition at line 596 of file efm32zg_cmu.h.

#define _CMU_IF_HFXORDY_SHIFT 1

Shift value for CMU_HFXORDY

Definition at line 595 of file efm32zg_cmu.h.

#define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 602 of file efm32zg_cmu.h.

#define _CMU_IF_LFRCORDY_MASK 0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 601 of file efm32zg_cmu.h.

#define _CMU_IF_LFRCORDY_SHIFT 2

Shift value for CMU_LFRCORDY

Definition at line 600 of file efm32zg_cmu.h.

#define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 607 of file efm32zg_cmu.h.

#define _CMU_IF_LFXORDY_MASK 0x8UL

Bit mask for CMU_LFXORDY

Definition at line 606 of file efm32zg_cmu.h.

#define _CMU_IF_LFXORDY_SHIFT 3

Shift value for CMU_LFXORDY

Definition at line 605 of file efm32zg_cmu.h.

#define _CMU_IF_MASK 0x0000007FUL

Mask for CMU_IF

Definition at line 588 of file efm32zg_cmu.h.

#define _CMU_IF_RESETVALUE 0x00000001UL

Default value for CMU_IF

Definition at line 587 of file efm32zg_cmu.h.

#define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 690 of file efm32zg_cmu.h.

#define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 689 of file efm32zg_cmu.h.

#define _CMU_IFC_AUXHFRCORDY_SHIFT 4

Shift value for CMU_AUXHFRCORDY

Definition at line 688 of file efm32zg_cmu.h.

#define _CMU_IFC_CALOF_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 700 of file efm32zg_cmu.h.

#define _CMU_IFC_CALOF_MASK 0x40UL

Bit mask for CMU_CALOF

Definition at line 699 of file efm32zg_cmu.h.

#define _CMU_IFC_CALOF_SHIFT 6

Shift value for CMU_CALOF

Definition at line 698 of file efm32zg_cmu.h.

#define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 695 of file efm32zg_cmu.h.

#define _CMU_IFC_CALRDY_MASK 0x20UL

Bit mask for CMU_CALRDY

Definition at line 694 of file efm32zg_cmu.h.

#define _CMU_IFC_CALRDY_SHIFT 5

Shift value for CMU_CALRDY

Definition at line 693 of file efm32zg_cmu.h.

#define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 670 of file efm32zg_cmu.h.

#define _CMU_IFC_HFRCORDY_MASK 0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 669 of file efm32zg_cmu.h.

#define _CMU_IFC_HFRCORDY_SHIFT 0

Shift value for CMU_HFRCORDY

Definition at line 668 of file efm32zg_cmu.h.

#define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 675 of file efm32zg_cmu.h.

#define _CMU_IFC_HFXORDY_MASK 0x2UL

Bit mask for CMU_HFXORDY

Definition at line 674 of file efm32zg_cmu.h.

#define _CMU_IFC_HFXORDY_SHIFT 1

Shift value for CMU_HFXORDY

Definition at line 673 of file efm32zg_cmu.h.

#define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 680 of file efm32zg_cmu.h.

#define _CMU_IFC_LFRCORDY_MASK 0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 679 of file efm32zg_cmu.h.

#define _CMU_IFC_LFRCORDY_SHIFT 2

Shift value for CMU_LFRCORDY

Definition at line 678 of file efm32zg_cmu.h.

#define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 685 of file efm32zg_cmu.h.

#define _CMU_IFC_LFXORDY_MASK 0x8UL

Bit mask for CMU_LFXORDY

Definition at line 684 of file efm32zg_cmu.h.

#define _CMU_IFC_LFXORDY_SHIFT 3

Shift value for CMU_LFXORDY

Definition at line 683 of file efm32zg_cmu.h.

#define _CMU_IFC_MASK 0x0000007FUL

Mask for CMU_IFC

Definition at line 666 of file efm32zg_cmu.h.

#define _CMU_IFC_RESETVALUE 0x00000000UL

Default value for CMU_IFC

Definition at line 665 of file efm32zg_cmu.h.

#define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 651 of file efm32zg_cmu.h.

#define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 650 of file efm32zg_cmu.h.

#define _CMU_IFS_AUXHFRCORDY_SHIFT 4

Shift value for CMU_AUXHFRCORDY

Definition at line 649 of file efm32zg_cmu.h.

#define _CMU_IFS_CALOF_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 661 of file efm32zg_cmu.h.

#define _CMU_IFS_CALOF_MASK 0x40UL

Bit mask for CMU_CALOF

Definition at line 660 of file efm32zg_cmu.h.

#define _CMU_IFS_CALOF_SHIFT 6

Shift value for CMU_CALOF

Definition at line 659 of file efm32zg_cmu.h.

#define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 656 of file efm32zg_cmu.h.

#define _CMU_IFS_CALRDY_MASK 0x20UL

Bit mask for CMU_CALRDY

Definition at line 655 of file efm32zg_cmu.h.

#define _CMU_IFS_CALRDY_SHIFT 5

Shift value for CMU_CALRDY

Definition at line 654 of file efm32zg_cmu.h.

#define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 631 of file efm32zg_cmu.h.

#define _CMU_IFS_HFRCORDY_MASK 0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 630 of file efm32zg_cmu.h.

#define _CMU_IFS_HFRCORDY_SHIFT 0

Shift value for CMU_HFRCORDY

Definition at line 629 of file efm32zg_cmu.h.

#define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 636 of file efm32zg_cmu.h.

#define _CMU_IFS_HFXORDY_MASK 0x2UL

Bit mask for CMU_HFXORDY

Definition at line 635 of file efm32zg_cmu.h.

#define _CMU_IFS_HFXORDY_SHIFT 1

Shift value for CMU_HFXORDY

Definition at line 634 of file efm32zg_cmu.h.

#define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 641 of file efm32zg_cmu.h.

#define _CMU_IFS_LFRCORDY_MASK 0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 640 of file efm32zg_cmu.h.

#define _CMU_IFS_LFRCORDY_SHIFT 2

Shift value for CMU_LFRCORDY

Definition at line 639 of file efm32zg_cmu.h.

#define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 646 of file efm32zg_cmu.h.

#define _CMU_IFS_LFXORDY_MASK 0x8UL

Bit mask for CMU_LFXORDY

Definition at line 645 of file efm32zg_cmu.h.

#define _CMU_IFS_LFXORDY_SHIFT 3

Shift value for CMU_LFXORDY

Definition at line 644 of file efm32zg_cmu.h.

#define _CMU_IFS_MASK 0x0000007FUL

Mask for CMU_IFS

Definition at line 627 of file efm32zg_cmu.h.

#define _CMU_IFS_RESETVALUE 0x00000000UL

Default value for CMU_IFS

Definition at line 626 of file efm32zg_cmu.h.

#define _CMU_LFACLKEN0_MASK 0x00000001UL

Mask for CMU_LFACLKEN0

Definition at line 854 of file efm32zg_cmu.h.

#define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL

Default value for CMU_LFACLKEN0

Definition at line 853 of file efm32zg_cmu.h.

#define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_LFACLKEN0

Definition at line 858 of file efm32zg_cmu.h.

#define _CMU_LFACLKEN0_RTC_MASK 0x1UL

Bit mask for CMU_RTC

Definition at line 857 of file efm32zg_cmu.h.

#define _CMU_LFACLKEN0_RTC_SHIFT 0

Shift value for CMU_RTC

Definition at line 856 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_MASK 0x0000000FUL

Mask for CMU_LFAPRESC0

Definition at line 872 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL

Default value for CMU_LFAPRESC0

Definition at line 871 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL

Mode DIV1 for CMU_LFAPRESC0

Definition at line 875 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL

Mode DIV1024 for CMU_LFAPRESC0

Definition at line 885 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL

Mode DIV128 for CMU_LFAPRESC0

Definition at line 882 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL

Mode DIV16 for CMU_LFAPRESC0

Definition at line 879 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL

Mode DIV16384 for CMU_LFAPRESC0

Definition at line 889 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL

Mode DIV2 for CMU_LFAPRESC0

Definition at line 876 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL

Mode DIV2048 for CMU_LFAPRESC0

Definition at line 886 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL

Mode DIV256 for CMU_LFAPRESC0

Definition at line 883 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL

Mode DIV32 for CMU_LFAPRESC0

Definition at line 880 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL

Mode DIV32768 for CMU_LFAPRESC0

Definition at line 890 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL

Mode DIV4 for CMU_LFAPRESC0

Definition at line 877 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL

Mode DIV4096 for CMU_LFAPRESC0

Definition at line 887 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL

Mode DIV512 for CMU_LFAPRESC0

Definition at line 884 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL

Mode DIV64 for CMU_LFAPRESC0

Definition at line 881 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL

Mode DIV8 for CMU_LFAPRESC0

Definition at line 878 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL

Mode DIV8192 for CMU_LFAPRESC0

Definition at line 888 of file efm32zg_cmu.h.

#define _CMU_LFAPRESC0_RTC_MASK 0xFUL

Bit mask for CMU_RTC

Definition at line 874 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), and CMU_ClockFreqGet().

#define _CMU_LFAPRESC0_RTC_SHIFT 0

Shift value for CMU_RTC

Definition at line 873 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), and CMU_ClockFreqGet().

#define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_LFBCLKEN0

Definition at line 867 of file efm32zg_cmu.h.

#define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL

Bit mask for CMU_LEUART0

Definition at line 866 of file efm32zg_cmu.h.

#define _CMU_LFBCLKEN0_LEUART0_SHIFT 0

Shift value for CMU_LEUART0

Definition at line 865 of file efm32zg_cmu.h.

#define _CMU_LFBCLKEN0_MASK 0x00000001UL

Mask for CMU_LFBCLKEN0

Definition at line 863 of file efm32zg_cmu.h.

#define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL

Default value for CMU_LFBCLKEN0

Definition at line 862 of file efm32zg_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL

Mode DIV1 for CMU_LFBPRESC0

Definition at line 913 of file efm32zg_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL

Mode DIV2 for CMU_LFBPRESC0

Definition at line 914 of file efm32zg_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL

Mode DIV4 for CMU_LFBPRESC0

Definition at line 915 of file efm32zg_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL

Mode DIV8 for CMU_LFBPRESC0

Definition at line 916 of file efm32zg_cmu.h.

#define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL

Bit mask for CMU_LEUART0

Definition at line 912 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), CMU_ClockFreqGet(), and UARTDRV_InitLeuart().

#define _CMU_LFBPRESC0_LEUART0_SHIFT 0

Shift value for CMU_LEUART0

Definition at line 911 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivGet(), CMU_ClockDivSet(), CMU_ClockFreqGet(), and UARTDRV_InitLeuart().

#define _CMU_LFBPRESC0_MASK 0x00000003UL

Mask for CMU_LFBPRESC0

Definition at line 910 of file efm32zg_cmu.h.

#define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL

Default value for CMU_LFBPRESC0

Definition at line 909 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL

Mode DEFAULT for CMU_LFCLKSEL

Definition at line 467 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL

Mode DISABLED for CMU_LFCLKSEL

Definition at line 466 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL

Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL

Definition at line 470 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL

Mode LFRCO for CMU_LFCLKSEL

Definition at line 468 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL

Mode LFXO for CMU_LFCLKSEL

Definition at line 469 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFA_MASK 0x3UL

Bit mask for CMU_LFA

Definition at line 465 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet(), and CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFA_SHIFT 0

Shift value for CMU_LFA

Definition at line 464 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_LFCLKSEL

Definition at line 491 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL

Mode DISABLED for CMU_LFCLKSEL

Definition at line 492 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL

Bit mask for CMU_LFAE

Definition at line 490 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet(), and CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFAE_SHIFT 16

Shift value for CMU_LFAE

Definition at line 489 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL

Mode ULFRCO for CMU_LFCLKSEL

Definition at line 493 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL

Mode DEFAULT for CMU_LFCLKSEL

Definition at line 479 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL

Mode DISABLED for CMU_LFCLKSEL

Definition at line 478 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL

Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL

Definition at line 482 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL

Mode LFRCO for CMU_LFCLKSEL

Definition at line 480 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL

Mode LFXO for CMU_LFCLKSEL

Definition at line 481 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFB_MASK 0xCUL

Bit mask for CMU_LFB

Definition at line 477 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet(), and CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFB_SHIFT 2

Shift value for CMU_LFB

Definition at line 476 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_LFCLKSEL

Definition at line 500 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL

Mode DISABLED for CMU_LFCLKSEL

Definition at line 501 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL

Bit mask for CMU_LFBE

Definition at line 499 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet(), and CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFBE_SHIFT 20

Shift value for CMU_LFBE

Definition at line 498 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL

Mode ULFRCO for CMU_LFCLKSEL

Definition at line 502 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_MASK 0x0011000FUL

Mask for CMU_LFCLKSEL

Definition at line 463 of file efm32zg_cmu.h.

#define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL

Default value for CMU_LFCLKSEL

Definition at line 462 of file efm32zg_cmu.h.

#define _CMU_LFRCOCTRL_MASK 0x0000007FUL

Mask for CMU_LFRCOCTRL

Definition at line 306 of file efm32zg_cmu.h.

#define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL

Default value for CMU_LFRCOCTRL

Definition at line 305 of file efm32zg_cmu.h.

#define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL

Mode DEFAULT for CMU_LFRCOCTRL

Definition at line 309 of file efm32zg_cmu.h.

#define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL

Bit mask for CMU_TUNING

Definition at line 308 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_LFRCOCTRL_TUNING_SHIFT 0

Shift value for CMU_TUNING

Definition at line 307 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorTuningGet(), and CMU_OscillatorTuningSet().

#define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_LOCK

Definition at line 969 of file efm32zg_cmu.h.

#define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL

Mode LOCK for CMU_LOCK

Definition at line 970 of file efm32zg_cmu.h.

#define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL

Mode LOCKED for CMU_LOCK

Definition at line 972 of file efm32zg_cmu.h.

#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL

Bit mask for CMU_LOCKKEY

Definition at line 968 of file efm32zg_cmu.h.

#define _CMU_LOCK_LOCKKEY_SHIFT 0

Shift value for CMU_LOCKKEY

Definition at line 967 of file efm32zg_cmu.h.

#define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL

Mode UNLOCK for CMU_LOCK

Definition at line 973 of file efm32zg_cmu.h.

#define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL

Mode UNLOCKED for CMU_LOCK

Definition at line 971 of file efm32zg_cmu.h.

#define _CMU_LOCK_MASK 0x0000FFFFUL

Mask for CMU_LOCK

Definition at line 966 of file efm32zg_cmu.h.

#define _CMU_LOCK_RESETVALUE 0x00000000UL

Default value for CMU_LOCK

Definition at line 965 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 412 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL

Bit mask for CMU_AUXHFRCODIS

Definition at line 411 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5

Shift value for CMU_AUXHFRCODIS

Definition at line 410 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 407 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL

Bit mask for CMU_AUXHFRCOEN

Definition at line 406 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4

Shift value for CMU_AUXHFRCOEN

Definition at line 405 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 392 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL

Bit mask for CMU_HFRCODIS

Definition at line 391 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFRCODIS_SHIFT 1

Shift value for CMU_HFRCODIS

Definition at line 390 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 387 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL

Bit mask for CMU_HFRCOEN

Definition at line 386 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFRCOEN_SHIFT 0

Shift value for CMU_HFRCOEN

Definition at line 385 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 402 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL

Bit mask for CMU_HFXODIS

Definition at line 401 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFXODIS_SHIFT 3

Shift value for CMU_HFXODIS

Definition at line 400 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 397 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL

Bit mask for CMU_HFXOEN

Definition at line 396 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_HFXOEN_SHIFT 2

Shift value for CMU_HFXOEN

Definition at line 395 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 422 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL

Bit mask for CMU_LFRCODIS

Definition at line 421 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFRCODIS_SHIFT 7

Shift value for CMU_LFRCODIS

Definition at line 420 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 417 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL

Bit mask for CMU_LFRCOEN

Definition at line 416 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFRCOEN_SHIFT 6

Shift value for CMU_LFRCOEN

Definition at line 415 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 432 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL

Bit mask for CMU_LFXODIS

Definition at line 431 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFXODIS_SHIFT 9

Shift value for CMU_LFXODIS

Definition at line 430 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 427 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL

Bit mask for CMU_LFXOEN

Definition at line 426 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_LFXOEN_SHIFT 8

Shift value for CMU_LFXOEN

Definition at line 425 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_MASK 0x000003FFUL

Mask for CMU_OSCENCMD

Definition at line 383 of file efm32zg_cmu.h.

#define _CMU_OSCENCMD_RESETVALUE 0x00000000UL

Default value for CMU_OSCENCMD

Definition at line 382 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_MASK 0x00000003UL

Mask for CMU_PCNTCTRL

Definition at line 924 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_PCNTCTRL

Definition at line 928 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL

Bit mask for CMU_PCNT0CLKEN

Definition at line 927 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0

Shift value for CMU_PCNT0CLKEN

Definition at line 926 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_PCNTCTRL

Definition at line 933 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL

Mode LFACLK for CMU_PCNTCTRL

Definition at line 934 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL

Bit mask for CMU_PCNT0CLKSEL

Definition at line 932 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL

Mode PCNT0S0 for CMU_PCNTCTRL

Definition at line 935 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1

Shift value for CMU_PCNT0CLKSEL

Definition at line 931 of file efm32zg_cmu.h.

#define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL

Default value for CMU_PCNTCTRL

Definition at line 923 of file efm32zg_cmu.h.

#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_ROUTE

Definition at line 946 of file efm32zg_cmu.h.

#define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL

Bit mask for CMU_CLKOUT0PEN

Definition at line 945 of file efm32zg_cmu.h.

#define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0

Shift value for CMU_CLKOUT0PEN

Definition at line 944 of file efm32zg_cmu.h.

#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_ROUTE

Definition at line 951 of file efm32zg_cmu.h.

#define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL

Bit mask for CMU_CLKOUT1PEN

Definition at line 950 of file efm32zg_cmu.h.

#define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1

Shift value for CMU_CLKOUT1PEN

Definition at line 949 of file efm32zg_cmu.h.

#define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_ROUTE

Definition at line 956 of file efm32zg_cmu.h.

#define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL

Mode LOC0 for CMU_ROUTE

Definition at line 955 of file efm32zg_cmu.h.

#define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL

Mode LOC1 for CMU_ROUTE

Definition at line 957 of file efm32zg_cmu.h.

#define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL

Mode LOC2 for CMU_ROUTE

Definition at line 958 of file efm32zg_cmu.h.

#define _CMU_ROUTE_LOCATION_MASK 0x1CUL

Bit mask for CMU_LOCATION

Definition at line 954 of file efm32zg_cmu.h.

#define _CMU_ROUTE_LOCATION_SHIFT 2

Shift value for CMU_LOCATION

Definition at line 953 of file efm32zg_cmu.h.

#define _CMU_ROUTE_MASK 0x0000001FUL

Mask for CMU_ROUTE

Definition at line 942 of file efm32zg_cmu.h.

#define _CMU_ROUTE_RESETVALUE 0x00000000UL

Default value for CMU_ROUTE

Definition at line 941 of file efm32zg_cmu.h.

#define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 533 of file efm32zg_cmu.h.

#define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL

Bit mask for CMU_AUXHFRCOENS

Definition at line 532 of file efm32zg_cmu.h.

#define _CMU_STATUS_AUXHFRCOENS_SHIFT 4

Shift value for CMU_AUXHFRCOENS

Definition at line 531 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 538 of file efm32zg_cmu.h.

#define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 537 of file efm32zg_cmu.h.

#define _CMU_STATUS_AUXHFRCORDY_SHIFT 5

Shift value for CMU_AUXHFRCORDY

Definition at line 536 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 583 of file efm32zg_cmu.h.

#define _CMU_STATUS_CALBSY_MASK 0x4000UL

Bit mask for CMU_CALBSY

Definition at line 582 of file efm32zg_cmu.h.

#define _CMU_STATUS_CALBSY_SHIFT 14

Shift value for CMU_CALBSY

Definition at line 581 of file efm32zg_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateCountGet().

#define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL

Mode DEFAULT for CMU_STATUS

Definition at line 513 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFRCOENS_MASK 0x1UL

Bit mask for CMU_HFRCOENS

Definition at line 512 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFRCOENS_SHIFT 0

Shift value for CMU_HFRCOENS

Definition at line 511 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL

Mode DEFAULT for CMU_STATUS

Definition at line 518 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFRCORDY_MASK 0x2UL

Bit mask for CMU_HFRCORDY

Definition at line 517 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFRCORDY_SHIFT 1

Shift value for CMU_HFRCORDY

Definition at line 516 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL

Mode DEFAULT for CMU_STATUS

Definition at line 563 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFRCOSEL_MASK 0x400UL

Bit mask for CMU_HFRCOSEL

Definition at line 562 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFRCOSEL_SHIFT 10

Shift value for CMU_HFRCOSEL

Definition at line 561 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 523 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFXOENS_MASK 0x4UL

Bit mask for CMU_HFXOENS

Definition at line 522 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFXOENS_SHIFT 2

Shift value for CMU_HFXOENS

Definition at line 521 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 528 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFXORDY_MASK 0x8UL

Bit mask for CMU_HFXORDY

Definition at line 527 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFXORDY_SHIFT 3

Shift value for CMU_HFXORDY

Definition at line 526 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 568 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFXOSEL_MASK 0x800UL

Bit mask for CMU_HFXOSEL

Definition at line 567 of file efm32zg_cmu.h.

#define _CMU_STATUS_HFXOSEL_SHIFT 11

Shift value for CMU_HFXOSEL

Definition at line 566 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 543 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFRCOENS_MASK 0x40UL

Bit mask for CMU_LFRCOENS

Definition at line 542 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFRCOENS_SHIFT 6

Shift value for CMU_LFRCOENS

Definition at line 541 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 548 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFRCORDY_MASK 0x80UL

Bit mask for CMU_LFRCORDY

Definition at line 547 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFRCORDY_SHIFT 7

Shift value for CMU_LFRCORDY

Definition at line 546 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 573 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL

Bit mask for CMU_LFRCOSEL

Definition at line 572 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFRCOSEL_SHIFT 12

Shift value for CMU_LFRCOSEL

Definition at line 571 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 553 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFXOENS_MASK 0x100UL

Bit mask for CMU_LFXOENS

Definition at line 552 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFXOENS_SHIFT 8

Shift value for CMU_LFXOENS

Definition at line 551 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 558 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFXORDY_MASK 0x200UL

Bit mask for CMU_LFXORDY

Definition at line 557 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFXORDY_SHIFT 9

Shift value for CMU_LFXORDY

Definition at line 556 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 578 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFXOSEL_MASK 0x2000UL

Bit mask for CMU_LFXOSEL

Definition at line 577 of file efm32zg_cmu.h.

#define _CMU_STATUS_LFXOSEL_SHIFT 13

Shift value for CMU_LFXOSEL

Definition at line 576 of file efm32zg_cmu.h.

#define _CMU_STATUS_MASK 0x00007FFFUL

Mask for CMU_STATUS

Definition at line 509 of file efm32zg_cmu.h.

#define _CMU_STATUS_RESETVALUE 0x00000403UL

Default value for CMU_STATUS

Definition at line 508 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_SYNCBUSY

Definition at line 821 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL

Bit mask for CMU_LFACLKEN0

Definition at line 820 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0

Shift value for CMU_LFACLKEN0

Definition at line 819 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_SYNCBUSY

Definition at line 826 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL

Bit mask for CMU_LFAPRESC0

Definition at line 825 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2

Shift value for CMU_LFAPRESC0

Definition at line 824 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_SYNCBUSY

Definition at line 831 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL

Bit mask for CMU_LFBCLKEN0

Definition at line 830 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4

Shift value for CMU_LFBCLKEN0

Definition at line 829 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL

Mode DEFAULT for CMU_SYNCBUSY

Definition at line 836 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL

Bit mask for CMU_LFBPRESC0

Definition at line 835 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6

Shift value for CMU_LFBPRESC0

Definition at line 834 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_MASK 0x00000055UL

Mask for CMU_SYNCBUSY

Definition at line 817 of file efm32zg_cmu.h.

#define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL

Default value for CMU_SYNCBUSY

Definition at line 816 of file efm32zg_cmu.h.

#define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)

Shifted mode 11MHZ for CMU_AUXHFRCOCTRL

Definition at line 329 of file efm32zg_cmu.h.

#define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)

Shifted mode 14MHZ for CMU_AUXHFRCOCTRL

Definition at line 328 of file efm32zg_cmu.h.

#define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)

Shifted mode 1MHZ for CMU_AUXHFRCOCTRL

Definition at line 331 of file efm32zg_cmu.h.

#define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)

Shifted mode 21MHZ for CMU_AUXHFRCOCTRL

Definition at line 332 of file efm32zg_cmu.h.

#define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)

Shifted mode 7MHZ for CMU_AUXHFRCOCTRL

Definition at line 330 of file efm32zg_cmu.h.

#define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)

Shifted mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 327 of file efm32zg_cmu.h.

#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)

Shifted mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 318 of file efm32zg_cmu.h.

#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)

Shifted mode DEFAULT for CMU_CALCNT

Definition at line 379 of file efm32zg_cmu.h.

#define CMU_CALCTRL_CONT (0x1UL << 6)

Continuous Calibration

Definition at line 367 of file efm32zg_cmu.h.

#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6)

Shifted mode DEFAULT for CMU_CALCTRL

Definition at line 371 of file efm32zg_cmu.h.

#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)

Shifted mode AUXHFRCO for CMU_CALCTRL

Definition at line 366 of file efm32zg_cmu.h.

Referenced by CMU_CalibrateConfig().

#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)

Shifted mode DEFAULT for CMU_CALCTRL

Definition at line 360 of file efm32zg_cmu.h.

#define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)

Shifted mode HFCLK for CMU_CALCTRL

Definition at line 361 of file efm32zg_cmu.h.

#define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)

Shifted mode HFRCO for CMU_CALCTRL

Definition at line 364 of file efm32zg_cmu.h.

Referenced by CMU_CalibrateConfig().

#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3)

Shifted mode HFXO for CMU_CALCTRL

Definition at line 362 of file efm32zg_cmu.h.

Referenced by CMU_CalibrateConfig().

#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)

Shifted mode LFRCO for CMU_CALCTRL

Definition at line 365 of file efm32zg_cmu.h.

Referenced by CMU_CalibrateConfig().

#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3)

Shifted mode LFXO for CMU_CALCTRL

Definition at line 363 of file efm32zg_cmu.h.

Referenced by CMU_CalibrateConfig().

#define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)

Shifted mode AUXHFRCO for CMU_CALCTRL

Definition at line 350 of file efm32zg_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)

Shifted mode DEFAULT for CMU_CALCTRL

Definition at line 345 of file efm32zg_cmu.h.

#define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)

Shifted mode HFRCO for CMU_CALCTRL

Definition at line 348 of file efm32zg_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)

Shifted mode HFXO for CMU_CALCTRL

Definition at line 346 of file efm32zg_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)

Shifted mode LFRCO for CMU_CALCTRL

Definition at line 349 of file efm32zg_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)

Shifted mode LFXO for CMU_CALCTRL

Definition at line 347 of file efm32zg_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateConfig().

#define CMU_CMD_CALSTART (0x1UL << 3)

Calibration Start

Definition at line 450 of file efm32zg_cmu.h.

Referenced by CMU_Calibrate(), and CMU_CalibrateStart().

#define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)

Shifted mode DEFAULT for CMU_CMD

Definition at line 454 of file efm32zg_cmu.h.

#define CMU_CMD_CALSTOP (0x1UL << 4)

Calibration Stop

Definition at line 455 of file efm32zg_cmu.h.

Referenced by CMU_CalibrateStop().

#define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4)

Shifted mode DEFAULT for CMU_CMD

Definition at line 459 of file efm32zg_cmu.h.

#define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)

Shifted mode DEFAULT for CMU_CMD

Definition at line 445 of file efm32zg_cmu.h.

#define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)

Shifted mode HFRCO for CMU_CMD

Definition at line 446 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)

Shifted mode HFXO for CMU_CMD

Definition at line 447 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)

Shifted mode LFRCO for CMU_CMD

Definition at line 448 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)

Shifted mode LFXO for CMU_CMD

Definition at line 449 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectSet().

#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)

Shifted mode AUXHFRCO for CMU_CTRL

Definition at line 186 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 178 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)

Shifted mode HFCLK16 for CMU_CTRL

Definition at line 184 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)

Shifted mode HFCLK2 for CMU_CTRL

Definition at line 181 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)

Shifted mode HFCLK4 for CMU_CTRL

Definition at line 182 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)

Shifted mode HFCLK8 for CMU_CTRL

Definition at line 183 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)

Shifted mode HFRCO for CMU_CTRL

Definition at line 179 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)

Shifted mode HFXO for CMU_CTRL

Definition at line 180 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)

Shifted mode ULFRCO for CMU_CTRL

Definition at line 185 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)

Shifted mode AUXHFRCOQ for CMU_CTRL

Definition at line 206 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 198 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)

Shifted mode HFCLK for CMU_CTRL

Definition at line 201 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)

Shifted mode HFRCOQ for CMU_CTRL

Definition at line 205 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)

Shifted mode HFXOQ for CMU_CTRL

Definition at line 203 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)

Shifted mode LFRCO for CMU_CTRL

Definition at line 199 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)

Shifted mode LFRCOQ for CMU_CTRL

Definition at line 204 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)

Shifted mode LFXO for CMU_CTRL

Definition at line 200 of file efm32zg_cmu.h.

#define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)

Shifted mode LFXOQ for CMU_CTRL

Definition at line 202 of file efm32zg_cmu.h.

Referenced by MIC_init().

#define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)

Shifted mode 100PCENT for CMU_CTRL

Definition at line 109 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)

Shifted mode 50PCENT for CMU_CTRL

Definition at line 105 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)

Shifted mode 70PCENT for CMU_CTRL

Definition at line 106 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)

Shifted mode 80PCENT for CMU_CTRL

Definition at line 107 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 108 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 113 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)

HFXO Glitch Detector Enable

Definition at line 114 of file efm32zg_cmu.h.

Referenced by CMU_HFXOInit().

#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 118 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)

Shifted mode BUFEXTCLK for CMU_CTRL

Definition at line 96 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 94 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)

Shifted mode DIGEXTCLK for CMU_CTRL

Definition at line 97 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)

Shifted mode XTAL for CMU_CTRL

Definition at line 95 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)

Shifted mode 16KCYCLES for CMU_CTRL

Definition at line 130 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)

Shifted mode 1KCYCLES for CMU_CTRL

Definition at line 128 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)

Shifted mode 256CYCLES for CMU_CTRL

Definition at line 127 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)

Shifted mode 8CYCLES for CMU_CTRL

Definition at line 126 of file efm32zg_cmu.h.

#define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 129 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOBOOST (0x1UL << 13)

LFXO Start-up Boost Current

Definition at line 141 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)

Shifted mode 100PCENT for CMU_CTRL

Definition at line 149 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)

Shifted mode 70PCENT for CMU_CTRL

Definition at line 147 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 148 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)

LFXO Boost Buffer Current

Definition at line 150 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 154 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)

Shifted mode BUFEXTCLK for CMU_CTRL

Definition at line 139 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 137 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)

Shifted mode DIGEXTCLK for CMU_CTRL

Definition at line 140 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)

Shifted mode XTAL for CMU_CTRL

Definition at line 138 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)

Shifted mode 16KCYCLES for CMU_CTRL

Definition at line 164 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)

Shifted mode 1KCYCLES for CMU_CTRL

Definition at line 163 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)

Shifted mode 32KCYCLES for CMU_CTRL

Definition at line 166 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)

Shifted mode 8CYCLES for CMU_CTRL

Definition at line 162 of file efm32zg_cmu.h.

#define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 165 of file efm32zg_cmu.h.

#define CMU_FREEZE_REGFREEZE (0x1UL << 0)

Register Update Freeze

Definition at line 842 of file efm32zg_cmu.h.

Referenced by CMU_FreezeEnable().

#define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)

Shifted mode DEFAULT for CMU_FREEZE

Definition at line 848 of file efm32zg_cmu.h.

#define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)

Shifted mode FREEZE for CMU_FREEZE

Definition at line 850 of file efm32zg_cmu.h.

#define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)

Shifted mode UPDATE for CMU_FREEZE

Definition at line 849 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFCORECLKDIV

Definition at line 224 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)

Shifted mode HFCLK for CMU_HFCORECLKDIV

Definition at line 225 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)

Shifted mode HFCLK128 for CMU_HFCORECLKDIV

Definition at line 232 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)

Shifted mode HFCLK16 for CMU_HFCORECLKDIV

Definition at line 229 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)

Shifted mode HFCLK2 for CMU_HFCORECLKDIV

Definition at line 226 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)

Shifted mode HFCLK256 for CMU_HFCORECLKDIV

Definition at line 233 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)

Shifted mode HFCLK32 for CMU_HFCORECLKDIV

Definition at line 230 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)

Shifted mode HFCLK4 for CMU_HFCORECLKDIV

Definition at line 227 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)

Shifted mode HFCLK512 for CMU_HFCORECLKDIV

Definition at line 234 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)

Shifted mode HFCLK64 for CMU_HFCORECLKDIV

Definition at line 231 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)

Shifted mode HFCLK8 for CMU_HFCORECLKDIV

Definition at line 228 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8)

Additional Division Factor For HFCORECLKLE

Definition at line 235 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8)

Shifted mode DEFAULT for CMU_HFCORECLKDIV

Definition at line 241 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)

Shifted mode DIV2 for CMU_HFCORECLKDIV

Definition at line 242 of file efm32zg_cmu.h.

#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)

Shifted mode DIV4 for CMU_HFCORECLKDIV

Definition at line 243 of file efm32zg_cmu.h.

#define CMU_HFCORECLKEN0_AES (0x1UL << 0)

Advanced Encryption Standard Accelerator Clock Enable

Definition at line 745 of file efm32zg_cmu.h.

#define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 749 of file efm32zg_cmu.h.

#define CMU_HFCORECLKEN0_DMA (0x1UL << 1)

Direct Memory Access Controller Clock Enable

Definition at line 750 of file efm32zg_cmu.h.

#define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)

Shifted mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 754 of file efm32zg_cmu.h.

#define CMU_HFCORECLKEN0_LE (0x1UL << 2)

Low Energy Peripheral Interface Clock Enable

Definition at line 755 of file efm32zg_cmu.h.

Referenced by UDELAY_Calibrate().

#define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)

Shifted mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 759 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFPERCLKDIV

Definition at line 261 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)

Shifted mode HFCLK for CMU_HFPERCLKDIV

Definition at line 262 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)

Shifted mode HFCLK128 for CMU_HFPERCLKDIV

Definition at line 269 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)

Shifted mode HFCLK16 for CMU_HFPERCLKDIV

Definition at line 266 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)

Shifted mode HFCLK2 for CMU_HFPERCLKDIV

Definition at line 263 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)

Shifted mode HFCLK256 for CMU_HFPERCLKDIV

Definition at line 270 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)

Shifted mode HFCLK32 for CMU_HFPERCLKDIV

Definition at line 267 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)

Shifted mode HFCLK4 for CMU_HFPERCLKDIV

Definition at line 264 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)

Shifted mode HFCLK512 for CMU_HFPERCLKDIV

Definition at line 271 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)

Shifted mode HFCLK64 for CMU_HFPERCLKDIV

Definition at line 268 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)

Shifted mode HFCLK8 for CMU_HFPERCLKDIV

Definition at line 265 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)

HFPERCLK Enable

Definition at line 272 of file efm32zg_cmu.h.

#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)

Shifted mode DEFAULT for CMU_HFPERCLKDIV

Definition at line 276 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 2)

Analog Comparator 0 Clock Enable

Definition at line 774 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 2)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 778 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_ADC0 (0x1UL << 10)

Analog to Digital Converter 0 Clock Enable

Definition at line 804 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 808 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_GPIO (0x1UL << 7)

General purpose Input/Output Clock Enable

Definition at line 794 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 7)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 798 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11)

I2C 0 Clock Enable

Definition at line 809 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 813 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 6)

Current Digital to Analog Converter 0 Clock Enable

Definition at line 789 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 6)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 793 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_PRS (0x1UL << 4)

Peripheral Reflex System Clock Enable

Definition at line 784 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 4)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 788 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0)

Timer 0 Clock Enable

Definition at line 764 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 768 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1)

Timer 1 Clock Enable

Definition at line 769 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 773 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_USART1 (0x1UL << 3)

Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable

Definition at line 779 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 783 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_VCMP (0x1UL << 8)

Voltage Comparator Clock Enable

Definition at line 799 of file efm32zg_cmu.h.

#define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 8)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 803 of file efm32zg_cmu.h.

#define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)

Shifted mode 11MHZ for CMU_HFRCOCTRL

Definition at line 295 of file efm32zg_cmu.h.

Referenced by SystemHFClockGet().

#define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)

Shifted mode 14MHZ for CMU_HFRCOCTRL

Definition at line 297 of file efm32zg_cmu.h.

Referenced by SystemHFClockGet().

#define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)

Shifted mode 1MHZ for CMU_HFRCOCTRL

Definition at line 293 of file efm32zg_cmu.h.

Referenced by SystemHFClockGet().

#define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)

Shifted mode 21MHZ for CMU_HFRCOCTRL

Definition at line 298 of file efm32zg_cmu.h.

Referenced by SystemHFClockGet().

#define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)

Shifted mode 7MHZ for CMU_HFRCOCTRL

Definition at line 294 of file efm32zg_cmu.h.

Referenced by SystemHFClockGet().

#define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)

Shifted mode DEFAULT for CMU_HFRCOCTRL

Definition at line 296 of file efm32zg_cmu.h.

#define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)

Shifted mode DEFAULT for CMU_HFRCOCTRL

Definition at line 302 of file efm32zg_cmu.h.

#define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFRCOCTRL

Definition at line 284 of file efm32zg_cmu.h.

#define CMU_IEN_AUXHFRCORDY (0x1UL << 4)

AUXHFRCO Ready Interrupt Enable

Definition at line 726 of file efm32zg_cmu.h.

#define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)

Shifted mode DEFAULT for CMU_IEN

Definition at line 730 of file efm32zg_cmu.h.

#define CMU_IEN_CALOF (0x1UL << 6)

Calibration Overflow Interrupt Enable

Definition at line 736 of file efm32zg_cmu.h.

#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)

Shifted mode DEFAULT for CMU_IEN

Definition at line 740 of file efm32zg_cmu.h.

#define CMU_IEN_CALRDY (0x1UL << 5)

Calibration Ready Interrupt Enable

Definition at line 731 of file efm32zg_cmu.h.

#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_IEN

Definition at line 735 of file efm32zg_cmu.h.

#define CMU_IEN_HFRCORDY (0x1UL << 0)

HFRCO Ready Interrupt Enable

Definition at line 706 of file efm32zg_cmu.h.

#define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_IEN

Definition at line 710 of file efm32zg_cmu.h.

#define CMU_IEN_HFXORDY (0x1UL << 1)

HFXO Ready Interrupt Enable

Definition at line 711 of file efm32zg_cmu.h.

#define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_IEN

Definition at line 715 of file efm32zg_cmu.h.

#define CMU_IEN_LFRCORDY (0x1UL << 2)

LFRCO Ready Interrupt Enable

Definition at line 716 of file efm32zg_cmu.h.

#define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)

Shifted mode DEFAULT for CMU_IEN

Definition at line 720 of file efm32zg_cmu.h.

#define CMU_IEN_LFXORDY (0x1UL << 3)

LFXO Ready Interrupt Enable

Definition at line 721 of file efm32zg_cmu.h.

#define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_IEN

Definition at line 725 of file efm32zg_cmu.h.

#define CMU_IF_AUXHFRCORDY (0x1UL << 4)

AUXHFRCO Ready Interrupt Flag

Definition at line 609 of file efm32zg_cmu.h.

#define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)

Shifted mode DEFAULT for CMU_IF

Definition at line 613 of file efm32zg_cmu.h.

#define CMU_IF_CALOF (0x1UL << 6)

Calibration Overflow Interrupt Flag

Definition at line 619 of file efm32zg_cmu.h.

#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)

Shifted mode DEFAULT for CMU_IF

Definition at line 623 of file efm32zg_cmu.h.

#define CMU_IF_CALRDY (0x1UL << 5)

Calibration Ready Interrupt Flag

Definition at line 614 of file efm32zg_cmu.h.

#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_IF

Definition at line 618 of file efm32zg_cmu.h.

#define CMU_IF_HFRCORDY (0x1UL << 0)

HFRCO Ready Interrupt Flag

Definition at line 589 of file efm32zg_cmu.h.

#define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_IF

Definition at line 593 of file efm32zg_cmu.h.

#define CMU_IF_HFXORDY (0x1UL << 1)

HFXO Ready Interrupt Flag

Definition at line 594 of file efm32zg_cmu.h.

#define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_IF

Definition at line 598 of file efm32zg_cmu.h.

#define CMU_IF_LFRCORDY (0x1UL << 2)

LFRCO Ready Interrupt Flag

Definition at line 599 of file efm32zg_cmu.h.

#define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)

Shifted mode DEFAULT for CMU_IF

Definition at line 603 of file efm32zg_cmu.h.

#define CMU_IF_LFXORDY (0x1UL << 3)

LFXO Ready Interrupt Flag

Definition at line 604 of file efm32zg_cmu.h.

#define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_IF

Definition at line 608 of file efm32zg_cmu.h.

#define CMU_IFC_AUXHFRCORDY (0x1UL << 4)

AUXHFRCO Ready Interrupt Flag Clear

Definition at line 687 of file efm32zg_cmu.h.

#define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)

Shifted mode DEFAULT for CMU_IFC

Definition at line 691 of file efm32zg_cmu.h.

#define CMU_IFC_CALOF (0x1UL << 6)

Calibration Overflow Interrupt Flag Clear

Definition at line 697 of file efm32zg_cmu.h.

#define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)

Shifted mode DEFAULT for CMU_IFC

Definition at line 701 of file efm32zg_cmu.h.

#define CMU_IFC_CALRDY (0x1UL << 5)

Calibration Ready Interrupt Flag Clear

Definition at line 692 of file efm32zg_cmu.h.

#define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_IFC

Definition at line 696 of file efm32zg_cmu.h.

#define CMU_IFC_HFRCORDY (0x1UL << 0)

HFRCO Ready Interrupt Flag Clear

Definition at line 667 of file efm32zg_cmu.h.

#define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_IFC

Definition at line 671 of file efm32zg_cmu.h.

#define CMU_IFC_HFXORDY (0x1UL << 1)

HFXO Ready Interrupt Flag Clear

Definition at line 672 of file efm32zg_cmu.h.

#define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_IFC

Definition at line 676 of file efm32zg_cmu.h.

#define CMU_IFC_LFRCORDY (0x1UL << 2)

LFRCO Ready Interrupt Flag Clear

Definition at line 677 of file efm32zg_cmu.h.

#define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)

Shifted mode DEFAULT for CMU_IFC

Definition at line 681 of file efm32zg_cmu.h.

#define CMU_IFC_LFXORDY (0x1UL << 3)

LFXO Ready Interrupt Flag Clear

Definition at line 682 of file efm32zg_cmu.h.

#define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_IFC

Definition at line 686 of file efm32zg_cmu.h.

#define CMU_IFS_AUXHFRCORDY (0x1UL << 4)

AUXHFRCO Ready Interrupt Flag Set

Definition at line 648 of file efm32zg_cmu.h.

#define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)

Shifted mode DEFAULT for CMU_IFS

Definition at line 652 of file efm32zg_cmu.h.

#define CMU_IFS_CALOF (0x1UL << 6)

Calibration Overflow Interrupt Flag Set

Definition at line 658 of file efm32zg_cmu.h.

#define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)

Shifted mode DEFAULT for CMU_IFS

Definition at line 662 of file efm32zg_cmu.h.

#define CMU_IFS_CALRDY (0x1UL << 5)

Calibration Ready Interrupt Flag Set

Definition at line 653 of file efm32zg_cmu.h.

#define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_IFS

Definition at line 657 of file efm32zg_cmu.h.

#define CMU_IFS_HFRCORDY (0x1UL << 0)

HFRCO Ready Interrupt Flag Set

Definition at line 628 of file efm32zg_cmu.h.

#define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_IFS

Definition at line 632 of file efm32zg_cmu.h.

#define CMU_IFS_HFXORDY (0x1UL << 1)

HFXO Ready Interrupt Flag Set

Definition at line 633 of file efm32zg_cmu.h.

#define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_IFS

Definition at line 637 of file efm32zg_cmu.h.

#define CMU_IFS_LFRCORDY (0x1UL << 2)

LFRCO Ready Interrupt Flag Set

Definition at line 638 of file efm32zg_cmu.h.

#define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)

Shifted mode DEFAULT for CMU_IFS

Definition at line 642 of file efm32zg_cmu.h.

#define CMU_IFS_LFXORDY (0x1UL << 3)

LFXO Ready Interrupt Flag Set

Definition at line 643 of file efm32zg_cmu.h.

#define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_IFS

Definition at line 647 of file efm32zg_cmu.h.

#define CMU_LFACLKEN0_RTC (0x1UL << 0)

Real-Time Counter Clock Enable

Definition at line 855 of file efm32zg_cmu.h.

Referenced by UDELAY_Calibrate().

#define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LFACLKEN0

Definition at line 859 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0)

Shifted mode DIV1 for CMU_LFAPRESC0

Definition at line 891 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0)

Shifted mode DIV1024 for CMU_LFAPRESC0

Definition at line 901 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0)

Shifted mode DIV128 for CMU_LFAPRESC0

Definition at line 898 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0)

Shifted mode DIV16 for CMU_LFAPRESC0

Definition at line 895 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)

Shifted mode DIV16384 for CMU_LFAPRESC0

Definition at line 905 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0)

Shifted mode DIV2 for CMU_LFAPRESC0

Definition at line 892 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0)

Shifted mode DIV2048 for CMU_LFAPRESC0

Definition at line 902 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0)

Shifted mode DIV256 for CMU_LFAPRESC0

Definition at line 899 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0)

Shifted mode DIV32 for CMU_LFAPRESC0

Definition at line 896 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)

Shifted mode DIV32768 for CMU_LFAPRESC0

Definition at line 906 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0)

Shifted mode DIV4 for CMU_LFAPRESC0

Definition at line 893 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0)

Shifted mode DIV4096 for CMU_LFAPRESC0

Definition at line 903 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0)

Shifted mode DIV512 for CMU_LFAPRESC0

Definition at line 900 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0)

Shifted mode DIV64 for CMU_LFAPRESC0

Definition at line 897 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0)

Shifted mode DIV8 for CMU_LFAPRESC0

Definition at line 894 of file efm32zg_cmu.h.

#define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0)

Shifted mode DIV8192 for CMU_LFAPRESC0

Definition at line 904 of file efm32zg_cmu.h.

#define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)

Low Energy UART 0 Clock Enable

Definition at line 864 of file efm32zg_cmu.h.

#define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LFBCLKEN0

Definition at line 868 of file efm32zg_cmu.h.

#define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)

Shifted mode DIV1 for CMU_LFBPRESC0

Definition at line 917 of file efm32zg_cmu.h.

#define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)

Shifted mode DIV2 for CMU_LFBPRESC0

Definition at line 918 of file efm32zg_cmu.h.

#define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)

Shifted mode DIV4 for CMU_LFBPRESC0

Definition at line 919 of file efm32zg_cmu.h.

#define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)

Shifted mode DIV8 for CMU_LFBPRESC0

Definition at line 920 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LFCLKSEL

Definition at line 472 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)

Shifted mode DISABLED for CMU_LFCLKSEL

Definition at line 471 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)

Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL

Definition at line 475 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet().

#define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)

Shifted mode LFRCO for CMU_LFCLKSEL

Definition at line 473 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet().

#define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)

Shifted mode LFXO for CMU_LFCLKSEL

Definition at line 474 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet().

#define CMU_LFCLKSEL_LFAE (0x1UL << 16)

Clock Select for LFA Extended

Definition at line 488 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)

Shifted mode DEFAULT for CMU_LFCLKSEL

Definition at line 494 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16)

Shifted mode DISABLED for CMU_LFCLKSEL

Definition at line 495 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)

Shifted mode ULFRCO for CMU_LFCLKSEL

Definition at line 496 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)

Shifted mode DEFAULT for CMU_LFCLKSEL

Definition at line 484 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)

Shifted mode DISABLED for CMU_LFCLKSEL

Definition at line 483 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)

Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL

Definition at line 487 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet().

#define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)

Shifted mode LFRCO for CMU_LFCLKSEL

Definition at line 485 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet().

#define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)

Shifted mode LFXO for CMU_LFCLKSEL

Definition at line 486 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet().

#define CMU_LFCLKSEL_LFBE (0x1UL << 20)

Clock Select for LFB Extended

Definition at line 497 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)

Shifted mode DEFAULT for CMU_LFCLKSEL

Definition at line 503 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20)

Shifted mode DISABLED for CMU_LFCLKSEL

Definition at line 504 of file efm32zg_cmu.h.

#define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)

Shifted mode ULFRCO for CMU_LFCLKSEL

Definition at line 505 of file efm32zg_cmu.h.

#define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LFRCOCTRL

Definition at line 310 of file efm32zg_cmu.h.

#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LOCK

Definition at line 974 of file efm32zg_cmu.h.

#define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)

Shifted mode LOCK for CMU_LOCK

Definition at line 975 of file efm32zg_cmu.h.

Referenced by CMU_Lock().

#define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)

Shifted mode LOCKED for CMU_LOCK

Definition at line 977 of file efm32zg_cmu.h.

Referenced by EMU_EnterEM3().

#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)

Shifted mode UNLOCK for CMU_LOCK

Definition at line 978 of file efm32zg_cmu.h.

Referenced by CMU_Unlock().

#define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)

Shifted mode UNLOCKED for CMU_LOCK

Definition at line 976 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)

AUXHFRCO Disable

Definition at line 409 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 413 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)

AUXHFRCO Enable

Definition at line 404 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 408 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)

HFRCO Disable

Definition at line 389 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 393 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)

HFRCO Enable

Definition at line 384 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 388 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_HFXODIS (0x1UL << 3)

HFXO Disable

Definition at line 399 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 403 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_HFXOEN (0x1UL << 2)

HFXO Enable

Definition at line 394 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 398 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)

LFRCO Disable

Definition at line 419 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable(), and EMU_EnterEM3().

#define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 423 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)

LFRCO Enable

Definition at line 414 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 418 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_LFXODIS (0x1UL << 9)

LFXO Disable

Definition at line 429 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable(), and EMU_EnterEM3().

#define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 433 of file efm32zg_cmu.h.

#define CMU_OSCENCMD_LFXOEN (0x1UL << 8)

LFXO Enable

Definition at line 424 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorEnable().

#define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 428 of file efm32zg_cmu.h.

#define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)

PCNT0 Clock Enable

Definition at line 925 of file efm32zg_cmu.h.

#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)

Shifted mode DEFAULT for CMU_PCNTCTRL

Definition at line 929 of file efm32zg_cmu.h.

#define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)

PCNT0 Clock Select

Definition at line 930 of file efm32zg_cmu.h.

#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)

Shifted mode DEFAULT for CMU_PCNTCTRL

Definition at line 936 of file efm32zg_cmu.h.

#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)

Shifted mode LFACLK for CMU_PCNTCTRL

Definition at line 937 of file efm32zg_cmu.h.

#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)

Shifted mode PCNT0S0 for CMU_PCNTCTRL

Definition at line 938 of file efm32zg_cmu.h.

Referenced by CMU_PCNTClockExternalGet().

#define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)

CLKOUT0 Pin Enable

Definition at line 943 of file efm32zg_cmu.h.

#define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)

Shifted mode DEFAULT for CMU_ROUTE

Definition at line 947 of file efm32zg_cmu.h.

#define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)

CLKOUT1 Pin Enable

Definition at line 948 of file efm32zg_cmu.h.

#define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)

Shifted mode DEFAULT for CMU_ROUTE

Definition at line 952 of file efm32zg_cmu.h.

#define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)

Shifted mode DEFAULT for CMU_ROUTE

Definition at line 960 of file efm32zg_cmu.h.

#define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)

Shifted mode LOC0 for CMU_ROUTE

Definition at line 959 of file efm32zg_cmu.h.

#define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)

Shifted mode LOC1 for CMU_ROUTE

Definition at line 961 of file efm32zg_cmu.h.

#define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2)

Shifted mode LOC2 for CMU_ROUTE

Definition at line 962 of file efm32zg_cmu.h.

#define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)

AUXHFRCO Enable Status

Definition at line 530 of file efm32zg_cmu.h.

#define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 534 of file efm32zg_cmu.h.

#define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)

AUXHFRCO Ready

Definition at line 535 of file efm32zg_cmu.h.

#define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 539 of file efm32zg_cmu.h.

#define CMU_STATUS_CALBSY (0x1UL << 14)

Calibration Busy

Definition at line 580 of file efm32zg_cmu.h.

#define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 584 of file efm32zg_cmu.h.

#define CMU_STATUS_HFRCOENS (0x1UL << 0)

HFRCO Enable Status

Definition at line 510 of file efm32zg_cmu.h.

#define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 514 of file efm32zg_cmu.h.

#define CMU_STATUS_HFRCORDY (0x1UL << 1)

HFRCO Ready

Definition at line 515 of file efm32zg_cmu.h.

#define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 519 of file efm32zg_cmu.h.

#define CMU_STATUS_HFRCOSEL (0x1UL << 10)

HFRCO Selected

Definition at line 560 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet(), and SystemHFClockGet().

#define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 564 of file efm32zg_cmu.h.

#define CMU_STATUS_HFXOENS (0x1UL << 2)

HFXO Enable Status

Definition at line 520 of file efm32zg_cmu.h.

Referenced by CMU_OscillatorTuningSet().

#define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 524 of file efm32zg_cmu.h.

#define CMU_STATUS_HFXORDY (0x1UL << 3)

HFXO Ready

Definition at line 525 of file efm32zg_cmu.h.

#define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 529 of file efm32zg_cmu.h.

#define CMU_STATUS_HFXOSEL (0x1UL << 11)

HFXO Selected

Definition at line 565 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet(), SystemHFClockGet(), and SystemHFXOClockSet().

#define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 569 of file efm32zg_cmu.h.

#define CMU_STATUS_LFRCOENS (0x1UL << 6)

LFRCO Enable Status

Definition at line 540 of file efm32zg_cmu.h.

Referenced by UDELAY_Calibrate().

#define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 544 of file efm32zg_cmu.h.

#define CMU_STATUS_LFRCORDY (0x1UL << 7)

LFRCO Ready

Definition at line 545 of file efm32zg_cmu.h.

#define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 549 of file efm32zg_cmu.h.

#define CMU_STATUS_LFRCOSEL (0x1UL << 12)

LFRCO Selected

Definition at line 570 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet(), and SystemHFClockGet().

#define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 574 of file efm32zg_cmu.h.

#define CMU_STATUS_LFXOENS (0x1UL << 8)

LFXO Enable Status

Definition at line 550 of file efm32zg_cmu.h.

Referenced by UARTDRV_InitLeuart(), and UDELAY_Calibrate().

#define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 554 of file efm32zg_cmu.h.

#define CMU_STATUS_LFXORDY (0x1UL << 9)

LFXO Ready

Definition at line 555 of file efm32zg_cmu.h.

#define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 559 of file efm32zg_cmu.h.

#define CMU_STATUS_LFXOSEL (0x1UL << 13)

LFXO Selected

Definition at line 575 of file efm32zg_cmu.h.

Referenced by CMU_ClockSelectGet(), SystemHFClockGet(), and SystemLFXOClockSet().

#define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 579 of file efm32zg_cmu.h.

#define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)

Low Frequency A Clock Enable 0 Busy

Definition at line 818 of file efm32zg_cmu.h.

Referenced by CMU_ClockEnable().

#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)

Shifted mode DEFAULT for CMU_SYNCBUSY

Definition at line 822 of file efm32zg_cmu.h.

#define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)

Low Frequency A Prescaler 0 Busy

Definition at line 823 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivSet().

#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)

Shifted mode DEFAULT for CMU_SYNCBUSY

Definition at line 827 of file efm32zg_cmu.h.

#define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)

Low Frequency B Clock Enable 0 Busy

Definition at line 828 of file efm32zg_cmu.h.

Referenced by CMU_ClockEnable().

#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)

Shifted mode DEFAULT for CMU_SYNCBUSY

Definition at line 832 of file efm32zg_cmu.h.

#define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)

Low Frequency B Prescaler 0 Busy

Definition at line 833 of file efm32zg_cmu.h.

Referenced by CMU_ClockDivSet().

#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)

Shifted mode DEFAULT for CMU_SYNCBUSY

Definition at line 837 of file efm32zg_cmu.h.

Detailed Description

Macros

Macro Definition Documentation