34 #if defined(IDAC_COUNT) && (IDAC_COUNT > 0)
51 #if defined(_SILICON_LABS_32B_SERIES_0) \
52 && (defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY))
53 #define ERRATA_FIX_IDAC_E101_EN
83 EFM_ASSERT(IDAC_REF_VALID(idac));
85 tmp = (uint32_t)(init->
prsSel);
95 #if defined(_IDAC_CTRL_OUTENPRS_MASK)
98 tmp |= IDAC_CTRL_APORTOUTENPRS;
122 EFM_ASSERT(IDAC_REF_VALID(idac));
136 EFM_ASSERT(IDAC_REF_VALID(idac));
138 #if defined(ERRATA_FIX_IDAC_E101_EN)
157 #if defined ( _IDAC_CAL_MASK )
175 EFM_ASSERT(IDAC_REF_VALID(idac));
199 #if defined( _IDAC_CURPROG_TUNING_MASK )
204 EFM_ASSERT(IDAC_REF_VALID(idac));
208 #if defined ( _IDAC_CAL_MASK )
232 tmp |= (uint32_t)range;
234 #elif defined( _IDAC_CURPROG_TUNING_MASK )
238 EFM_ASSERT(idac ==
IDAC0);
242 tmp = idac->
CURPROG & ~(_IDAC_CURPROG_TUNING_MASK
249 tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK)
250 >> _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT)
251 << _IDAC_CURPROG_TUNING_SHIFT;
255 tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK)
256 >> _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT)
257 << _IDAC_CURPROG_TUNING_SHIFT;
261 tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK)
262 >> _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT)
263 << _IDAC_CURPROG_TUNING_SHIFT;
267 tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK)
268 >> _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT)
269 << _IDAC_CURPROG_TUNING_SHIFT;
278 tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK)
279 >> _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT)
280 << _IDAC_CURPROG_TUNING_SHIFT;
284 tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK)
285 >> _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT)
286 << _IDAC_CURPROG_TUNING_SHIFT;
290 tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK)
291 >> _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT)
292 << _IDAC_CURPROG_TUNING_SHIFT;
296 tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK)
297 >> _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT)
298 << _IDAC_CURPROG_TUNING_SHIFT;
303 tmp |= (uint32_t)range;
306 #warning "IDAC calibration register definition unknown."
327 EFM_ASSERT(IDAC_REF_VALID(idac));
349 EFM_ASSERT(IDAC_REF_VALID(idac));
350 #if defined(_IDAC_CTRL_OUTEN_MASK)
#define _DEVINFO_IDAC0CAL0_RANGE2_SHIFT
Clock management unit (CMU) API.
#define _DEVINFO_IDAC0CAL0_RANGE0_SHIFT
#define IDAC_CTRL_CURSINK
#define IDAC_CURPROG_RANGESEL_RANGE0
IDAC_PRSSEL_TypeDef prsSel
Emlib peripheral API "assert" implementation.
#define _IDAC_CURPROG_RANGESEL_MASK
#define _IDAC_CURPROG_STEPSEL_MASK
RAM and peripheral bit-field set and clear API.
#define _DEVINFO_IDAC0CAL0_RANGE2_MASK
Current Digital to Analog Converter (IDAC) peripheral API.
#define IDAC_CTRL_OUTENPRS
#define _DEVINFO_IDAC0CAL0_RANGE0_MASK
#define _DEVINFO_IDAC0CAL0_RANGE1_SHIFT
void IDAC_Enable(IDAC_TypeDef *idac, bool enable)
Enable/disable IDAC.
#define _IDAC_CURPROG_RANGESEL_SHIFT
__IOM uint32_t DUTYCONFIG
void IDAC_MinimalOutputTransitionMode(IDAC_TypeDef *idac, bool enable)
Enable/disable Minimal Output Transition mode.
#define _IDAC_CTRL_MINOUTTRANS_SHIFT
#define _IDAC_DUTYCONFIG_RESETVALUE
#define _DEVINFO_IDAC0CAL0_RANGE3_SHIFT
void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
Set the current range of the IDAC output.
#define _IDAC_CAL_RESETVALUE
#define _IDAC_CTRL_OUTEN_SHIFT
void IDAC_Init(IDAC_TypeDef *idac, const IDAC_Init_TypeDef *init)
Initialize IDAC.
#define _DEVINFO_IDAC0CAL0_RANGE1_MASK
#define _IDAC_CURPROG_STEPSEL_SHIFT
IDAC_OutMode_TypeDef outMode
void IDAC_StepSet(IDAC_TypeDef *idac, const uint32_t step)
Set the current step of the IDAC output.
#define _IDAC_CTRL_EN_SHIFT
#define _IDAC_CTRL_RESETVALUE
#define IDAC_DUTYCONFIG_DUTYCYCLEEN
void IDAC_Reset(IDAC_TypeDef *idac)
Reset IDAC to same state as after a HW reset.
#define _IDAC_CURPROG_RESETVALUE
#define _DEVINFO_IDAC0CAL0_RANGE3_MASK
void IDAC_OutEnable(IDAC_TypeDef *idac, bool enable)
Enable/disable the IDAC OUT pin.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.