EFM32 Zero Gecko Software Documentation  efm32zg-doc-5.1.2
em_i2c.c
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1 /***************************************************************************/
33 #include "em_i2c.h"
34 #if defined(I2C_COUNT) && (I2C_COUNT > 0)
35 
36 #include "em_cmu.h"
37 #include "em_bus.h"
38 #include "em_assert.h"
39 
40  #include <limits.h>
41 
42 /***************************************************************************/
47 /***************************************************************************/
57 /*******************************************************************************
58  ******************************* DEFINES ***********************************
59  ******************************************************************************/
60 
64 #if (I2C_COUNT == 1)
65 #define I2C_REF_VALID(ref) ((ref) == I2C0)
66 #elif (I2C_COUNT == 2)
67 #define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1))
68 #elif (I2C_COUNT == 3)
69 #define I2C_REF_VALID(ref) ((ref == I2C0) || (ref == I2C1)|| (ref == I2C2))
70 #endif
71 
73 /* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */
74 /* this SW supporting master mode. Likewise for I2C_IF_RXUF (receive underflow) */
75 /* RXUF is only likely to occur with this SW if using a debugger peeking into */
76 /* RXDATA register. Thus, we ignore those types of fault. */
77 #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
78 
79 /* Max I2C transmission rate constant */
80 #if defined( _SILICON_LABS_32B_SERIES_0 )
81 #define I2C_CR_MAX 4
82 #elif defined( _SILICON_LABS_32B_SERIES_1 )
83 #define I2C_CR_MAX 8
84 #else
85 #warning "Max I2C transmission rate constant is not defined"
86 #endif
87 
90 /*******************************************************************************
91  ******************************** ENUMS ************************************
92  ******************************************************************************/
93 
97 typedef enum
98 {
99  i2cStateStartAddrSend,
100  i2cStateAddrWFAckNack,
101  i2cStateAddrWF2ndAckNack,
102  i2cStateRStartAddrSend,
103  i2cStateRAddrWFAckNack,
104  i2cStateDataSend,
105  i2cStateDataWFAckNack,
106  i2cStateWFData,
107  i2cStateWFStopSent,
108  i2cStateDone
109 } I2C_TransferState_TypeDef;
110 
113 /*******************************************************************************
114  ******************************* STRUCTS ***********************************
115  ******************************************************************************/
116 
120 typedef struct
121 {
123  I2C_TransferState_TypeDef state;
124 
127 
129  uint16_t offset;
130 
131  /* Index to current sequence buffer in use. */
132  uint8_t bufIndx;
133 
136 } I2C_Transfer_TypeDef;
137 
140 /*******************************************************************************
141  ***************************** LOCAL DATA *******^**************************
142  ******************************************************************************/
143 
150 static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 };
151 
153 static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT];
154 
157 /*******************************************************************************
158  ************************** GLOBAL FUNCTIONS *******************************
159  ******************************************************************************/
160 
161 /***************************************************************************/
175 {
176  uint32_t freqHfper;
177  uint32_t n;
178 
179  /* Max frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX)
180  * More details can be found in the reference manual,
181  * I2C Clock Generation chapter. */
182  freqHfper = CMU_ClockFreqGet(cmuClock_HFPER);
183  /* n = Nlow + Nhigh */
184  n = (uint32_t)(i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) >> _I2C_CTRL_CLHR_SHIFT]);
185 
186  return (freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX));
187 }
188 
189 
190 /***************************************************************************/
228  uint32_t freqRef,
229  uint32_t freqScl,
230  I2C_ClockHLR_TypeDef i2cMode)
231 {
232  uint32_t n, minFreq;
233  int32_t div;
234 
235  /* Avoid divide by 0 */
236  EFM_ASSERT(freqScl);
237  if (!freqScl)
238  {
239  return;
240  }
241 
242  /* Set the CLHR (clock low to high ratio). */
243  i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK;
244  BUS_RegMaskedWrite(&i2c->CTRL,
246  i2cMode <<_I2C_CTRL_CLHR_SHIFT);
247 
248  if (!freqRef)
249  {
250  freqRef = CMU_ClockFreqGet(cmuClock_HFPER);
251  }
252 
253  /* Check minumum HF peripheral clock */
254  minFreq = UINT_MAX;
255  if (i2c->CTRL & I2C_CTRL_SLAVE)
256  {
257  switch(i2cMode)
258  {
259  case i2cClockHLRStandard:
260 #if defined( _SILICON_LABS_32B_SERIES_0 )
261  minFreq = 4200000; break;
262 #elif defined( _SILICON_LABS_32B_SERIES_1 )
263  minFreq = 2000000; break;
264 #endif
266 #if defined( _SILICON_LABS_32B_SERIES_0 )
267  minFreq = 11000000; break;
268 #elif defined( _SILICON_LABS_32B_SERIES_1 )
269  minFreq = 5000000; break;
270 #endif
271  case i2cClockHLRFast:
272 #if defined( _SILICON_LABS_32B_SERIES_0 )
273  minFreq = 24400000; break;
274 #elif defined( _SILICON_LABS_32B_SERIES_1 )
275  minFreq = 14000000; break;
276 #endif
277  }
278  }
279  else
280  {
281  /* For master mode, platform 1 and 2 share the same
282  min frequencies */
283  switch(i2cMode)
284  {
285  case i2cClockHLRStandard:
286  minFreq = 2000000; break;
288  minFreq = 9000000; break;
289  case i2cClockHLRFast:
290  minFreq = 20000000; break;
291  }
292  }
293 
294  /* Frequency most be larger-than */
295  EFM_ASSERT(freqRef > minFreq);
296 
297  /* SCL frequency is given by
298  * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_CR_MAX)
299  *
300  * Thus
301  * DIV = ((freqRef - (I2C_CR_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1
302  *
303  * More details can be found in the reference manual,
304  * I2C Clock Generation chapter. */
305 
306  /* n = Nlow + Nhigh */
307  n = (uint32_t)(i2cNSum[i2cMode]);
308  div = ((freqRef - (I2C_CR_MAX * freqScl)) / (n * freqScl)) - 1;
309  EFM_ASSERT(div >= 0);
310  EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK);
311 
312  /* Clock divisor must be at least 1 in slave mode according to reference */
313  /* manual (in which case there is normally no need to set bus frequency). */
314  if ((i2c->CTRL & I2C_CTRL_SLAVE) && !div)
315  {
316  div = 1;
317  }
318  i2c->CLKDIV = (uint32_t)div;
319 }
320 
321 
322 /***************************************************************************/
335 void I2C_Enable(I2C_TypeDef *i2c, bool enable)
336 {
337  EFM_ASSERT(I2C_REF_VALID(i2c));
338 
339  BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable);
340 }
341 
342 
343 /***************************************************************************/
353 void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init)
354 {
355  EFM_ASSERT(I2C_REF_VALID(i2c));
356 
357  i2c->IEN = 0;
358  i2c->IFC = _I2C_IFC_MASK;
359 
360  /* Set SLAVE select mode */
361  BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1);
362 
363  I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr);
364 
366 }
367 
368 
369 /***************************************************************************/
381 {
382  i2c->CTRL = _I2C_CTRL_RESETVALUE;
386  i2c->IEN = _I2C_IEN_RESETVALUE;
387  i2c->IFC = _I2C_IFC_MASK;
388  /* Do not reset route register, setting should be done independently */
389 }
390 
391 
392 /***************************************************************************/
429 {
430  uint32_t tmp;
431  uint32_t pending;
432  I2C_Transfer_TypeDef *transfer;
434 
435  EFM_ASSERT(I2C_REF_VALID(i2c));
436 
437  /* Support up to 2 I2C buses */
438  if (i2c == I2C0)
439  {
440  transfer = i2cTransfer;
441  }
442 #if (I2C_COUNT > 1)
443  else if (i2c == I2C1)
444  {
445  transfer = i2cTransfer + 1;
446  }
447 #endif
448  else
449  {
450  return i2cTransferUsageFault;
451  }
452 
453  seq = transfer->seq;
454  for (;; )
455  {
456  pending = i2c->IF;
457 
458  /* If some sort of fault, abort transfer. */
459  if (pending & I2C_IF_ERRORS)
460  {
461  if (pending & I2C_IF_ARBLOST)
462  {
463  /* If arbitration fault, it indicates either a slave device */
464  /* not responding as expected, or other master which is not */
465  /* supported by this SW. */
466  transfer->result = i2cTransferArbLost;
467  }
468  else if (pending & I2C_IF_BUSERR)
469  {
470  /* A bus error indicates a misplaced start or stop, which should */
471  /* not occur in master mode controlled by this SW. */
472  transfer->result = i2cTransferBusErr;
473  }
474 
475  /* If error situation occurred, it is difficult to know */
476  /* exact cause and how to resolve. It will be up to a wrapper */
477  /* to determine how to handle a fault/recovery if possible. */
478  transfer->state = i2cStateDone;
479  goto done;
480  }
481 
482  switch (transfer->state)
483  {
484  /***************************************************/
485  /* Send first start+address (first byte if 10 bit) */
486  /***************************************************/
487  case i2cStateStartAddrSend:
488  if (seq->flags & I2C_FLAG_10BIT_ADDR)
489  {
490  tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0;
491 
492  /* In 10 bit address mode, the address following the first */
493  /* start always indicate write. */
494  }
495  else
496  {
497  tmp = (uint32_t)(seq->addr) & 0xfe;
498 
499  if (seq->flags & I2C_FLAG_READ)
500  {
501  /* Indicate read request */
502  tmp |= 1;
503  }
504  }
505 
506  transfer->state = i2cStateAddrWFAckNack;
507  i2c->TXDATA = tmp; /* Data not transmitted until START sent */
508  i2c->CMD = I2C_CMD_START;
509  goto done;
510 
511  /*******************************************************/
512  /* Wait for ACK/NACK on address (first byte if 10 bit) */
513  /*******************************************************/
514  case i2cStateAddrWFAckNack:
515  if (pending & I2C_IF_NACK)
516  {
517  i2c->IFC = I2C_IFC_NACK;
518  transfer->result = i2cTransferNack;
519  transfer->state = i2cStateWFStopSent;
520  i2c->CMD = I2C_CMD_STOP;
521  }
522  else if (pending & I2C_IF_ACK)
523  {
524  i2c->IFC = I2C_IFC_ACK;
525 
526  /* If 10 bit address, send 2nd byte of address. */
527  if (seq->flags & I2C_FLAG_10BIT_ADDR)
528  {
529  transfer->state = i2cStateAddrWF2ndAckNack;
530  i2c->TXDATA = (uint32_t)(seq->addr) & 0xff;
531  }
532  else
533  {
534  /* Determine whether receiving or sending data */
535  if (seq->flags & I2C_FLAG_READ)
536  {
537  transfer->state = i2cStateWFData;
538  if(seq->buf[transfer->bufIndx].len==1)
539  {
540  i2c->CMD = I2C_CMD_NACK;
541  }
542  }
543  else
544  {
545  transfer->state = i2cStateDataSend;
546  continue;
547  }
548  }
549  }
550  goto done;
551 
552  /******************************************************/
553  /* Wait for ACK/NACK on second byte of 10 bit address */
554  /******************************************************/
555  case i2cStateAddrWF2ndAckNack:
556  if (pending & I2C_IF_NACK)
557  {
558  i2c->IFC = I2C_IFC_NACK;
559  transfer->result = i2cTransferNack;
560  transfer->state = i2cStateWFStopSent;
561  i2c->CMD = I2C_CMD_STOP;
562  }
563  else if (pending & I2C_IF_ACK)
564  {
565  i2c->IFC = I2C_IFC_ACK;
566 
567  /* If using plain read sequence with 10 bit address, switch to send */
568  /* repeated start. */
569  if (seq->flags & I2C_FLAG_READ)
570  {
571  transfer->state = i2cStateRStartAddrSend;
572  }
573  /* Otherwise expected to write 0 or more bytes */
574  else
575  {
576  transfer->state = i2cStateDataSend;
577  }
578  continue;
579  }
580  goto done;
581 
582  /*******************************/
583  /* Send repeated start+address */
584  /*******************************/
585  case i2cStateRStartAddrSend:
586  if (seq->flags & I2C_FLAG_10BIT_ADDR)
587  {
588  tmp = ((seq->addr >> 8) & 0x06) | 0xf0;
589  }
590  else
591  {
592  tmp = seq->addr & 0xfe;
593  }
594 
595  /* If this is a write+read combined sequence, then read is about to start */
596  if (seq->flags & I2C_FLAG_WRITE_READ)
597  {
598  /* Indicate read request */
599  tmp |= 1;
600  }
601 
602  transfer->state = i2cStateRAddrWFAckNack;
603  /* We have to write START cmd first since repeated start, otherwise */
604  /* data would be sent first. */
605  i2c->CMD = I2C_CMD_START;
606  i2c->TXDATA = tmp;
607  goto done;
608 
609  /**********************************************************************/
610  /* Wait for ACK/NACK on repeated start+address (first byte if 10 bit) */
611  /**********************************************************************/
612  case i2cStateRAddrWFAckNack:
613  if (pending & I2C_IF_NACK)
614  {
615  i2c->IFC = I2C_IFC_NACK;
616  transfer->result = i2cTransferNack;
617  transfer->state = i2cStateWFStopSent;
618  i2c->CMD = I2C_CMD_STOP;
619  }
620  else if (pending & I2C_IF_ACK)
621  {
622  i2c->IFC = I2C_IFC_ACK;
623 
624  /* Determine whether receiving or sending data */
625  if (seq->flags & I2C_FLAG_WRITE_READ)
626  {
627  transfer->state = i2cStateWFData;
628  }
629  else
630  {
631  transfer->state = i2cStateDataSend;
632  continue;
633  }
634  }
635  goto done;
636 
637  /*****************************/
638  /* Send a data byte to slave */
639  /*****************************/
640  case i2cStateDataSend:
641  /* Reached end of data buffer? */
642  if (transfer->offset >= seq->buf[transfer->bufIndx].len)
643  {
644  /* Move to next message part */
645  transfer->offset = 0;
646  transfer->bufIndx++;
647 
648  /* Send repeated start when switching to read mode on 2nd buffer */
649  if (seq->flags & I2C_FLAG_WRITE_READ)
650  {
651  transfer->state = i2cStateRStartAddrSend;
652  continue;
653  }
654 
655  /* Only writing from one buffer, or finished both buffers */
656  if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1))
657  {
658  transfer->state = i2cStateWFStopSent;
659  i2c->CMD = I2C_CMD_STOP;
660  goto done;
661  }
662 
663  /* Reprocess in case next buffer is empty */
664  continue;
665  }
666 
667  /* Send byte */
668  i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]);
669  transfer->state = i2cStateDataWFAckNack;
670  goto done;
671 
672  /*********************************************************/
673  /* Wait for ACK/NACK from slave after sending data to it */
674  /*********************************************************/
675  case i2cStateDataWFAckNack:
676  if (pending & I2C_IF_NACK)
677  {
678  i2c->IFC = I2C_IFC_NACK;
679  transfer->result = i2cTransferNack;
680  transfer->state = i2cStateWFStopSent;
681  i2c->CMD = I2C_CMD_STOP;
682  }
683  else if (pending & I2C_IF_ACK)
684  {
685  i2c->IFC = I2C_IFC_ACK;
686  transfer->state = i2cStateDataSend;
687  continue;
688  }
689  goto done;
690 
691  /****************************/
692  /* Wait for data from slave */
693  /****************************/
694  case i2cStateWFData:
695  if (pending & I2C_IF_RXDATAV)
696  {
697  uint8_t data;
698  unsigned int rxLen = seq->buf[transfer->bufIndx].len;
699 
700  /* Must read out data in order to not block further progress */
701  data = (uint8_t)(i2c->RXDATA);
702 
703  /* Make sure not storing beyond end of buffer just in case */
704  if (transfer->offset < rxLen)
705  {
706  seq->buf[transfer->bufIndx].data[transfer->offset++] = data;
707  }
708 
709  /* If we have read all requested data, then the sequence should end */
710  if (transfer->offset >= rxLen)
711  {
712  /* If there is only one byte to receive we need to transmit the
713  NACK now, before the stop. */
714  if (1 == rxLen)
715  {
716  i2c->CMD = I2C_CMD_NACK;
717  }
718 
719  transfer->state = i2cStateWFStopSent;
720  i2c->CMD = I2C_CMD_STOP;
721  }
722  else
723  {
724  /* Send ACK and wait for next byte */
725  i2c->CMD = I2C_CMD_ACK;
726 
727  if ( (1<rxLen) && (transfer->offset == (rxLen-1)) )
728  {
729  /* If there is more than one byte to receive and this is the next
730  to last byte we need to transmit the NACK now, before receiving
731  the last byte. */
732  i2c->CMD = I2C_CMD_NACK;
733  }
734  }
735  }
736  goto done;
737 
738  /***********************************/
739  /* Wait for STOP to have been sent */
740  /***********************************/
741  case i2cStateWFStopSent:
742  if (pending & I2C_IF_MSTOP)
743  {
744  i2c->IFC = I2C_IFC_MSTOP;
745  transfer->state = i2cStateDone;
746  }
747  goto done;
748 
749  /******************************/
750  /* Unexpected state, SW fault */
751  /******************************/
752  default:
753  transfer->result = i2cTransferSwFault;
754  transfer->state = i2cStateDone;
755  goto done;
756  }
757  }
758 
759  done:
760 
761  if (transfer->state == i2cStateDone)
762  {
763  /* Disable interrupt sources when done */
764  i2c->IEN = 0;
765 
766  /* Update result unless some fault already occurred */
767  if (transfer->result == i2cTransferInProgress)
768  {
769  transfer->result = i2cTransferDone;
770  }
771  }
772  /* Until transfer is done keep returning i2cTransferInProgress */
773  else
774  {
775  return i2cTransferInProgress;
776  }
777 
778  return transfer->result;
779 }
780 
781 
782 /***************************************************************************/
809 {
810  I2C_Transfer_TypeDef *transfer;
811 
812  EFM_ASSERT(I2C_REF_VALID(i2c));
813  EFM_ASSERT(seq);
814 
815  /* Support up to 2 I2C buses */
816  if (i2c == I2C0)
817  {
818  transfer = i2cTransfer;
819  }
820 #if (I2C_COUNT > 1)
821  else if (i2c == I2C1)
822  {
823  transfer = i2cTransfer + 1;
824  }
825 #endif
826  else
827  {
828  return i2cTransferUsageFault;
829  }
830 
831  /* Check if in busy state. Since this SW assumes single master, we can */
832  /* just issue an abort. The BUSY state is normal after a reset. */
833  if (i2c->STATE & I2C_STATE_BUSY)
834  {
835  i2c->CMD = I2C_CMD_ABORT;
836  }
837 
838  /* Make sure user is not trying to read 0 bytes, it is not */
839  /* possible according to I2C spec, since slave will always start */
840  /* sending first byte ACK on address. The read operation can */
841  /* only be stopped by NACKing a received byte, ie minimum 1 byte. */
842  if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) ||
843  ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
844  )
845  {
846  return i2cTransferUsageFault;
847  }
848 
849  /* Prepare for a transfer */
850  transfer->state = i2cStateStartAddrSend;
851  transfer->result = i2cTransferInProgress;
852  transfer->offset = 0;
853  transfer->bufIndx = 0;
854  transfer->seq = seq;
855 
856  /* Ensure buffers are empty */
858  if (i2c->IF & I2C_IF_RXDATAV)
859  {
860  (void)i2c->RXDATA;
861  }
862 
863  /* Clear all pending interrupts prior to starting transfer. */
864  i2c->IFC = _I2C_IFC_MASK;
865 
866  /* Enable those interrupts we are interested in throughout transfer. */
867  /* Notice that the I2C interrupt must also be enabled in the NVIC, but */
868  /* that is left for an additional driver wrapper. */
869  i2c->IEN |= I2C_IF_NACK | I2C_IF_ACK | I2C_IF_MSTOP |
870  I2C_IF_RXDATAV | I2C_IF_ERRORS;
871 
872  /* Start transfer */
873  return I2C_Transfer(i2c);
874 }
875 
878 #endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */
Clock management unit (CMU) API.
#define _I2C_CTRL_SLAVE_SHIFT
Definition: efm32zg_i2c.h:74
#define _I2C_IFC_MASK
Definition: efm32zg_i2c.h:505
#define I2C_CMD_NACK
Definition: efm32zg_i2c.h:165
#define I2C_CMD_ACK
Definition: efm32zg_i2c.h:160
Emlib peripheral API "assert" implementation.
#define _I2C_IEN_RESETVALUE
Definition: efm32zg_i2c.h:583
__IOM uint32_t SADDR
Definition: efm32zg_i2c.h:48
__IOM uint32_t CMD
Definition: efm32zg_i2c.h:44
#define I2C_FLAG_READ
Indicate plain read sequence: S+ADDR(R)+DATA0+P.
Definition: em_i2c.h:135
RAM and peripheral bit-field set and clear API.
#define I2C_CMD_START
Definition: efm32zg_i2c.h:150
I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, I2C_TransferSeq_TypeDef *seq)
Prepare and start an I2C transfer (single master mode only).
Definition: em_i2c.c:807
#define _I2C_SADDR_RESETVALUE
Definition: efm32zg_i2c.h:296
void I2C_Enable(I2C_TypeDef *i2c, bool enable)
Enable/disable I2C.
Definition: em_i2c.c:335
#define _I2C_CTRL_RESETVALUE
Definition: efm32zg_i2c.h:66
__IM uint32_t IF
Definition: efm32zg_i2c.h:53
#define I2C_IFC_ACK
Definition: efm32zg_i2c.h:526
#define I2C_IFC_MSTOP
Definition: efm32zg_i2c.h:536
#define I2C_CMD_ABORT
Definition: efm32zg_i2c.h:175
#define I2C_FLAG_WRITE
Indicate plain write sequence: S+ADDR(W)+DATA0+P.
Definition: em_i2c.h:124
__IM uint32_t RXDATA
Definition: efm32zg_i2c.h:50
#define _I2C_CTRL_CLHR_SHIFT
Definition: efm32zg_i2c.h:103
I2C_TransferReturn_TypeDef
Definition: em_i2c.h:179
#define I2C_FLAG_10BIT_ADDR
Definition: em_i2c.h:162
void I2C_Reset(I2C_TypeDef *i2c)
Reset I2C to same state as after a HW reset.
Definition: em_i2c.c:380
#define _I2C_CTRL_CLHR_MASK
Definition: efm32zg_i2c.h:104
#define I2C_IF_ARBLOST
Definition: efm32zg_i2c.h:383
I2C_ClockHLR_TypeDef clhr
Definition: em_i2c.h:223
void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init)
Initialize I2C.
Definition: em_i2c.c:353
#define I2C_COUNT
__IM uint32_t STATE
Definition: efm32zg_i2c.h:45
struct I2C_TransferSeq_TypeDef::@0 buf[2]
#define I2C_CMD_STOP
Definition: efm32zg_i2c.h:155
#define I2C_IF_MSTOP
Definition: efm32zg_i2c.h:378
uint32_t freq
Definition: em_i2c.h:220
#define _I2C_CLKDIV_DIV_MASK
Definition: efm32zg_i2c.h:291
__IOM uint32_t CTRL
Definition: efm32zg_i2c.h:43
void I2C_BusFreqSet(I2C_TypeDef *i2c, uint32_t freqRef, uint32_t freqScl, I2C_ClockHLR_TypeDef i2cMode)
Set I2C bus frequency.
Definition: em_i2c.c:227
__IOM uint32_t TXDATA
Definition: efm32zg_i2c.h:52
#define _I2C_CLKDIV_RESETVALUE
Definition: efm32zg_i2c.h:288
#define I2C_IFC_NACK
Definition: efm32zg_i2c.h:531
#define I2C0
#define I2C_IF_NACK
Definition: efm32zg_i2c.h:373
__IOM uint32_t SADDRMASK
Definition: efm32zg_i2c.h:49
Master mode transfer message structure used to define a complete I2C transfer sequence (from start to...
Definition: em_i2c.h:252
uint32_t refFreq
Definition: em_i2c.h:214
__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val)
Perform peripheral register masked clear and value write.
Definition: em_bus.h:288
__IOM uint32_t CLKDIV
Definition: efm32zg_i2c.h:47
#define _I2C_SADDRMASK_RESETVALUE
Definition: efm32zg_i2c.h:304
I2C_ClockHLR_TypeDef
Definition: em_i2c.h:170
#define I2C_IF_BUSERR
Definition: efm32zg_i2c.h:388
#define I2C_IF_RXDATAV
Definition: efm32zg_i2c.h:363
#define I2C_STATE_BUSY
Definition: efm32zg_i2c.h:194
#define I2C_FLAG_WRITE_READ
Indicate combined write/read sequence: S+ADDR(W)+DATA0+Sr+ADDR(R)+DATA1+P.
Definition: em_i2c.h:148
Inter-intergrated circuit (I2C) peripheral API.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148
__IOM uint32_t IFC
Definition: efm32zg_i2c.h:55
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
Definition: em_cmu.c:1550
uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c)
Get current configured I2C bus frequency.
Definition: em_i2c.c:174
uint16_t addr
Address to use after (repeated) start.
Definition: em_i2c.h:262
#define I2C_CMD_CLEARPC
Definition: efm32zg_i2c.h:185
I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c)
Continue an initiated I2C transfer (single master mode only).
Definition: em_i2c.c:428
#define I2C_IF_ACK
Definition: efm32zg_i2c.h:368
#define I2C_CMD_CLEARTX
Definition: efm32zg_i2c.h:180
__IOM uint32_t IEN
Definition: efm32zg_i2c.h:56
#define _I2C_CTRL_EN_SHIFT
Definition: efm32zg_i2c.h:69
#define I2C_CTRL_SLAVE
Definition: efm32zg_i2c.h:73