EFM32 Wonder Gecko Software Documentation  efm32wg-doc-5.1.2
efm32wg_msc.h
Go to the documentation of this file.
1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
44  __IOM uint32_t READCTRL;
45  __IOM uint32_t WRITECTRL;
46  __IOM uint32_t WRITECMD;
47  __IOM uint32_t ADDRB;
49  uint32_t RESERVED0[1];
50  __IOM uint32_t WDATA;
51  __IM uint32_t STATUS;
53  uint32_t RESERVED1[3];
54  __IM uint32_t IF;
55  __IOM uint32_t IFS;
56  __IOM uint32_t IFC;
57  __IOM uint32_t IEN;
58  __IOM uint32_t LOCK;
59  __IOM uint32_t CMD;
60  __IM uint32_t CACHEHITS;
61  __IM uint32_t CACHEMISSES;
62  uint32_t RESERVED2[1];
63  __IOM uint32_t TIMEBASE;
64  __IOM uint32_t MASSLOCK;
65 } MSC_TypeDef;
67 /**************************************************************************/
72 /* Bit fields for MSC CTRL */
73 #define _MSC_CTRL_RESETVALUE 0x00000001UL
74 #define _MSC_CTRL_MASK 0x00000001UL
75 #define MSC_CTRL_BUSFAULT (0x1UL << 0)
76 #define _MSC_CTRL_BUSFAULT_SHIFT 0
77 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL
78 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL
79 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL
80 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL
81 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0)
82 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0)
83 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0)
85 /* Bit fields for MSC READCTRL */
86 #define _MSC_READCTRL_RESETVALUE 0x00000001UL
87 #define _MSC_READCTRL_MASK 0x000300FFUL
88 #define _MSC_READCTRL_MODE_SHIFT 0
89 #define _MSC_READCTRL_MODE_MASK 0x7UL
90 #define _MSC_READCTRL_MODE_WS0 0x00000000UL
91 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL
92 #define _MSC_READCTRL_MODE_WS1 0x00000001UL
93 #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL
94 #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL
95 #define _MSC_READCTRL_MODE_WS2 0x00000004UL
96 #define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL
97 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0)
98 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0)
99 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0)
100 #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0)
101 #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0)
102 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0)
103 #define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0)
104 #define MSC_READCTRL_IFCDIS (0x1UL << 3)
105 #define _MSC_READCTRL_IFCDIS_SHIFT 3
106 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL
107 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL
108 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3)
109 #define MSC_READCTRL_AIDIS (0x1UL << 4)
110 #define _MSC_READCTRL_AIDIS_SHIFT 4
111 #define _MSC_READCTRL_AIDIS_MASK 0x10UL
112 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL
113 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4)
114 #define MSC_READCTRL_ICCDIS (0x1UL << 5)
115 #define _MSC_READCTRL_ICCDIS_SHIFT 5
116 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL
117 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL
118 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5)
119 #define MSC_READCTRL_EBICDIS (0x1UL << 6)
120 #define _MSC_READCTRL_EBICDIS_SHIFT 6
121 #define _MSC_READCTRL_EBICDIS_MASK 0x40UL
122 #define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL
123 #define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6)
124 #define MSC_READCTRL_RAMCEN (0x1UL << 7)
125 #define _MSC_READCTRL_RAMCEN_SHIFT 7
126 #define _MSC_READCTRL_RAMCEN_MASK 0x80UL
127 #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL
128 #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7)
129 #define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16
130 #define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL
131 #define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL
132 #define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL
133 #define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL
134 #define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL
135 #define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL
136 #define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16)
137 #define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16)
138 #define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16)
139 #define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16)
140 #define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16)
142 /* Bit fields for MSC WRITECTRL */
143 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL
144 #define _MSC_WRITECTRL_MASK 0x00000003UL
145 #define MSC_WRITECTRL_WREN (0x1UL << 0)
146 #define _MSC_WRITECTRL_WREN_SHIFT 0
147 #define _MSC_WRITECTRL_WREN_MASK 0x1UL
148 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL
149 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0)
150 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1)
151 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1
152 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL
153 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL
154 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)
156 /* Bit fields for MSC WRITECMD */
157 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL
158 #define _MSC_WRITECMD_MASK 0x0000113FUL
159 #define MSC_WRITECMD_LADDRIM (0x1UL << 0)
160 #define _MSC_WRITECMD_LADDRIM_SHIFT 0
161 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL
162 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL
163 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)
164 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1)
165 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1
166 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL
167 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL
168 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)
169 #define MSC_WRITECMD_WRITEEND (0x1UL << 2)
170 #define _MSC_WRITECMD_WRITEEND_SHIFT 2
171 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL
172 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL
173 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)
174 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3)
175 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3
176 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL
177 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL
178 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)
179 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4)
180 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4
181 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL
182 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL
183 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)
184 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5)
185 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5
186 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL
187 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL
188 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5)
189 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8)
190 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8
191 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL
192 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL
193 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)
194 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12)
195 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12
196 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL
197 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL
198 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12)
200 /* Bit fields for MSC ADDRB */
201 #define _MSC_ADDRB_RESETVALUE 0x00000000UL
202 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL
203 #define _MSC_ADDRB_ADDRB_SHIFT 0
204 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL
205 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL
206 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0)
208 /* Bit fields for MSC WDATA */
209 #define _MSC_WDATA_RESETVALUE 0x00000000UL
210 #define _MSC_WDATA_MASK 0xFFFFFFFFUL
211 #define _MSC_WDATA_WDATA_SHIFT 0
212 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL
213 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL
214 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0)
216 /* Bit fields for MSC STATUS */
217 #define _MSC_STATUS_RESETVALUE 0x00000008UL
218 #define _MSC_STATUS_MASK 0x0000007FUL
219 #define MSC_STATUS_BUSY (0x1UL << 0)
220 #define _MSC_STATUS_BUSY_SHIFT 0
221 #define _MSC_STATUS_BUSY_MASK 0x1UL
222 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL
223 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0)
224 #define MSC_STATUS_LOCKED (0x1UL << 1)
225 #define _MSC_STATUS_LOCKED_SHIFT 1
226 #define _MSC_STATUS_LOCKED_MASK 0x2UL
227 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL
228 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1)
229 #define MSC_STATUS_INVADDR (0x1UL << 2)
230 #define _MSC_STATUS_INVADDR_SHIFT 2
231 #define _MSC_STATUS_INVADDR_MASK 0x4UL
232 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL
233 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2)
234 #define MSC_STATUS_WDATAREADY (0x1UL << 3)
235 #define _MSC_STATUS_WDATAREADY_SHIFT 3
236 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL
237 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL
238 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3)
239 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4)
240 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4
241 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL
242 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL
243 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)
244 #define MSC_STATUS_ERASEABORTED (0x1UL << 5)
245 #define _MSC_STATUS_ERASEABORTED_SHIFT 5
246 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL
247 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL
248 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5)
249 #define MSC_STATUS_PCRUNNING (0x1UL << 6)
250 #define _MSC_STATUS_PCRUNNING_SHIFT 6
251 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL
252 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL
253 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6)
255 /* Bit fields for MSC IF */
256 #define _MSC_IF_RESETVALUE 0x00000000UL
257 #define _MSC_IF_MASK 0x0000000FUL
258 #define MSC_IF_ERASE (0x1UL << 0)
259 #define _MSC_IF_ERASE_SHIFT 0
260 #define _MSC_IF_ERASE_MASK 0x1UL
261 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL
262 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0)
263 #define MSC_IF_WRITE (0x1UL << 1)
264 #define _MSC_IF_WRITE_SHIFT 1
265 #define _MSC_IF_WRITE_MASK 0x2UL
266 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL
267 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1)
268 #define MSC_IF_CHOF (0x1UL << 2)
269 #define _MSC_IF_CHOF_SHIFT 2
270 #define _MSC_IF_CHOF_MASK 0x4UL
271 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL
272 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2)
273 #define MSC_IF_CMOF (0x1UL << 3)
274 #define _MSC_IF_CMOF_SHIFT 3
275 #define _MSC_IF_CMOF_MASK 0x8UL
276 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL
277 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3)
279 /* Bit fields for MSC IFS */
280 #define _MSC_IFS_RESETVALUE 0x00000000UL
281 #define _MSC_IFS_MASK 0x0000000FUL
282 #define MSC_IFS_ERASE (0x1UL << 0)
283 #define _MSC_IFS_ERASE_SHIFT 0
284 #define _MSC_IFS_ERASE_MASK 0x1UL
285 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL
286 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0)
287 #define MSC_IFS_WRITE (0x1UL << 1)
288 #define _MSC_IFS_WRITE_SHIFT 1
289 #define _MSC_IFS_WRITE_MASK 0x2UL
290 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL
291 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1)
292 #define MSC_IFS_CHOF (0x1UL << 2)
293 #define _MSC_IFS_CHOF_SHIFT 2
294 #define _MSC_IFS_CHOF_MASK 0x4UL
295 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL
296 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2)
297 #define MSC_IFS_CMOF (0x1UL << 3)
298 #define _MSC_IFS_CMOF_SHIFT 3
299 #define _MSC_IFS_CMOF_MASK 0x8UL
300 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL
301 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3)
303 /* Bit fields for MSC IFC */
304 #define _MSC_IFC_RESETVALUE 0x00000000UL
305 #define _MSC_IFC_MASK 0x0000000FUL
306 #define MSC_IFC_ERASE (0x1UL << 0)
307 #define _MSC_IFC_ERASE_SHIFT 0
308 #define _MSC_IFC_ERASE_MASK 0x1UL
309 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL
310 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0)
311 #define MSC_IFC_WRITE (0x1UL << 1)
312 #define _MSC_IFC_WRITE_SHIFT 1
313 #define _MSC_IFC_WRITE_MASK 0x2UL
314 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL
315 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1)
316 #define MSC_IFC_CHOF (0x1UL << 2)
317 #define _MSC_IFC_CHOF_SHIFT 2
318 #define _MSC_IFC_CHOF_MASK 0x4UL
319 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL
320 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2)
321 #define MSC_IFC_CMOF (0x1UL << 3)
322 #define _MSC_IFC_CMOF_SHIFT 3
323 #define _MSC_IFC_CMOF_MASK 0x8UL
324 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL
325 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3)
327 /* Bit fields for MSC IEN */
328 #define _MSC_IEN_RESETVALUE 0x00000000UL
329 #define _MSC_IEN_MASK 0x0000000FUL
330 #define MSC_IEN_ERASE (0x1UL << 0)
331 #define _MSC_IEN_ERASE_SHIFT 0
332 #define _MSC_IEN_ERASE_MASK 0x1UL
333 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL
334 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0)
335 #define MSC_IEN_WRITE (0x1UL << 1)
336 #define _MSC_IEN_WRITE_SHIFT 1
337 #define _MSC_IEN_WRITE_MASK 0x2UL
338 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL
339 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1)
340 #define MSC_IEN_CHOF (0x1UL << 2)
341 #define _MSC_IEN_CHOF_SHIFT 2
342 #define _MSC_IEN_CHOF_MASK 0x4UL
343 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL
344 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2)
345 #define MSC_IEN_CMOF (0x1UL << 3)
346 #define _MSC_IEN_CMOF_SHIFT 3
347 #define _MSC_IEN_CMOF_MASK 0x8UL
348 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL
349 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3)
351 /* Bit fields for MSC LOCK */
352 #define _MSC_LOCK_RESETVALUE 0x00000000UL
353 #define _MSC_LOCK_MASK 0x0000FFFFUL
354 #define _MSC_LOCK_LOCKKEY_SHIFT 0
355 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL
356 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
357 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL
358 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
359 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL
360 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL
361 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0)
362 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0)
363 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0)
364 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0)
365 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0)
367 /* Bit fields for MSC CMD */
368 #define _MSC_CMD_RESETVALUE 0x00000000UL
369 #define _MSC_CMD_MASK 0x00000007UL
370 #define MSC_CMD_INVCACHE (0x1UL << 0)
371 #define _MSC_CMD_INVCACHE_SHIFT 0
372 #define _MSC_CMD_INVCACHE_MASK 0x1UL
373 #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL
374 #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0)
375 #define MSC_CMD_STARTPC (0x1UL << 1)
376 #define _MSC_CMD_STARTPC_SHIFT 1
377 #define _MSC_CMD_STARTPC_MASK 0x2UL
378 #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL
379 #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1)
380 #define MSC_CMD_STOPPC (0x1UL << 2)
381 #define _MSC_CMD_STOPPC_SHIFT 2
382 #define _MSC_CMD_STOPPC_MASK 0x4UL
383 #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL
384 #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2)
386 /* Bit fields for MSC CACHEHITS */
387 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL
388 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL
389 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0
390 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL
391 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL
392 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0)
394 /* Bit fields for MSC CACHEMISSES */
395 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL
396 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL
397 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0
398 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL
399 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL
400 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0)
402 /* Bit fields for MSC TIMEBASE */
403 #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL
404 #define _MSC_TIMEBASE_MASK 0x0001003FUL
405 #define _MSC_TIMEBASE_BASE_SHIFT 0
406 #define _MSC_TIMEBASE_BASE_MASK 0x3FUL
407 #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL
408 #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0)
409 #define MSC_TIMEBASE_PERIOD (0x1UL << 16)
410 #define _MSC_TIMEBASE_PERIOD_SHIFT 16
411 #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL
412 #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL
413 #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL
414 #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL
415 #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16)
416 #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16)
417 #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16)
419 /* Bit fields for MSC MASSLOCK */
420 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL
421 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL
422 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0
423 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL
424 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL
425 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL
426 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL
427 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL
428 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL
429 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0)
430 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0)
431 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)
432 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0)
433 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)
__IOM uint32_t MASSLOCK
Definition: efm32wg_msc.h:64
__IM uint32_t CACHEHITS
Definition: efm32wg_msc.h:60
__IOM uint32_t LOCK
Definition: efm32wg_msc.h:58
__IOM uint32_t IEN
Definition: efm32wg_msc.h:57
__IM uint32_t STATUS
Definition: efm32wg_msc.h:51
__IOM uint32_t WDATA
Definition: efm32wg_msc.h:50
__IOM uint32_t TIMEBASE
Definition: efm32wg_msc.h:63
__IOM uint32_t READCTRL
Definition: efm32wg_msc.h:44
__IOM uint32_t IFC
Definition: efm32wg_msc.h:56
__IOM uint32_t ADDRB
Definition: efm32wg_msc.h:47
__IM uint32_t CACHEMISSES
Definition: efm32wg_msc.h:61
__IOM uint32_t IFS
Definition: efm32wg_msc.h:55
__IOM uint32_t WRITECTRL
Definition: efm32wg_msc.h:45
__IOM uint32_t CMD
Definition: efm32wg_msc.h:59
__IOM uint32_t CTRL
Definition: efm32wg_msc.h:43
__IM uint32_t IF
Definition: efm32wg_msc.h:54
__IOM uint32_t WRITECMD
Definition: efm32wg_msc.h:46