EFM32 Wonder Gecko Software Documentation  efm32wg-doc-5.1.2
efm32wg_emu.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
45  uint32_t RESERVED0[1];
46  __IOM uint32_t LOCK;
48  uint32_t RESERVED1[6];
49  __IOM uint32_t AUXCTRL;
51  uint32_t RESERVED2[1];
52  __IOM uint32_t EM4CONF;
53  __IOM uint32_t BUCTRL;
54  __IOM uint32_t PWRCONF;
55  __IOM uint32_t BUINACT;
56  __IOM uint32_t BUACT;
57  __IM uint32_t STATUS;
58  __IOM uint32_t ROUTE;
59  __IM uint32_t IF;
60  __IOM uint32_t IFS;
61  __IOM uint32_t IFC;
62  __IOM uint32_t IEN;
63  __IOM uint32_t BUBODBUVINCAL;
64  __IOM uint32_t BUBODUNREGCAL;
65 } EMU_TypeDef;
67 /**************************************************************************/
72 /* Bit fields for EMU CTRL */
73 #define _EMU_CTRL_RESETVALUE 0x00000000UL
74 #define _EMU_CTRL_MASK 0x0000000FUL
75 #define EMU_CTRL_EMVREG (0x1UL << 0)
76 #define _EMU_CTRL_EMVREG_SHIFT 0
77 #define _EMU_CTRL_EMVREG_MASK 0x1UL
78 #define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL
79 #define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL
80 #define _EMU_CTRL_EMVREG_FULL 0x00000001UL
81 #define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0)
82 #define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0)
83 #define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0)
84 #define EMU_CTRL_EM2BLOCK (0x1UL << 1)
85 #define _EMU_CTRL_EM2BLOCK_SHIFT 1
86 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL
87 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL
88 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)
89 #define _EMU_CTRL_EM4CTRL_SHIFT 2
90 #define _EMU_CTRL_EM4CTRL_MASK 0xCUL
91 #define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL
92 #define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2)
94 /* Bit fields for EMU LOCK */
95 #define _EMU_LOCK_RESETVALUE 0x00000000UL
96 #define _EMU_LOCK_MASK 0x0000FFFFUL
97 #define _EMU_LOCK_LOCKKEY_SHIFT 0
98 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL
99 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
100 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL
101 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
102 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
103 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL
104 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0)
105 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0)
106 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0)
107 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0)
108 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0)
110 /* Bit fields for EMU AUXCTRL */
111 #define _EMU_AUXCTRL_RESETVALUE 0x00000000UL
112 #define _EMU_AUXCTRL_MASK 0x00000001UL
113 #define EMU_AUXCTRL_HRCCLR (0x1UL << 0)
114 #define _EMU_AUXCTRL_HRCCLR_SHIFT 0
115 #define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL
116 #define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL
117 #define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0)
119 /* Bit fields for EMU EM4CONF */
120 #define _EMU_EM4CONF_RESETVALUE 0x00000000UL
121 #define _EMU_EM4CONF_MASK 0x0001001FUL
122 #define EMU_EM4CONF_VREGEN (0x1UL << 0)
123 #define _EMU_EM4CONF_VREGEN_SHIFT 0
124 #define _EMU_EM4CONF_VREGEN_MASK 0x1UL
125 #define _EMU_EM4CONF_VREGEN_DEFAULT 0x00000000UL
126 #define EMU_EM4CONF_VREGEN_DEFAULT (_EMU_EM4CONF_VREGEN_DEFAULT << 0)
127 #define EMU_EM4CONF_BURTCWU (0x1UL << 1)
128 #define _EMU_EM4CONF_BURTCWU_SHIFT 1
129 #define _EMU_EM4CONF_BURTCWU_MASK 0x2UL
130 #define _EMU_EM4CONF_BURTCWU_DEFAULT 0x00000000UL
131 #define EMU_EM4CONF_BURTCWU_DEFAULT (_EMU_EM4CONF_BURTCWU_DEFAULT << 1)
132 #define _EMU_EM4CONF_OSC_SHIFT 2
133 #define _EMU_EM4CONF_OSC_MASK 0xCUL
134 #define _EMU_EM4CONF_OSC_DEFAULT 0x00000000UL
135 #define _EMU_EM4CONF_OSC_ULFRCO 0x00000000UL
136 #define _EMU_EM4CONF_OSC_LFRCO 0x00000001UL
137 #define _EMU_EM4CONF_OSC_LFXO 0x00000002UL
138 #define EMU_EM4CONF_OSC_DEFAULT (_EMU_EM4CONF_OSC_DEFAULT << 2)
139 #define EMU_EM4CONF_OSC_ULFRCO (_EMU_EM4CONF_OSC_ULFRCO << 2)
140 #define EMU_EM4CONF_OSC_LFRCO (_EMU_EM4CONF_OSC_LFRCO << 2)
141 #define EMU_EM4CONF_OSC_LFXO (_EMU_EM4CONF_OSC_LFXO << 2)
142 #define EMU_EM4CONF_BUBODRSTDIS (0x1UL << 4)
143 #define _EMU_EM4CONF_BUBODRSTDIS_SHIFT 4
144 #define _EMU_EM4CONF_BUBODRSTDIS_MASK 0x10UL
145 #define _EMU_EM4CONF_BUBODRSTDIS_DEFAULT 0x00000000UL
146 #define EMU_EM4CONF_BUBODRSTDIS_DEFAULT (_EMU_EM4CONF_BUBODRSTDIS_DEFAULT << 4)
147 #define EMU_EM4CONF_LOCKCONF (0x1UL << 16)
148 #define _EMU_EM4CONF_LOCKCONF_SHIFT 16
149 #define _EMU_EM4CONF_LOCKCONF_MASK 0x10000UL
150 #define _EMU_EM4CONF_LOCKCONF_DEFAULT 0x00000000UL
151 #define EMU_EM4CONF_LOCKCONF_DEFAULT (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16)
153 /* Bit fields for EMU BUCTRL */
154 #define _EMU_BUCTRL_RESETVALUE 0x00000000UL
155 #define _EMU_BUCTRL_MASK 0x0000006FUL
156 #define EMU_BUCTRL_EN (0x1UL << 0)
157 #define _EMU_BUCTRL_EN_SHIFT 0
158 #define _EMU_BUCTRL_EN_MASK 0x1UL
159 #define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL
160 #define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0)
161 #define EMU_BUCTRL_STATEN (0x1UL << 1)
162 #define _EMU_BUCTRL_STATEN_SHIFT 1
163 #define _EMU_BUCTRL_STATEN_MASK 0x2UL
164 #define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL
165 #define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1)
166 #define EMU_BUCTRL_BODCAL (0x1UL << 2)
167 #define _EMU_BUCTRL_BODCAL_SHIFT 2
168 #define _EMU_BUCTRL_BODCAL_MASK 0x4UL
169 #define _EMU_BUCTRL_BODCAL_DEFAULT 0x00000000UL
170 #define EMU_BUCTRL_BODCAL_DEFAULT (_EMU_BUCTRL_BODCAL_DEFAULT << 2)
171 #define EMU_BUCTRL_BUMODEBODEN (0x1UL << 3)
172 #define _EMU_BUCTRL_BUMODEBODEN_SHIFT 3
173 #define _EMU_BUCTRL_BUMODEBODEN_MASK 0x8UL
174 #define _EMU_BUCTRL_BUMODEBODEN_DEFAULT 0x00000000UL
175 #define EMU_BUCTRL_BUMODEBODEN_DEFAULT (_EMU_BUCTRL_BUMODEBODEN_DEFAULT << 3)
176 #define _EMU_BUCTRL_PROBE_SHIFT 5
177 #define _EMU_BUCTRL_PROBE_MASK 0x60UL
178 #define _EMU_BUCTRL_PROBE_DEFAULT 0x00000000UL
179 #define _EMU_BUCTRL_PROBE_DISABLE 0x00000000UL
180 #define _EMU_BUCTRL_PROBE_VDDDREG 0x00000001UL
181 #define _EMU_BUCTRL_PROBE_BUIN 0x00000002UL
182 #define _EMU_BUCTRL_PROBE_BUOUT 0x00000003UL
183 #define EMU_BUCTRL_PROBE_DEFAULT (_EMU_BUCTRL_PROBE_DEFAULT << 5)
184 #define EMU_BUCTRL_PROBE_DISABLE (_EMU_BUCTRL_PROBE_DISABLE << 5)
185 #define EMU_BUCTRL_PROBE_VDDDREG (_EMU_BUCTRL_PROBE_VDDDREG << 5)
186 #define EMU_BUCTRL_PROBE_BUIN (_EMU_BUCTRL_PROBE_BUIN << 5)
187 #define EMU_BUCTRL_PROBE_BUOUT (_EMU_BUCTRL_PROBE_BUOUT << 5)
189 /* Bit fields for EMU PWRCONF */
190 #define _EMU_PWRCONF_RESETVALUE 0x00000000UL
191 #define _EMU_PWRCONF_MASK 0x0000001FUL
192 #define EMU_PWRCONF_VOUTWEAK (0x1UL << 0)
193 #define _EMU_PWRCONF_VOUTWEAK_SHIFT 0
194 #define _EMU_PWRCONF_VOUTWEAK_MASK 0x1UL
195 #define _EMU_PWRCONF_VOUTWEAK_DEFAULT 0x00000000UL
196 #define EMU_PWRCONF_VOUTWEAK_DEFAULT (_EMU_PWRCONF_VOUTWEAK_DEFAULT << 0)
197 #define EMU_PWRCONF_VOUTMED (0x1UL << 1)
198 #define _EMU_PWRCONF_VOUTMED_SHIFT 1
199 #define _EMU_PWRCONF_VOUTMED_MASK 0x2UL
200 #define _EMU_PWRCONF_VOUTMED_DEFAULT 0x00000000UL
201 #define EMU_PWRCONF_VOUTMED_DEFAULT (_EMU_PWRCONF_VOUTMED_DEFAULT << 1)
202 #define EMU_PWRCONF_VOUTSTRONG (0x1UL << 2)
203 #define _EMU_PWRCONF_VOUTSTRONG_SHIFT 2
204 #define _EMU_PWRCONF_VOUTSTRONG_MASK 0x4UL
205 #define _EMU_PWRCONF_VOUTSTRONG_DEFAULT 0x00000000UL
206 #define EMU_PWRCONF_VOUTSTRONG_DEFAULT (_EMU_PWRCONF_VOUTSTRONG_DEFAULT << 2)
207 #define _EMU_PWRCONF_PWRRES_SHIFT 3
208 #define _EMU_PWRCONF_PWRRES_MASK 0x18UL
209 #define _EMU_PWRCONF_PWRRES_DEFAULT 0x00000000UL
210 #define _EMU_PWRCONF_PWRRES_RES0 0x00000000UL
211 #define _EMU_PWRCONF_PWRRES_RES1 0x00000001UL
212 #define _EMU_PWRCONF_PWRRES_RES2 0x00000002UL
213 #define _EMU_PWRCONF_PWRRES_RES3 0x00000003UL
214 #define EMU_PWRCONF_PWRRES_DEFAULT (_EMU_PWRCONF_PWRRES_DEFAULT << 3)
215 #define EMU_PWRCONF_PWRRES_RES0 (_EMU_PWRCONF_PWRRES_RES0 << 3)
216 #define EMU_PWRCONF_PWRRES_RES1 (_EMU_PWRCONF_PWRRES_RES1 << 3)
217 #define EMU_PWRCONF_PWRRES_RES2 (_EMU_PWRCONF_PWRRES_RES2 << 3)
218 #define EMU_PWRCONF_PWRRES_RES3 (_EMU_PWRCONF_PWRRES_RES3 << 3)
220 /* Bit fields for EMU BUINACT */
221 #define _EMU_BUINACT_RESETVALUE 0x0000000BUL
222 #define _EMU_BUINACT_MASK 0x0000007FUL
223 #define _EMU_BUINACT_BUENTHRES_SHIFT 0
224 #define _EMU_BUINACT_BUENTHRES_MASK 0x7UL
225 #define _EMU_BUINACT_BUENTHRES_DEFAULT 0x00000003UL
226 #define EMU_BUINACT_BUENTHRES_DEFAULT (_EMU_BUINACT_BUENTHRES_DEFAULT << 0)
227 #define _EMU_BUINACT_BUENRANGE_SHIFT 3
228 #define _EMU_BUINACT_BUENRANGE_MASK 0x18UL
229 #define _EMU_BUINACT_BUENRANGE_DEFAULT 0x00000001UL
230 #define EMU_BUINACT_BUENRANGE_DEFAULT (_EMU_BUINACT_BUENRANGE_DEFAULT << 3)
231 #define _EMU_BUINACT_PWRCON_SHIFT 5
232 #define _EMU_BUINACT_PWRCON_MASK 0x60UL
233 #define _EMU_BUINACT_PWRCON_DEFAULT 0x00000000UL
234 #define _EMU_BUINACT_PWRCON_NONE 0x00000000UL
235 #define _EMU_BUINACT_PWRCON_BUMAIN 0x00000001UL
236 #define _EMU_BUINACT_PWRCON_MAINBU 0x00000002UL
237 #define _EMU_BUINACT_PWRCON_NODIODE 0x00000003UL
238 #define EMU_BUINACT_PWRCON_DEFAULT (_EMU_BUINACT_PWRCON_DEFAULT << 5)
239 #define EMU_BUINACT_PWRCON_NONE (_EMU_BUINACT_PWRCON_NONE << 5)
240 #define EMU_BUINACT_PWRCON_BUMAIN (_EMU_BUINACT_PWRCON_BUMAIN << 5)
241 #define EMU_BUINACT_PWRCON_MAINBU (_EMU_BUINACT_PWRCON_MAINBU << 5)
242 #define EMU_BUINACT_PWRCON_NODIODE (_EMU_BUINACT_PWRCON_NODIODE << 5)
244 /* Bit fields for EMU BUACT */
245 #define _EMU_BUACT_RESETVALUE 0x0000000BUL
246 #define _EMU_BUACT_MASK 0x0000007FUL
247 #define _EMU_BUACT_BUEXTHRES_SHIFT 0
248 #define _EMU_BUACT_BUEXTHRES_MASK 0x7UL
249 #define _EMU_BUACT_BUEXTHRES_DEFAULT 0x00000003UL
250 #define EMU_BUACT_BUEXTHRES_DEFAULT (_EMU_BUACT_BUEXTHRES_DEFAULT << 0)
251 #define _EMU_BUACT_BUEXRANGE_SHIFT 3
252 #define _EMU_BUACT_BUEXRANGE_MASK 0x18UL
253 #define _EMU_BUACT_BUEXRANGE_DEFAULT 0x00000001UL
254 #define EMU_BUACT_BUEXRANGE_DEFAULT (_EMU_BUACT_BUEXRANGE_DEFAULT << 3)
255 #define _EMU_BUACT_PWRCON_SHIFT 5
256 #define _EMU_BUACT_PWRCON_MASK 0x60UL
257 #define _EMU_BUACT_PWRCON_DEFAULT 0x00000000UL
258 #define _EMU_BUACT_PWRCON_NONE 0x00000000UL
259 #define _EMU_BUACT_PWRCON_BUMAIN 0x00000001UL
260 #define _EMU_BUACT_PWRCON_MAINBU 0x00000002UL
261 #define _EMU_BUACT_PWRCON_NODIODE 0x00000003UL
262 #define EMU_BUACT_PWRCON_DEFAULT (_EMU_BUACT_PWRCON_DEFAULT << 5)
263 #define EMU_BUACT_PWRCON_NONE (_EMU_BUACT_PWRCON_NONE << 5)
264 #define EMU_BUACT_PWRCON_BUMAIN (_EMU_BUACT_PWRCON_BUMAIN << 5)
265 #define EMU_BUACT_PWRCON_MAINBU (_EMU_BUACT_PWRCON_MAINBU << 5)
266 #define EMU_BUACT_PWRCON_NODIODE (_EMU_BUACT_PWRCON_NODIODE << 5)
268 /* Bit fields for EMU STATUS */
269 #define _EMU_STATUS_RESETVALUE 0x00000000UL
270 #define _EMU_STATUS_MASK 0x00000001UL
271 #define EMU_STATUS_BURDY (0x1UL << 0)
272 #define _EMU_STATUS_BURDY_SHIFT 0
273 #define _EMU_STATUS_BURDY_MASK 0x1UL
274 #define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL
275 #define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 0)
277 /* Bit fields for EMU ROUTE */
278 #define _EMU_ROUTE_RESETVALUE 0x00000001UL
279 #define _EMU_ROUTE_MASK 0x00000001UL
280 #define EMU_ROUTE_BUVINPEN (0x1UL << 0)
281 #define _EMU_ROUTE_BUVINPEN_SHIFT 0
282 #define _EMU_ROUTE_BUVINPEN_MASK 0x1UL
283 #define _EMU_ROUTE_BUVINPEN_DEFAULT 0x00000001UL
284 #define EMU_ROUTE_BUVINPEN_DEFAULT (_EMU_ROUTE_BUVINPEN_DEFAULT << 0)
286 /* Bit fields for EMU IF */
287 #define _EMU_IF_RESETVALUE 0x00000000UL
288 #define _EMU_IF_MASK 0x00000001UL
289 #define EMU_IF_BURDY (0x1UL << 0)
290 #define _EMU_IF_BURDY_SHIFT 0
291 #define _EMU_IF_BURDY_MASK 0x1UL
292 #define _EMU_IF_BURDY_DEFAULT 0x00000000UL
293 #define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 0)
295 /* Bit fields for EMU IFS */
296 #define _EMU_IFS_RESETVALUE 0x00000000UL
297 #define _EMU_IFS_MASK 0x00000001UL
298 #define EMU_IFS_BURDY (0x1UL << 0)
299 #define _EMU_IFS_BURDY_SHIFT 0
300 #define _EMU_IFS_BURDY_MASK 0x1UL
301 #define _EMU_IFS_BURDY_DEFAULT 0x00000000UL
302 #define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 0)
304 /* Bit fields for EMU IFC */
305 #define _EMU_IFC_RESETVALUE 0x00000000UL
306 #define _EMU_IFC_MASK 0x00000001UL
307 #define EMU_IFC_BURDY (0x1UL << 0)
308 #define _EMU_IFC_BURDY_SHIFT 0
309 #define _EMU_IFC_BURDY_MASK 0x1UL
310 #define _EMU_IFC_BURDY_DEFAULT 0x00000000UL
311 #define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 0)
313 /* Bit fields for EMU IEN */
314 #define _EMU_IEN_RESETVALUE 0x00000000UL
315 #define _EMU_IEN_MASK 0x00000001UL
316 #define EMU_IEN_BURDY (0x1UL << 0)
317 #define _EMU_IEN_BURDY_SHIFT 0
318 #define _EMU_IEN_BURDY_MASK 0x1UL
319 #define _EMU_IEN_BURDY_DEFAULT 0x00000000UL
320 #define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 0)
322 /* Bit fields for EMU BUBODBUVINCAL */
323 #define _EMU_BUBODBUVINCAL_RESETVALUE 0x0000000BUL
324 #define _EMU_BUBODBUVINCAL_MASK 0x0000001FUL
325 #define _EMU_BUBODBUVINCAL_THRES_SHIFT 0
326 #define _EMU_BUBODBUVINCAL_THRES_MASK 0x7UL
327 #define _EMU_BUBODBUVINCAL_THRES_DEFAULT 0x00000003UL
328 #define EMU_BUBODBUVINCAL_THRES_DEFAULT (_EMU_BUBODBUVINCAL_THRES_DEFAULT << 0)
329 #define _EMU_BUBODBUVINCAL_RANGE_SHIFT 3
330 #define _EMU_BUBODBUVINCAL_RANGE_MASK 0x18UL
331 #define _EMU_BUBODBUVINCAL_RANGE_DEFAULT 0x00000001UL
332 #define EMU_BUBODBUVINCAL_RANGE_DEFAULT (_EMU_BUBODBUVINCAL_RANGE_DEFAULT << 3)
334 /* Bit fields for EMU BUBODUNREGCAL */
335 #define _EMU_BUBODUNREGCAL_RESETVALUE 0x0000000BUL
336 #define _EMU_BUBODUNREGCAL_MASK 0x0000001FUL
337 #define _EMU_BUBODUNREGCAL_THRES_SHIFT 0
338 #define _EMU_BUBODUNREGCAL_THRES_MASK 0x7UL
339 #define _EMU_BUBODUNREGCAL_THRES_DEFAULT 0x00000003UL
340 #define EMU_BUBODUNREGCAL_THRES_DEFAULT (_EMU_BUBODUNREGCAL_THRES_DEFAULT << 0)
341 #define _EMU_BUBODUNREGCAL_RANGE_SHIFT 3
342 #define _EMU_BUBODUNREGCAL_RANGE_MASK 0x18UL
343 #define _EMU_BUBODUNREGCAL_RANGE_DEFAULT 0x00000001UL
344 #define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3)
__IOM uint32_t PWRCONF
Definition: efm32wg_emu.h:54
__IOM uint32_t EM4CONF
Definition: efm32wg_emu.h:52
__IOM uint32_t IFS
Definition: efm32wg_emu.h:60
__IOM uint32_t IFC
Definition: efm32wg_emu.h:61
__IOM uint32_t IEN
Definition: efm32wg_emu.h:62
__IOM uint32_t ROUTE
Definition: efm32wg_emu.h:58
__IOM uint32_t BUBODUNREGCAL
Definition: efm32wg_emu.h:64
__IOM uint32_t BUCTRL
Definition: efm32wg_emu.h:53
__IM uint32_t IF
Definition: efm32wg_emu.h:59
__IOM uint32_t CTRL
Definition: efm32wg_emu.h:43
__IOM uint32_t BUACT
Definition: efm32wg_emu.h:56
__IM uint32_t STATUS
Definition: efm32wg_emu.h:57
__IOM uint32_t AUXCTRL
Definition: efm32wg_emu.h:49
__IOM uint32_t BUINACT
Definition: efm32wg_emu.h:55
__IOM uint32_t LOCK
Definition: efm32wg_emu.h:46
__IOM uint32_t BUBODBUVINCAL
Definition: efm32wg_emu.h:63