EFM32 Pearl Gecko 12 Software Documentation
efm32pg12-doc-5.1.2
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EFM32PG12B_DMAREQ register and bit field definitions.
Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
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Definition in file efm32pg12b_dmareq.h.
Go to the source code of this file.
Macros | |
#define | DMAREQ_ADC0_SCAN ((8 << 16) + 1) |
#define | DMAREQ_ADC0_SINGLE ((8 << 16) + 0) |
#define | DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) |
#define | DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) |
#define | DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) |
#define | DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) |
#define | DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) |
#define | DMAREQ_CRYPTO1_DATA0RD ((52 << 16) + 2) |
#define | DMAREQ_CRYPTO1_DATA0WR ((52 << 16) + 0) |
#define | DMAREQ_CRYPTO1_DATA0XWR ((52 << 16) + 1) |
#define | DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) |
#define | DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) |
#define | DMAREQ_CRYPTO_DATA0RD DMAREQ_CRYPTO0_DATA0RD |
#define | DMAREQ_CRYPTO_DATA0WR DMAREQ_CRYPTO0_DATA0WR |
#define | DMAREQ_CRYPTO_DATA0XWR DMAREQ_CRYPTO0_DATA0XWR |
#define | DMAREQ_CRYPTO_DATA1RD DMAREQ_CRYPTO0_DATA1RD |
#define | DMAREQ_CRYPTO_DATA1WR DMAREQ_CRYPTO0_DATA1WR |
#define | DMAREQ_CSEN_BSLN ((50 << 16) + 1) |
#define | DMAREQ_CSEN_DATA ((50 << 16) + 0) |
#define | DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) |
#define | DMAREQ_I2C0_TXBL ((20 << 16) + 1) |
#define | DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) |
#define | DMAREQ_I2C1_TXBL ((21 << 16) + 1) |
#define | DMAREQ_LESENSE_BUFDATAV ((51 << 16) + 0) |
#define | DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) |
#define | DMAREQ_LEUART0_TXBL ((16 << 16) + 1) |
#define | DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) |
#define | DMAREQ_MSC_WDATA ((48 << 16) + 0) |
#define | DMAREQ_PRS_REQ0 ((1 << 16) + 0) |
#define | DMAREQ_PRS_REQ1 ((1 << 16) + 1) |
#define | DMAREQ_TIMER0_CC0 ((24 << 16) + 1) |
#define | DMAREQ_TIMER0_CC1 ((24 << 16) + 2) |
#define | DMAREQ_TIMER0_CC2 ((24 << 16) + 3) |
#define | DMAREQ_TIMER0_UFOF ((24 << 16) + 0) |
#define | DMAREQ_TIMER1_CC0 ((25 << 16) + 1) |
#define | DMAREQ_TIMER1_CC1 ((25 << 16) + 2) |
#define | DMAREQ_TIMER1_CC2 ((25 << 16) + 3) |
#define | DMAREQ_TIMER1_CC3 ((25 << 16) + 4) |
#define | DMAREQ_TIMER1_UFOF ((25 << 16) + 0) |
#define | DMAREQ_USART0_RXDATAV ((12 << 16) + 0) |
#define | DMAREQ_USART0_TXBL ((12 << 16) + 1) |
#define | DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) |
#define | DMAREQ_USART1_RXDATAV ((13 << 16) + 0) |
#define | DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) |
#define | DMAREQ_USART1_TXBL ((13 << 16) + 1) |
#define | DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) |
#define | DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) |
#define | DMAREQ_USART2_RXDATAV ((14 << 16) + 0) |
#define | DMAREQ_USART2_TXBL ((14 << 16) + 1) |
#define | DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) |
#define | DMAREQ_USART3_RXDATAV ((15 << 16) + 0) |
#define | DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) |
#define | DMAREQ_USART3_TXBL ((15 << 16) + 1) |
#define | DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) |
#define | DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) |
#define | DMAREQ_VDAC0_CH0 ((10 << 16) + 0) |
#define | DMAREQ_VDAC0_CH1 ((10 << 16) + 1) |
#define | DMAREQ_WTIMER0_CC0 ((26 << 16) + 1) |
#define | DMAREQ_WTIMER0_CC1 ((26 << 16) + 2) |
#define | DMAREQ_WTIMER0_CC2 ((26 << 16) + 3) |
#define | DMAREQ_WTIMER0_UFOF ((26 << 16) + 0) |
#define | DMAREQ_WTIMER1_CC0 ((27 << 16) + 1) |
#define | DMAREQ_WTIMER1_CC1 ((27 << 16) + 2) |
#define | DMAREQ_WTIMER1_CC2 ((27 << 16) + 3) |
#define | DMAREQ_WTIMER1_CC3 ((27 << 16) + 4) |
#define | DMAREQ_WTIMER1_UFOF ((27 << 16) + 0) |