EFM32 Jade Gecko 12 Software Documentation  efm32jg12-doc-5.1.2
Macros
EFM32JG12B_ETM_BitFields
Devices

Detailed Description

Macros

#define _ETM_ETMAUTHSTATUS_MASK   0x000000FFUL
 
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT   0x00000000UL
 
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK   0x3UL
 
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT   0
 
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT   0x00000000UL
 
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE   0x00000002UL
 
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE   0x00000003UL
 
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK   0xCUL
 
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT   2
 
#define _ETM_ETMAUTHSTATUS_RESETVALUE   0x000000C0UL
 
#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT   0x00000000UL
 
#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK   0x30UL
 
#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT   4
 
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT   0x00000003UL
 
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK   0xC0UL
 
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT   6
 
#define _ETM_ETMCCER_DADDRCMP_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCER_DADDRCMP_MASK   0x1000UL
 
#define _ETM_ETMCCER_DADDRCMP_SHIFT   12
 
#define _ETM_ETMCCER_EICEIMP_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCER_EICEIMP_MASK   0x200000UL
 
#define _ETM_ETMCCER_EICEIMP_SHIFT   21
 
#define _ETM_ETMCCER_EICEWPNT_DEFAULT   0x00000004UL
 
#define _ETM_ETMCCER_EICEWPNT_MASK   0xF0000UL
 
#define _ETM_ETMCCER_EICEWPNT_SHIFT   16
 
#define _ETM_ETMCCER_EXTINPBUS_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCER_EXTINPBUS_MASK   0x7F8UL
 
#define _ETM_ETMCCER_EXTINPBUS_SHIFT   3
 
#define _ETM_ETMCCER_EXTINPSEL_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCER_EXTINPSEL_MASK   0x3UL
 
#define _ETM_ETMCCER_EXTINPSEL_SHIFT   0
 
#define _ETM_ETMCCER_INSTRES_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCER_INSTRES_MASK   0xE000UL
 
#define _ETM_ETMCCER_INSTRES_SHIFT   13
 
#define _ETM_ETMCCER_MASK   0x387FFFFBUL
 
#define _ETM_ETMCCER_READREGS_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCER_READREGS_MASK   0x800UL
 
#define _ETM_ETMCCER_READREGS_SHIFT   11
 
#define _ETM_ETMCCER_RESETVALUE   0x18541800UL
 
#define _ETM_ETMCCER_RFCNT_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCER_RFCNT_MASK   0x8000000UL
 
#define _ETM_ETMCCER_RFCNT_SHIFT   27
 
#define _ETM_ETMCCER_TEICEWPNT_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCER_TEICEWPNT_MASK   0x100000UL
 
#define _ETM_ETMCCER_TEICEWPNT_SHIFT   20
 
#define _ETM_ETMCCER_TENC_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCER_TENC_MASK   0x10000000UL
 
#define _ETM_ETMCCER_TENC_SHIFT   28
 
#define _ETM_ETMCCER_TIMP_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCER_TIMP_MASK   0x400000UL
 
#define _ETM_ETMCCER_TIMP_SHIFT   22
 
#define _ETM_ETMCCER_TSIZE_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCER_TSIZE_MASK   0x20000000UL
 
#define _ETM_ETMCCER_TSIZE_SHIFT   29
 
#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCR_ADRCMPPAIR_MASK   0xFUL
 
#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT   0
 
#define _ETM_ETMCCR_COUNTNUM_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCR_COUNTNUM_MASK   0xE000UL
 
#define _ETM_ETMCCR_COUNTNUM_SHIFT   13
 
#define _ETM_ETMCCR_DATACMPNUM_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCR_DATACMPNUM_MASK   0xF0UL
 
#define _ETM_ETMCCR_DATACMPNUM_SHIFT   4
 
#define _ETM_ETMCCR_ETMID_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCR_ETMID_MASK   0x80000000UL
 
#define _ETM_ETMCCR_ETMID_SHIFT   31
 
#define _ETM_ETMCCR_EXTINPNUM_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCR_EXTINPNUM_MASK   0xE0000UL
 
#define _ETM_ETMCCR_EXTINPNUM_ONE   0x00000001UL
 
#define _ETM_ETMCCR_EXTINPNUM_SHIFT   17
 
#define _ETM_ETMCCR_EXTINPNUM_TWO   0x00000002UL
 
#define _ETM_ETMCCR_EXTINPNUM_ZERO   0x00000000UL
 
#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCR_EXTOUTNUM_MASK   0x700000UL
 
#define _ETM_ETMCCR_EXTOUTNUM_SHIFT   20
 
#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCR_FIFOFULLPRES_MASK   0x800000UL
 
#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT   23
 
#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCR_IDCOMPNUM_MASK   0x3000000UL
 
#define _ETM_ETMCCR_IDCOMPNUM_SHIFT   24
 
#define _ETM_ETMCCR_MASK   0x8FFFFFFFUL
 
#define _ETM_ETMCCR_MMACCESS_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCR_MMACCESS_MASK   0x8000000UL
 
#define _ETM_ETMCCR_MMACCESS_SHIFT   27
 
#define _ETM_ETMCCR_MMDECCNT_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCR_MMDECCNT_MASK   0x1F00UL
 
#define _ETM_ETMCCR_MMDECCNT_SHIFT   8
 
#define _ETM_ETMCCR_RESETVALUE   0x8C802000UL
 
#define _ETM_ETMCCR_SEQPRES_DEFAULT   0x00000000UL
 
#define _ETM_ETMCCR_SEQPRES_MASK   0x10000UL
 
#define _ETM_ETMCCR_SEQPRES_SHIFT   16
 
#define _ETM_ETMCCR_TRACESS_DEFAULT   0x00000001UL
 
#define _ETM_ETMCCR_TRACESS_MASK   0x4000000UL
 
#define _ETM_ETMCCR_TRACESS_SHIFT   26
 
#define _ETM_ETMCIDR0_MASK   0x000000FFUL
 
#define _ETM_ETMCIDR0_PREAMB_DEFAULT   0x0000000DUL
 
#define _ETM_ETMCIDR0_PREAMB_MASK   0xFFUL
 
#define _ETM_ETMCIDR0_PREAMB_SHIFT   0
 
#define _ETM_ETMCIDR0_RESETVALUE   0x0000000DUL
 
#define _ETM_ETMCIDR1_MASK   0x000000FFUL
 
#define _ETM_ETMCIDR1_PREAMB_DEFAULT   0x00000090UL
 
#define _ETM_ETMCIDR1_PREAMB_MASK   0xFFUL
 
#define _ETM_ETMCIDR1_PREAMB_SHIFT   0
 
#define _ETM_ETMCIDR1_RESETVALUE   0x00000090UL
 
#define _ETM_ETMCIDR2_MASK   0x000000FFUL
 
#define _ETM_ETMCIDR2_PREAMB_DEFAULT   0x00000005UL
 
#define _ETM_ETMCIDR2_PREAMB_MASK   0xFFUL
 
#define _ETM_ETMCIDR2_PREAMB_SHIFT   0
 
#define _ETM_ETMCIDR2_RESETVALUE   0x00000005UL
 
#define _ETM_ETMCIDR3_MASK   0x000000FFUL
 
#define _ETM_ETMCIDR3_PREAMB_DEFAULT   0x000000B1UL
 
#define _ETM_ETMCIDR3_PREAMB_MASK   0xFFUL
 
#define _ETM_ETMCIDR3_PREAMB_SHIFT   0
 
#define _ETM_ETMCIDR3_RESETVALUE   0x000000B1UL
 
#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT   0x00000000UL
 
#define _ETM_ETMCLAIMCLR_CLRTAG_MASK   0x1UL
 
#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT   0
 
#define _ETM_ETMCLAIMCLR_MASK   0x00000001UL
 
#define _ETM_ETMCLAIMCLR_RESETVALUE   0x00000000UL
 
#define _ETM_ETMCLAIMSET_MASK   0x000000FFUL
 
#define _ETM_ETMCLAIMSET_RESETVALUE   0x0000000FUL
 
#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT   0x0000000FUL
 
#define _ETM_ETMCLAIMSET_SETTAG_MASK   0xFFUL
 
#define _ETM_ETMCLAIMSET_SETTAG_SHIFT   0
 
#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT   0x00000000UL
 
#define _ETM_ETMCNTRLDVR1_COUNT_MASK   0xFFFFUL
 
#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT   0
 
#define _ETM_ETMCNTRLDVR1_MASK   0x0000FFFFUL
 
#define _ETM_ETMCNTRLDVR1_RESETVALUE   0x00000000UL
 
#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT   0x00000000UL
 
#define _ETM_ETMCR_BRANCHOUTPUT_MASK   0x100UL
 
#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT   8
 
#define _ETM_ETMCR_DBGREQCTRL_DEFAULT   0x00000000UL
 
#define _ETM_ETMCR_DBGREQCTRL_MASK   0x200UL
 
#define _ETM_ETMCR_DBGREQCTRL_SHIFT   9
 
#define _ETM_ETMCR_EPORTSIZE_DEFAULT   0x00000000UL
 
#define _ETM_ETMCR_EPORTSIZE_MASK   0x600000UL
 
#define _ETM_ETMCR_EPORTSIZE_SHIFT   21
 
#define _ETM_ETMCR_ETMPORTSEL_DEFAULT   0x00000000UL
 
#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH   0x00000001UL
 
#define _ETM_ETMCR_ETMPORTSEL_ETMLOW   0x00000000UL
 
#define _ETM_ETMCR_ETMPORTSEL_MASK   0x800UL
 
#define _ETM_ETMCR_ETMPORTSEL_SHIFT   11
 
#define _ETM_ETMCR_ETMPROG_DEFAULT   0x00000001UL
 
#define _ETM_ETMCR_ETMPROG_MASK   0x400UL
 
#define _ETM_ETMCR_ETMPROG_SHIFT   10
 
#define _ETM_ETMCR_MASK   0x10632FF1UL
 
#define _ETM_ETMCR_PORTMODE2_DEFAULT   0x00000000UL
 
#define _ETM_ETMCR_PORTMODE2_MASK   0x2000UL
 
#define _ETM_ETMCR_PORTMODE2_SHIFT   13
 
#define _ETM_ETMCR_PORTMODE_DEFAULT   0x00000000UL
 
#define _ETM_ETMCR_PORTMODE_MASK   0x30000UL
 
#define _ETM_ETMCR_PORTMODE_SHIFT   16
 
#define _ETM_ETMCR_PORTSIZE_DEFAULT   0x00000001UL
 
#define _ETM_ETMCR_PORTSIZE_MASK   0x70UL
 
#define _ETM_ETMCR_PORTSIZE_SHIFT   4
 
#define _ETM_ETMCR_POWERDWN_DEFAULT   0x00000001UL
 
#define _ETM_ETMCR_POWERDWN_MASK   0x1UL
 
#define _ETM_ETMCR_POWERDWN_SHIFT   0
 
#define _ETM_ETMCR_RESETVALUE   0x00000411UL
 
#define _ETM_ETMCR_STALL_DEFAULT   0x00000000UL
 
#define _ETM_ETMCR_STALL_MASK   0x80UL
 
#define _ETM_ETMCR_STALL_SHIFT   7
 
#define _ETM_ETMCR_TSTAMPEN_DEFAULT   0x00000000UL
 
#define _ETM_ETMCR_TSTAMPEN_MASK   0x10000000UL
 
#define _ETM_ETMCR_TSTAMPEN_SHIFT   28
 
#define _ETM_ETMDEVTYPE_MASK   0x000000FFUL
 
#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT   0x00000001UL
 
#define _ETM_ETMDEVTYPE_PROCTRACE_MASK   0xF0UL
 
#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT   4
 
#define _ETM_ETMDEVTYPE_RESETVALUE   0x00000013UL
 
#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT   0x00000003UL
 
#define _ETM_ETMDEVTYPE_TRACESRC_MASK   0xFUL
 
#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT   0
 
#define _ETM_ETMFFLR_BYTENUM_DEFAULT   0x00000000UL
 
#define _ETM_ETMFFLR_BYTENUM_MASK   0xFFUL
 
#define _ETM_ETMFFLR_BYTENUM_SHIFT   0
 
#define _ETM_ETMFFLR_MASK   0x000000FFUL
 
#define _ETM_ETMFFLR_RESETVALUE   0x00000000UL
 
#define _ETM_ETMIDR2_MASK   0x00000003UL
 
#define _ETM_ETMIDR2_RESETVALUE   0x00000000UL
 
#define _ETM_ETMIDR2_RFE_CPSR   0x00000001UL
 
#define _ETM_ETMIDR2_RFE_DEFAULT   0x00000000UL
 
#define _ETM_ETMIDR2_RFE_MASK   0x1UL
 
#define _ETM_ETMIDR2_RFE_PC   0x00000000UL
 
#define _ETM_ETMIDR2_RFE_SHIFT   0
 
#define _ETM_ETMIDR2_SWP_DEFAULT   0x00000000UL
 
#define _ETM_ETMIDR2_SWP_LOAD   0x00000000UL
 
#define _ETM_ETMIDR2_SWP_MASK   0x2UL
 
#define _ETM_ETMIDR2_SWP_SHIFT   1
 
#define _ETM_ETMIDR2_SWP_STORE   0x00000001UL
 
#define _ETM_ETMIDR_BPE_DEFAULT   0x00000001UL
 
#define _ETM_ETMIDR_BPE_MASK   0x100000UL
 
#define _ETM_ETMIDR_BPE_SHIFT   20
 
#define _ETM_ETMIDR_ETMMAJVER_DEFAULT   0x00000002UL
 
#define _ETM_ETMIDR_ETMMAJVER_MASK   0xF00UL
 
#define _ETM_ETMIDR_ETMMAJVER_SHIFT   8
 
#define _ETM_ETMIDR_ETMMINVER_DEFAULT   0x00000005UL
 
#define _ETM_ETMIDR_ETMMINVER_MASK   0xF0UL
 
#define _ETM_ETMIDR_ETMMINVER_SHIFT   4
 
#define _ETM_ETMIDR_IMPCODE_DEFAULT   0x00000041UL
 
#define _ETM_ETMIDR_IMPCODE_MASK   0xFF000000UL
 
#define _ETM_ETMIDR_IMPCODE_SHIFT   24
 
#define _ETM_ETMIDR_IMPVER_DEFAULT   0x00000003UL
 
#define _ETM_ETMIDR_IMPVER_MASK   0xFUL
 
#define _ETM_ETMIDR_IMPVER_SHIFT   0
 
#define _ETM_ETMIDR_LPCF_DEFAULT   0x00000000UL
 
#define _ETM_ETMIDR_LPCF_MASK   0x10000UL
 
#define _ETM_ETMIDR_LPCF_SHIFT   16
 
#define _ETM_ETMIDR_MASK   0xFF1DFFFFUL
 
#define _ETM_ETMIDR_PROCFAM_DEFAULT   0x0000000FUL
 
#define _ETM_ETMIDR_PROCFAM_MASK   0xF000UL
 
#define _ETM_ETMIDR_PROCFAM_SHIFT   12
 
#define _ETM_ETMIDR_RESETVALUE   0x4114F253UL
 
#define _ETM_ETMIDR_SECEXT_DEFAULT   0x00000000UL
 
#define _ETM_ETMIDR_SECEXT_MASK   0x80000UL
 
#define _ETM_ETMIDR_SECEXT_SHIFT   19
 
#define _ETM_ETMIDR_THUMBT_DEFAULT   0x00000001UL
 
#define _ETM_ETMIDR_THUMBT_MASK   0x40000UL
 
#define _ETM_ETMIDR_THUMBT_SHIFT   18
 
#define _ETM_ETMISCIN_COREHALT_DEFAULT   0x00000000UL
 
#define _ETM_ETMISCIN_COREHALT_MASK   0x10UL
 
#define _ETM_ETMISCIN_COREHALT_SHIFT   4
 
#define _ETM_ETMISCIN_EXTIN_DEFAULT   0x00000000UL
 
#define _ETM_ETMISCIN_EXTIN_MASK   0x3UL
 
#define _ETM_ETMISCIN_EXTIN_SHIFT   0
 
#define _ETM_ETMISCIN_MASK   0x00000013UL
 
#define _ETM_ETMISCIN_RESETVALUE   0x00000000UL
 
#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT   0x00000000UL
 
#define _ETM_ETMITATBCTR0_ATVALID_MASK   0x1UL
 
#define _ETM_ETMITATBCTR0_ATVALID_SHIFT   0
 
#define _ETM_ETMITATBCTR0_MASK   0x00000001UL
 
#define _ETM_ETMITATBCTR0_RESETVALUE   0x00000000UL
 
#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT   0x00000001UL
 
#define _ETM_ETMITATBCTR2_ATREADY_MASK   0x1UL
 
#define _ETM_ETMITATBCTR2_ATREADY_SHIFT   0
 
#define _ETM_ETMITATBCTR2_MASK   0x00000001UL
 
#define _ETM_ETMITATBCTR2_RESETVALUE   0x00000001UL
 
#define _ETM_ETMITCTRL_ITEN_DEFAULT   0x00000000UL
 
#define _ETM_ETMITCTRL_ITEN_MASK   0x1UL
 
#define _ETM_ETMITCTRL_ITEN_SHIFT   0
 
#define _ETM_ETMITCTRL_MASK   0x00000001UL
 
#define _ETM_ETMITCTRL_RESETVALUE   0x00000000UL
 
#define _ETM_ETMLAR_KEY_DEFAULT   0x00000000UL
 
#define _ETM_ETMLAR_KEY_MASK   0x1UL
 
#define _ETM_ETMLAR_KEY_SHIFT   0
 
#define _ETM_ETMLAR_MASK   0x00000001UL
 
#define _ETM_ETMLAR_RESETVALUE   0x00000000UL
 
#define _ETM_ETMLSR_LOCKED_DEFAULT   0x00000001UL
 
#define _ETM_ETMLSR_LOCKED_MASK   0x2UL
 
#define _ETM_ETMLSR_LOCKED_SHIFT   1
 
#define _ETM_ETMLSR_LOCKIMP_DEFAULT   0x00000001UL
 
#define _ETM_ETMLSR_LOCKIMP_MASK   0x1UL
 
#define _ETM_ETMLSR_LOCKIMP_SHIFT   0
 
#define _ETM_ETMLSR_MASK   0x00000003UL
 
#define _ETM_ETMLSR_RESETVALUE   0x00000003UL
 
#define _ETM_ETMPDSR_ETMUP_DEFAULT   0x00000001UL
 
#define _ETM_ETMPDSR_ETMUP_MASK   0x1UL
 
#define _ETM_ETMPDSR_ETMUP_SHIFT   0
 
#define _ETM_ETMPDSR_MASK   0x00000001UL
 
#define _ETM_ETMPDSR_RESETVALUE   0x00000001UL
 
#define _ETM_ETMPIDR0_MASK   0x000000FFUL
 
#define _ETM_ETMPIDR0_PARTNUM_DEFAULT   0x00000025UL
 
#define _ETM_ETMPIDR0_PARTNUM_MASK   0xFFUL
 
#define _ETM_ETMPIDR0_PARTNUM_SHIFT   0
 
#define _ETM_ETMPIDR0_RESETVALUE   0x00000025UL
 
#define _ETM_ETMPIDR1_IDCODE_DEFAULT   0x0000000BUL
 
#define _ETM_ETMPIDR1_IDCODE_MASK   0xF0UL
 
#define _ETM_ETMPIDR1_IDCODE_SHIFT   4
 
#define _ETM_ETMPIDR1_MASK   0x000000FFUL
 
#define _ETM_ETMPIDR1_PARTNUM_DEFAULT   0x00000009UL
 
#define _ETM_ETMPIDR1_PARTNUM_MASK   0xFUL
 
#define _ETM_ETMPIDR1_PARTNUM_SHIFT   0
 
#define _ETM_ETMPIDR1_RESETVALUE   0x000000B9UL
 
#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT   0x00000001UL
 
#define _ETM_ETMPIDR2_ALWAYS1_MASK   0x8UL
 
#define _ETM_ETMPIDR2_ALWAYS1_SHIFT   3
 
#define _ETM_ETMPIDR2_IDCODE_DEFAULT   0x00000003UL
 
#define _ETM_ETMPIDR2_IDCODE_MASK   0x7UL
 
#define _ETM_ETMPIDR2_IDCODE_SHIFT   0
 
#define _ETM_ETMPIDR2_MASK   0x000000FFUL
 
#define _ETM_ETMPIDR2_RESETVALUE   0x0000000BUL
 
#define _ETM_ETMPIDR2_REV_DEFAULT   0x00000000UL
 
#define _ETM_ETMPIDR2_REV_MASK   0xF0UL
 
#define _ETM_ETMPIDR2_REV_SHIFT   4
 
#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT   0x00000000UL
 
#define _ETM_ETMPIDR3_CUSTMOD_MASK   0xFUL
 
#define _ETM_ETMPIDR3_CUSTMOD_SHIFT   0
 
#define _ETM_ETMPIDR3_MASK   0x000000FFUL
 
#define _ETM_ETMPIDR3_RESETVALUE   0x00000000UL
 
#define _ETM_ETMPIDR3_REVAND_DEFAULT   0x00000000UL
 
#define _ETM_ETMPIDR3_REVAND_MASK   0xF0UL
 
#define _ETM_ETMPIDR3_REVAND_SHIFT   4
 
#define _ETM_ETMPIDR4_CONTCODE_DEFAULT   0x00000004UL
 
#define _ETM_ETMPIDR4_CONTCODE_MASK   0xFUL
 
#define _ETM_ETMPIDR4_CONTCODE_SHIFT   0
 
#define _ETM_ETMPIDR4_COUNT_DEFAULT   0x00000000UL
 
#define _ETM_ETMPIDR4_COUNT_MASK   0xF0UL
 
#define _ETM_ETMPIDR4_COUNT_SHIFT   4
 
#define _ETM_ETMPIDR4_MASK   0x000000FFUL
 
#define _ETM_ETMPIDR4_RESETVALUE   0x00000004UL
 
#define _ETM_ETMPIDR5_MASK   0x00000000UL
 
#define _ETM_ETMPIDR5_RESETVALUE   0x00000000UL
 
#define _ETM_ETMPIDR6_MASK   0x00000000UL
 
#define _ETM_ETMPIDR6_RESETVALUE   0x00000000UL
 
#define _ETM_ETMPIDR7_MASK   0x00000000UL
 
#define _ETM_ETMPIDR7_RESETVALUE   0x00000000UL
 
#define _ETM_ETMSCR_FIFOFULL_DEFAULT   0x00000001UL
 
#define _ETM_ETMSCR_FIFOFULL_MASK   0x100UL
 
#define _ETM_ETMSCR_FIFOFULL_SHIFT   8
 
#define _ETM_ETMSCR_MASK   0x00027F0FUL
 
#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT   0x00000000UL
 
#define _ETM_ETMSCR_MAXPORTSIZE3_MASK   0x200UL
 
#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT   9
 
#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT   0x00000001UL
 
#define _ETM_ETMSCR_MAXPORTSIZE_MASK   0x7UL
 
#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT   0
 
#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT   0x00000001UL
 
#define _ETM_ETMSCR_NOFETCHCOMP_MASK   0x20000UL
 
#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT   17
 
#define _ETM_ETMSCR_PORTMODE_DEFAULT   0x00000001UL
 
#define _ETM_ETMSCR_PORTMODE_MASK   0x800UL
 
#define _ETM_ETMSCR_PORTMODE_SHIFT   11
 
#define _ETM_ETMSCR_PORTSIZE_DEFAULT   0x00000001UL
 
#define _ETM_ETMSCR_PORTSIZE_MASK   0x400UL
 
#define _ETM_ETMSCR_PORTSIZE_SHIFT   10
 
#define _ETM_ETMSCR_PROCNUM_DEFAULT   0x00000000UL
 
#define _ETM_ETMSCR_PROCNUM_MASK   0x7000UL
 
#define _ETM_ETMSCR_PROCNUM_SHIFT   12
 
#define _ETM_ETMSCR_RESETVALUE   0x00020D09UL
 
#define _ETM_ETMSR_ETHOF_DEFAULT   0x00000000UL
 
#define _ETM_ETMSR_ETHOF_MASK   0x1UL
 
#define _ETM_ETMSR_ETHOF_SHIFT   0
 
#define _ETM_ETMSR_ETMPROGBIT_DEFAULT   0x00000001UL
 
#define _ETM_ETMSR_ETMPROGBIT_MASK   0x2UL
 
#define _ETM_ETMSR_ETMPROGBIT_SHIFT   1
 
#define _ETM_ETMSR_MASK   0x0000000FUL
 
#define _ETM_ETMSR_RESETVALUE   0x00000002UL
 
#define _ETM_ETMSR_TRACESTAT_DEFAULT   0x00000000UL
 
#define _ETM_ETMSR_TRACESTAT_MASK   0x4UL
 
#define _ETM_ETMSR_TRACESTAT_SHIFT   2
 
#define _ETM_ETMSR_TRIGBIT_DEFAULT   0x00000000UL
 
#define _ETM_ETMSR_TRIGBIT_MASK   0x8UL
 
#define _ETM_ETMSR_TRIGBIT_SHIFT   3
 
#define _ETM_ETMSYNCFR_FREQ_DEFAULT   0x00000400UL
 
#define _ETM_ETMSYNCFR_FREQ_MASK   0xFFFUL
 
#define _ETM_ETMSYNCFR_FREQ_SHIFT   0
 
#define _ETM_ETMSYNCFR_MASK   0x00000FFFUL
 
#define _ETM_ETMSYNCFR_RESETVALUE   0x00000400UL
 
#define _ETM_ETMTECR1_ADRCMP_DEFAULT   0x00000000UL
 
#define _ETM_ETMTECR1_ADRCMP_MASK   0xFFUL
 
#define _ETM_ETMTECR1_ADRCMP_SHIFT   0
 
#define _ETM_ETMTECR1_INCEXCTL_DEFAULT   0x00000000UL
 
#define _ETM_ETMTECR1_INCEXCTL_EXC   0x00000001UL
 
#define _ETM_ETMTECR1_INCEXCTL_INC   0x00000000UL
 
#define _ETM_ETMTECR1_INCEXCTL_MASK   0x1000000UL
 
#define _ETM_ETMTECR1_INCEXCTL_SHIFT   24
 
#define _ETM_ETMTECR1_MASK   0x03FFFFFFUL
 
#define _ETM_ETMTECR1_MEMMAP_DEFAULT   0x00000000UL
 
#define _ETM_ETMTECR1_MEMMAP_MASK   0xFFFF00UL
 
#define _ETM_ETMTECR1_MEMMAP_SHIFT   8
 
#define _ETM_ETMTECR1_RESETVALUE   0x00000000UL
 
#define _ETM_ETMTECR1_TCE_DEFAULT   0x00000000UL
 
#define _ETM_ETMTECR1_TCE_DIS   0x00000001UL
 
#define _ETM_ETMTECR1_TCE_EN   0x00000000UL
 
#define _ETM_ETMTECR1_TCE_MASK   0x2000000UL
 
#define _ETM_ETMTECR1_TCE_SHIFT   25
 
#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT   0x00000000UL
 
#define _ETM_ETMTEEVR_ETMFCNEN_MASK   0x1C000UL
 
#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT   14
 
#define _ETM_ETMTEEVR_MASK   0x0001FFFFUL
 
#define _ETM_ETMTEEVR_RESA_DEFAULT   0x00000000UL
 
#define _ETM_ETMTEEVR_RESA_MASK   0x7FUL
 
#define _ETM_ETMTEEVR_RESA_SHIFT   0
 
#define _ETM_ETMTEEVR_RESB_DEFAULT   0x00000000UL
 
#define _ETM_ETMTEEVR_RESB_MASK   0x3F80UL
 
#define _ETM_ETMTEEVR_RESB_SHIFT   7
 
#define _ETM_ETMTEEVR_RESETVALUE   0x00000000UL
 
#define _ETM_ETMTESSEICR_MASK   0x000F000FUL
 
#define _ETM_ETMTESSEICR_RESETVALUE   0x00000000UL
 
#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT   0x00000000UL
 
#define _ETM_ETMTESSEICR_STARTRSEL_MASK   0xFUL
 
#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT   0
 
#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT   0x00000000UL
 
#define _ETM_ETMTESSEICR_STOPRSEL_MASK   0xF0000UL
 
#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT   16
 
#define _ETM_ETMTRACEIDR_MASK   0x0000007FUL
 
#define _ETM_ETMTRACEIDR_RESETVALUE   0x00000000UL
 
#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT   0x00000000UL
 
#define _ETM_ETMTRACEIDR_TRACEID_MASK   0x7FUL
 
#define _ETM_ETMTRACEIDR_TRACEID_SHIFT   0
 
#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT   0x00000000UL
 
#define _ETM_ETMTRIGGER_ETMFCN_MASK   0x1C000UL
 
#define _ETM_ETMTRIGGER_ETMFCN_SHIFT   14
 
#define _ETM_ETMTRIGGER_MASK   0x0001FFFFUL
 
#define _ETM_ETMTRIGGER_RESA_DEFAULT   0x00000000UL
 
#define _ETM_ETMTRIGGER_RESA_MASK   0x7FUL
 
#define _ETM_ETMTRIGGER_RESA_SHIFT   0
 
#define _ETM_ETMTRIGGER_RESB_DEFAULT   0x00000000UL
 
#define _ETM_ETMTRIGGER_RESB_MASK   0x3F80UL
 
#define _ETM_ETMTRIGGER_RESB_SHIFT   7
 
#define _ETM_ETMTRIGGER_RESETVALUE   0x00000000UL
 
#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT   0x00000000UL
 
#define _ETM_ETMTSEVR_ETMFCNEVT_MASK   0x1C000UL
 
#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT   14
 
#define _ETM_ETMTSEVR_MASK   0x0001FFFFUL
 
#define _ETM_ETMTSEVR_RESAEVT_DEFAULT   0x00000000UL
 
#define _ETM_ETMTSEVR_RESAEVT_MASK   0x7FUL
 
#define _ETM_ETMTSEVR_RESAEVT_SHIFT   0
 
#define _ETM_ETMTSEVR_RESBEVT_DEFAULT   0x00000000UL
 
#define _ETM_ETMTSEVR_RESBEVT_MASK   0x3F80UL
 
#define _ETM_ETMTSEVR_RESBEVT_SHIFT   7
 
#define _ETM_ETMTSEVR_RESETVALUE   0x00000000UL
 
#define _ETM_ITTRIGOUT_MASK   0x00000001UL
 
#define _ETM_ITTRIGOUT_RESETVALUE   0x00000000UL
 
#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT   0x00000000UL
 
#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK   0x1UL
 
#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT   0
 
#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT   (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0)
 
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT   (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2)
 
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE   (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2)
 
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE   (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2)
 
#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT   (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4)
 
#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT   (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6)
 
#define ETM_ETMCCER_DADDRCMP   (0x1UL << 12)
 
#define ETM_ETMCCER_DADDRCMP_DEFAULT   (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12)
 
#define ETM_ETMCCER_EICEIMP   (0x1UL << 21)
 
#define ETM_ETMCCER_EICEIMP_DEFAULT   (_ETM_ETMCCER_EICEIMP_DEFAULT << 21)
 
#define ETM_ETMCCER_EICEWPNT_DEFAULT   (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16)
 
#define ETM_ETMCCER_EXTINPBUS_DEFAULT   (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3)
 
#define ETM_ETMCCER_EXTINPSEL_DEFAULT   (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0)
 
#define ETM_ETMCCER_INSTRES_DEFAULT   (_ETM_ETMCCER_INSTRES_DEFAULT << 13)
 
#define ETM_ETMCCER_READREGS   (0x1UL << 11)
 
#define ETM_ETMCCER_READREGS_DEFAULT   (_ETM_ETMCCER_READREGS_DEFAULT << 11)
 
#define ETM_ETMCCER_RFCNT   (0x1UL << 27)
 
#define ETM_ETMCCER_RFCNT_DEFAULT   (_ETM_ETMCCER_RFCNT_DEFAULT << 27)
 
#define ETM_ETMCCER_TEICEWPNT   (0x1UL << 20)
 
#define ETM_ETMCCER_TEICEWPNT_DEFAULT   (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20)
 
#define ETM_ETMCCER_TENC   (0x1UL << 28)
 
#define ETM_ETMCCER_TENC_DEFAULT   (_ETM_ETMCCER_TENC_DEFAULT << 28)
 
#define ETM_ETMCCER_TIMP   (0x1UL << 22)
 
#define ETM_ETMCCER_TIMP_DEFAULT   (_ETM_ETMCCER_TIMP_DEFAULT << 22)
 
#define ETM_ETMCCER_TSIZE   (0x1UL << 29)
 
#define ETM_ETMCCER_TSIZE_DEFAULT   (_ETM_ETMCCER_TSIZE_DEFAULT << 29)
 
#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT   (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0)
 
#define ETM_ETMCCR_COUNTNUM_DEFAULT   (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13)
 
#define ETM_ETMCCR_DATACMPNUM_DEFAULT   (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4)
 
#define ETM_ETMCCR_ETMID   (0x1UL << 31)
 
#define ETM_ETMCCR_ETMID_DEFAULT   (_ETM_ETMCCR_ETMID_DEFAULT << 31)
 
#define ETM_ETMCCR_EXTINPNUM_DEFAULT   (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17)
 
#define ETM_ETMCCR_EXTINPNUM_ONE   (_ETM_ETMCCR_EXTINPNUM_ONE << 17)
 
#define ETM_ETMCCR_EXTINPNUM_TWO   (_ETM_ETMCCR_EXTINPNUM_TWO << 17)
 
#define ETM_ETMCCR_EXTINPNUM_ZERO   (_ETM_ETMCCR_EXTINPNUM_ZERO << 17)
 
#define ETM_ETMCCR_EXTOUTNUM_DEFAULT   (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20)
 
#define ETM_ETMCCR_FIFOFULLPRES   (0x1UL << 23)
 
#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT   (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23)
 
#define ETM_ETMCCR_IDCOMPNUM_DEFAULT   (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24)
 
#define ETM_ETMCCR_MMACCESS   (0x1UL << 27)
 
#define ETM_ETMCCR_MMACCESS_DEFAULT   (_ETM_ETMCCR_MMACCESS_DEFAULT << 27)
 
#define ETM_ETMCCR_MMDECCNT_DEFAULT   (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8)
 
#define ETM_ETMCCR_SEQPRES   (0x1UL << 16)
 
#define ETM_ETMCCR_SEQPRES_DEFAULT   (_ETM_ETMCCR_SEQPRES_DEFAULT << 16)
 
#define ETM_ETMCCR_TRACESS   (0x1UL << 26)
 
#define ETM_ETMCCR_TRACESS_DEFAULT   (_ETM_ETMCCR_TRACESS_DEFAULT << 26)
 
#define ETM_ETMCIDR0_PREAMB_DEFAULT   (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0)
 
#define ETM_ETMCIDR1_PREAMB_DEFAULT   (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0)
 
#define ETM_ETMCIDR2_PREAMB_DEFAULT   (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0)
 
#define ETM_ETMCIDR3_PREAMB_DEFAULT   (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0)
 
#define ETM_ETMCLAIMCLR_CLRTAG   (0x1UL << 0)
 
#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT   (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0)
 
#define ETM_ETMCLAIMSET_SETTAG_DEFAULT   (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0)
 
#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT   (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0)
 
#define ETM_ETMCR_BRANCHOUTPUT   (0x1UL << 8)
 
#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT   (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8)
 
#define ETM_ETMCR_DBGREQCTRL   (0x1UL << 9)
 
#define ETM_ETMCR_DBGREQCTRL_DEFAULT   (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9)
 
#define ETM_ETMCR_EPORTSIZE_DEFAULT   (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21)
 
#define ETM_ETMCR_ETMPORTSEL   (0x1UL << 11)
 
#define ETM_ETMCR_ETMPORTSEL_DEFAULT   (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11)
 
#define ETM_ETMCR_ETMPORTSEL_ETMHIGH   (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11)
 
#define ETM_ETMCR_ETMPORTSEL_ETMLOW   (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11)
 
#define ETM_ETMCR_ETMPROG   (0x1UL << 10)
 
#define ETM_ETMCR_ETMPROG_DEFAULT   (_ETM_ETMCR_ETMPROG_DEFAULT << 10)
 
#define ETM_ETMCR_PORTMODE2   (0x1UL << 13)
 
#define ETM_ETMCR_PORTMODE2_DEFAULT   (_ETM_ETMCR_PORTMODE2_DEFAULT << 13)
 
#define ETM_ETMCR_PORTMODE_DEFAULT   (_ETM_ETMCR_PORTMODE_DEFAULT << 16)
 
#define ETM_ETMCR_PORTSIZE_DEFAULT   (_ETM_ETMCR_PORTSIZE_DEFAULT << 4)
 
#define ETM_ETMCR_POWERDWN   (0x1UL << 0)
 
#define ETM_ETMCR_POWERDWN_DEFAULT   (_ETM_ETMCR_POWERDWN_DEFAULT << 0)
 
#define ETM_ETMCR_STALL   (0x1UL << 7)
 
#define ETM_ETMCR_STALL_DEFAULT   (_ETM_ETMCR_STALL_DEFAULT << 7)
 
#define ETM_ETMCR_TSTAMPEN   (0x1UL << 28)
 
#define ETM_ETMCR_TSTAMPEN_DEFAULT   (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28)
 
#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT   (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4)
 
#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT   (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0)
 
#define ETM_ETMFFLR_BYTENUM_DEFAULT   (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0)
 
#define ETM_ETMIDR2_RFE   (0x1UL << 0)
 
#define ETM_ETMIDR2_RFE_CPSR   (_ETM_ETMIDR2_RFE_CPSR << 0)
 
#define ETM_ETMIDR2_RFE_DEFAULT   (_ETM_ETMIDR2_RFE_DEFAULT << 0)
 
#define ETM_ETMIDR2_RFE_PC   (_ETM_ETMIDR2_RFE_PC << 0)
 
#define ETM_ETMIDR2_SWP   (0x1UL << 1)
 
#define ETM_ETMIDR2_SWP_DEFAULT   (_ETM_ETMIDR2_SWP_DEFAULT << 1)
 
#define ETM_ETMIDR2_SWP_LOAD   (_ETM_ETMIDR2_SWP_LOAD << 1)
 
#define ETM_ETMIDR2_SWP_STORE   (_ETM_ETMIDR2_SWP_STORE << 1)
 
#define ETM_ETMIDR_BPE   (0x1UL << 20)
 
#define ETM_ETMIDR_BPE_DEFAULT   (_ETM_ETMIDR_BPE_DEFAULT << 20)
 
#define ETM_ETMIDR_ETMMAJVER_DEFAULT   (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8)
 
#define ETM_ETMIDR_ETMMINVER_DEFAULT   (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4)
 
#define ETM_ETMIDR_IMPCODE_DEFAULT   (_ETM_ETMIDR_IMPCODE_DEFAULT << 24)
 
#define ETM_ETMIDR_IMPVER_DEFAULT   (_ETM_ETMIDR_IMPVER_DEFAULT << 0)
 
#define ETM_ETMIDR_LPCF   (0x1UL << 16)
 
#define ETM_ETMIDR_LPCF_DEFAULT   (_ETM_ETMIDR_LPCF_DEFAULT << 16)
 
#define ETM_ETMIDR_PROCFAM_DEFAULT   (_ETM_ETMIDR_PROCFAM_DEFAULT << 12)
 
#define ETM_ETMIDR_SECEXT   (0x1UL << 19)
 
#define ETM_ETMIDR_SECEXT_DEFAULT   (_ETM_ETMIDR_SECEXT_DEFAULT << 19)
 
#define ETM_ETMIDR_THUMBT   (0x1UL << 18)
 
#define ETM_ETMIDR_THUMBT_DEFAULT   (_ETM_ETMIDR_THUMBT_DEFAULT << 18)
 
#define ETM_ETMISCIN_COREHALT   (0x1UL << 4)
 
#define ETM_ETMISCIN_COREHALT_DEFAULT   (_ETM_ETMISCIN_COREHALT_DEFAULT << 4)
 
#define ETM_ETMISCIN_EXTIN_DEFAULT   (_ETM_ETMISCIN_EXTIN_DEFAULT << 0)
 
#define ETM_ETMITATBCTR0_ATVALID   (0x1UL << 0)
 
#define ETM_ETMITATBCTR0_ATVALID_DEFAULT   (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0)
 
#define ETM_ETMITATBCTR2_ATREADY   (0x1UL << 0)
 
#define ETM_ETMITATBCTR2_ATREADY_DEFAULT   (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0)
 
#define ETM_ETMITCTRL_ITEN   (0x1UL << 0)
 
#define ETM_ETMITCTRL_ITEN_DEFAULT   (_ETM_ETMITCTRL_ITEN_DEFAULT << 0)
 
#define ETM_ETMLAR_KEY   (0x1UL << 0)
 
#define ETM_ETMLAR_KEY_DEFAULT   (_ETM_ETMLAR_KEY_DEFAULT << 0)
 
#define ETM_ETMLSR_LOCKED   (0x1UL << 1)
 
#define ETM_ETMLSR_LOCKED_DEFAULT   (_ETM_ETMLSR_LOCKED_DEFAULT << 1)
 
#define ETM_ETMLSR_LOCKIMP   (0x1UL << 0)
 
#define ETM_ETMLSR_LOCKIMP_DEFAULT   (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0)
 
#define ETM_ETMPDSR_ETMUP   (0x1UL << 0)
 
#define ETM_ETMPDSR_ETMUP_DEFAULT   (_ETM_ETMPDSR_ETMUP_DEFAULT << 0)
 
#define ETM_ETMPIDR0_PARTNUM_DEFAULT   (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0)
 
#define ETM_ETMPIDR1_IDCODE_DEFAULT   (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4)
 
#define ETM_ETMPIDR1_PARTNUM_DEFAULT   (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0)
 
#define ETM_ETMPIDR2_ALWAYS1   (0x1UL << 3)
 
#define ETM_ETMPIDR2_ALWAYS1_DEFAULT   (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3)
 
#define ETM_ETMPIDR2_IDCODE_DEFAULT   (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0)
 
#define ETM_ETMPIDR2_REV_DEFAULT   (_ETM_ETMPIDR2_REV_DEFAULT << 4)
 
#define ETM_ETMPIDR3_CUSTMOD_DEFAULT   (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0)
 
#define ETM_ETMPIDR3_REVAND_DEFAULT   (_ETM_ETMPIDR3_REVAND_DEFAULT << 4)
 
#define ETM_ETMPIDR4_CONTCODE_DEFAULT   (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0)
 
#define ETM_ETMPIDR4_COUNT_DEFAULT   (_ETM_ETMPIDR4_COUNT_DEFAULT << 4)
 
#define ETM_ETMSCR_FIFOFULL   (0x1UL << 8)
 
#define ETM_ETMSCR_FIFOFULL_DEFAULT   (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8)
 
#define ETM_ETMSCR_MAXPORTSIZE3   (0x1UL << 9)
 
#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT   (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9)
 
#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT   (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0)
 
#define ETM_ETMSCR_NOFETCHCOMP   (0x1UL << 17)
 
#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT   (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17)
 
#define ETM_ETMSCR_PORTMODE   (0x1UL << 11)
 
#define ETM_ETMSCR_PORTMODE_DEFAULT   (_ETM_ETMSCR_PORTMODE_DEFAULT << 11)
 
#define ETM_ETMSCR_PORTSIZE   (0x1UL << 10)
 
#define ETM_ETMSCR_PORTSIZE_DEFAULT   (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10)
 
#define ETM_ETMSCR_PROCNUM_DEFAULT   (_ETM_ETMSCR_PROCNUM_DEFAULT << 12)
 
#define ETM_ETMSR_ETHOF   (0x1UL << 0)
 
#define ETM_ETMSR_ETHOF_DEFAULT   (_ETM_ETMSR_ETHOF_DEFAULT << 0)
 
#define ETM_ETMSR_ETMPROGBIT   (0x1UL << 1)
 
#define ETM_ETMSR_ETMPROGBIT_DEFAULT   (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1)
 
#define ETM_ETMSR_TRACESTAT   (0x1UL << 2)
 
#define ETM_ETMSR_TRACESTAT_DEFAULT   (_ETM_ETMSR_TRACESTAT_DEFAULT << 2)
 
#define ETM_ETMSR_TRIGBIT   (0x1UL << 3)
 
#define ETM_ETMSR_TRIGBIT_DEFAULT   (_ETM_ETMSR_TRIGBIT_DEFAULT << 3)
 
#define ETM_ETMSYNCFR_FREQ_DEFAULT   (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0)
 
#define ETM_ETMTECR1_ADRCMP_DEFAULT   (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0)
 
#define ETM_ETMTECR1_INCEXCTL   (0x1UL << 24)
 
#define ETM_ETMTECR1_INCEXCTL_DEFAULT   (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24)
 
#define ETM_ETMTECR1_INCEXCTL_EXC   (_ETM_ETMTECR1_INCEXCTL_EXC << 24)
 
#define ETM_ETMTECR1_INCEXCTL_INC   (_ETM_ETMTECR1_INCEXCTL_INC << 24)
 
#define ETM_ETMTECR1_MEMMAP_DEFAULT   (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8)
 
#define ETM_ETMTECR1_TCE   (0x1UL << 25)
 
#define ETM_ETMTECR1_TCE_DEFAULT   (_ETM_ETMTECR1_TCE_DEFAULT << 25)
 
#define ETM_ETMTECR1_TCE_DIS   (_ETM_ETMTECR1_TCE_DIS << 25)
 
#define ETM_ETMTECR1_TCE_EN   (_ETM_ETMTECR1_TCE_EN << 25)
 
#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT   (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14)
 
#define ETM_ETMTEEVR_RESA_DEFAULT   (_ETM_ETMTEEVR_RESA_DEFAULT << 0)
 
#define ETM_ETMTEEVR_RESB_DEFAULT   (_ETM_ETMTEEVR_RESB_DEFAULT << 7)
 
#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT   (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0)
 
#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT   (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16)
 
#define ETM_ETMTRACEIDR_TRACEID_DEFAULT   (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0)
 
#define ETM_ETMTRIGGER_ETMFCN_DEFAULT   (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14)
 
#define ETM_ETMTRIGGER_RESA_DEFAULT   (_ETM_ETMTRIGGER_RESA_DEFAULT << 0)
 
#define ETM_ETMTRIGGER_RESB_DEFAULT   (_ETM_ETMTRIGGER_RESB_DEFAULT << 7)
 
#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT   (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14)
 
#define ETM_ETMTSEVR_RESAEVT_DEFAULT   (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0)
 
#define ETM_ETMTSEVR_RESBEVT_DEFAULT   (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7)
 
#define ETM_ITTRIGOUT_TRIGGEROUT   (0x1UL << 0)
 
#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT   (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0)
 

Macro Definition Documentation

#define _ETM_ETMAUTHSTATUS_MASK   0x000000FFUL

Mask for ETM_ETMAUTHSTATUS

Definition at line 640 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMAUTHSTATUS

Definition at line 643 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK   0x3UL

Bit mask for ETM_NONSECINVDBG

Definition at line 642 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT   0

Shift value for ETM_NONSECINVDBG

Definition at line 641 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMAUTHSTATUS

Definition at line 647 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE   0x00000002UL

Mode DISABLE for ETM_ETMAUTHSTATUS

Definition at line 648 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE   0x00000003UL

Mode ENABLE for ETM_ETMAUTHSTATUS

Definition at line 649 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK   0xCUL

Bit mask for ETM_NONSECNONINVDBG

Definition at line 646 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT   2

Shift value for ETM_NONSECNONINVDBG

Definition at line 645 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_RESETVALUE   0x000000C0UL

Default value for ETM_ETMAUTHSTATUS

Definition at line 639 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMAUTHSTATUS

Definition at line 655 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK   0x30UL

Bit mask for ETM_SECINVDBG

Definition at line 654 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT   4

Shift value for ETM_SECINVDBG

Definition at line 653 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT   0x00000003UL

Mode DEFAULT for ETM_ETMAUTHSTATUS

Definition at line 659 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK   0xC0UL

Bit mask for ETM_SECNONINVDBG

Definition at line 658 of file efm32jg12b_etm.h.

#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT   6

Shift value for ETM_SECNONINVDBG

Definition at line 657 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_DADDRCMP_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 441 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_DADDRCMP_MASK   0x1000UL

Bit mask for ETM_DADDRCMP

Definition at line 440 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_DADDRCMP_SHIFT   12

Shift value for ETM_DADDRCMP

Definition at line 439 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EICEIMP_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 459 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EICEIMP_MASK   0x200000UL

Bit mask for ETM_EICEIMP

Definition at line 458 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EICEIMP_SHIFT   21

Shift value for ETM_EICEIMP

Definition at line 457 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EICEWPNT_DEFAULT   0x00000004UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 449 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EICEWPNT_MASK   0xF0000UL

Bit mask for ETM_EICEWPNT

Definition at line 448 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EICEWPNT_SHIFT   16

Shift value for ETM_EICEWPNT

Definition at line 447 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EXTINPBUS_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 431 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EXTINPBUS_MASK   0x7F8UL

Bit mask for ETM_EXTINPBUS

Definition at line 430 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EXTINPBUS_SHIFT   3

Shift value for ETM_EXTINPBUS

Definition at line 429 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EXTINPSEL_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 427 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EXTINPSEL_MASK   0x3UL

Bit mask for ETM_EXTINPSEL

Definition at line 426 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_EXTINPSEL_SHIFT   0

Shift value for ETM_EXTINPSEL

Definition at line 425 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_INSTRES_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 445 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_INSTRES_MASK   0xE000UL

Bit mask for ETM_INSTRES

Definition at line 444 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_INSTRES_SHIFT   13

Shift value for ETM_INSTRES

Definition at line 443 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_MASK   0x387FFFFBUL

Mask for ETM_ETMCCER

Definition at line 424 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_READREGS_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 436 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_READREGS_MASK   0x800UL

Bit mask for ETM_READREGS

Definition at line 435 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_READREGS_SHIFT   11

Shift value for ETM_READREGS

Definition at line 434 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_RESETVALUE   0x18541800UL

Default value for ETM_ETMCCER

Definition at line 423 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_RFCNT_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 469 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_RFCNT_MASK   0x8000000UL

Bit mask for ETM_RFCNT

Definition at line 468 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_RFCNT_SHIFT   27

Shift value for ETM_RFCNT

Definition at line 467 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TEICEWPNT_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 454 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TEICEWPNT_MASK   0x100000UL

Bit mask for ETM_TEICEWPNT

Definition at line 453 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TEICEWPNT_SHIFT   20

Shift value for ETM_TEICEWPNT

Definition at line 452 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TENC_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 474 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TENC_MASK   0x10000000UL

Bit mask for ETM_TENC

Definition at line 473 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TENC_SHIFT   28

Shift value for ETM_TENC

Definition at line 472 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TIMP_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 464 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TIMP_MASK   0x400000UL

Bit mask for ETM_TIMP

Definition at line 463 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TIMP_SHIFT   22

Shift value for ETM_TIMP

Definition at line 462 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TSIZE_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCER

Definition at line 479 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TSIZE_MASK   0x20000000UL

Bit mask for ETM_TSIZE

Definition at line 478 of file efm32jg12b_etm.h.

#define _ETM_ETMCCER_TSIZE_SHIFT   29

Shift value for ETM_TSIZE

Definition at line 477 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 173 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_ADRCMPPAIR_MASK   0xFUL

Bit mask for ETM_ADRCMPPAIR

Definition at line 172 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT   0

Shift value for ETM_ADRCMPPAIR

Definition at line 171 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_COUNTNUM_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 185 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_COUNTNUM_MASK   0xE000UL

Bit mask for ETM_COUNTNUM

Definition at line 184 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_COUNTNUM_SHIFT   13

Shift value for ETM_COUNTNUM

Definition at line 183 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_DATACMPNUM_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 177 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_DATACMPNUM_MASK   0xF0UL

Bit mask for ETM_DATACMPNUM

Definition at line 176 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_DATACMPNUM_SHIFT   4

Shift value for ETM_DATACMPNUM

Definition at line 175 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_ETMID_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 228 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_ETMID_MASK   0x80000000UL

Bit mask for ETM_ETMID

Definition at line 227 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_ETMID_SHIFT   31

Shift value for ETM_ETMID

Definition at line 226 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_EXTINPNUM_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 194 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_EXTINPNUM_MASK   0xE0000UL

Bit mask for ETM_EXTINPNUM

Definition at line 193 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_EXTINPNUM_ONE   0x00000001UL

Mode ONE for ETM_ETMCCR

Definition at line 196 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_EXTINPNUM_SHIFT   17

Shift value for ETM_EXTINPNUM

Definition at line 192 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_EXTINPNUM_TWO   0x00000002UL

Mode TWO for ETM_ETMCCR

Definition at line 197 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_EXTINPNUM_ZERO   0x00000000UL

Mode ZERO for ETM_ETMCCR

Definition at line 195 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 204 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_EXTOUTNUM_MASK   0x700000UL

Bit mask for ETM_EXTOUTNUM

Definition at line 203 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_EXTOUTNUM_SHIFT   20

Shift value for ETM_EXTOUTNUM

Definition at line 202 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 209 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_FIFOFULLPRES_MASK   0x800000UL

Bit mask for ETM_FIFOFULLPRES

Definition at line 208 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT   23

Shift value for ETM_FIFOFULLPRES

Definition at line 207 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 213 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_IDCOMPNUM_MASK   0x3000000UL

Bit mask for ETM_IDCOMPNUM

Definition at line 212 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_IDCOMPNUM_SHIFT   24

Shift value for ETM_IDCOMPNUM

Definition at line 211 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_MASK   0x8FFFFFFFUL

Mask for ETM_ETMCCR

Definition at line 170 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_MMACCESS_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 223 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_MMACCESS_MASK   0x8000000UL

Bit mask for ETM_MMACCESS

Definition at line 222 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_MMACCESS_SHIFT   27

Shift value for ETM_MMACCESS

Definition at line 221 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_MMDECCNT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 181 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_MMDECCNT_MASK   0x1F00UL

Bit mask for ETM_MMDECCNT

Definition at line 180 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_MMDECCNT_SHIFT   8

Shift value for ETM_MMDECCNT

Definition at line 179 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_RESETVALUE   0x8C802000UL

Default value for ETM_ETMCCR

Definition at line 169 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_SEQPRES_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 190 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_SEQPRES_MASK   0x10000UL

Bit mask for ETM_SEQPRES

Definition at line 189 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_SEQPRES_SHIFT   16

Shift value for ETM_SEQPRES

Definition at line 188 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_TRACESS_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCCR

Definition at line 218 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_TRACESS_MASK   0x4000000UL

Bit mask for ETM_TRACESS

Definition at line 217 of file efm32jg12b_etm.h.

#define _ETM_ETMCCR_TRACESS_SHIFT   26

Shift value for ETM_TRACESS

Definition at line 216 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR0_MASK   0x000000FFUL

Mask for ETM_ETMCIDR0

Definition at line 749 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR0_PREAMB_DEFAULT   0x0000000DUL

Mode DEFAULT for ETM_ETMCIDR0

Definition at line 752 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR0_PREAMB_MASK   0xFFUL

Bit mask for ETM_PREAMB

Definition at line 751 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR0_PREAMB_SHIFT   0

Shift value for ETM_PREAMB

Definition at line 750 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR0_RESETVALUE   0x0000000DUL

Default value for ETM_ETMCIDR0

Definition at line 748 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR1_MASK   0x000000FFUL

Mask for ETM_ETMCIDR1

Definition at line 757 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR1_PREAMB_DEFAULT   0x00000090UL

Mode DEFAULT for ETM_ETMCIDR1

Definition at line 760 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR1_PREAMB_MASK   0xFFUL

Bit mask for ETM_PREAMB

Definition at line 759 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR1_PREAMB_SHIFT   0

Shift value for ETM_PREAMB

Definition at line 758 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR1_RESETVALUE   0x00000090UL

Default value for ETM_ETMCIDR1

Definition at line 756 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR2_MASK   0x000000FFUL

Mask for ETM_ETMCIDR2

Definition at line 765 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR2_PREAMB_DEFAULT   0x00000005UL

Mode DEFAULT for ETM_ETMCIDR2

Definition at line 768 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR2_PREAMB_MASK   0xFFUL

Bit mask for ETM_PREAMB

Definition at line 767 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR2_PREAMB_SHIFT   0

Shift value for ETM_PREAMB

Definition at line 766 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR2_RESETVALUE   0x00000005UL

Default value for ETM_ETMCIDR2

Definition at line 764 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR3_MASK   0x000000FFUL

Mask for ETM_ETMCIDR3

Definition at line 773 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR3_PREAMB_DEFAULT   0x000000B1UL

Mode DEFAULT for ETM_ETMCIDR3

Definition at line 776 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR3_PREAMB_MASK   0xFFUL

Bit mask for ETM_PREAMB

Definition at line 775 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR3_PREAMB_SHIFT   0

Shift value for ETM_PREAMB

Definition at line 774 of file efm32jg12b_etm.h.

#define _ETM_ETMCIDR3_RESETVALUE   0x000000B1UL

Default value for ETM_ETMCIDR3

Definition at line 772 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCLAIMCLR

Definition at line 612 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMCLR_CLRTAG_MASK   0x1UL

Bit mask for ETM_CLRTAG

Definition at line 611 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT   0

Shift value for ETM_CLRTAG

Definition at line 610 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMCLR_MASK   0x00000001UL

Mask for ETM_ETMCLAIMCLR

Definition at line 608 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMCLR_RESETVALUE   0x00000000UL

Default value for ETM_ETMCLAIMCLR

Definition at line 607 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMSET_MASK   0x000000FFUL

Mask for ETM_ETMCLAIMSET

Definition at line 600 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMSET_RESETVALUE   0x0000000FUL

Default value for ETM_ETMCLAIMSET

Definition at line 599 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT   0x0000000FUL

Mode DEFAULT for ETM_ETMCLAIMSET

Definition at line 603 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMSET_SETTAG_MASK   0xFFUL

Bit mask for ETM_SETTAG

Definition at line 602 of file efm32jg12b_etm.h.

#define _ETM_ETMCLAIMSET_SETTAG_SHIFT   0

Shift value for ETM_SETTAG

Definition at line 601 of file efm32jg12b_etm.h.

#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCNTRLDVR1

Definition at line 367 of file efm32jg12b_etm.h.

#define _ETM_ETMCNTRLDVR1_COUNT_MASK   0xFFFFUL

Bit mask for ETM_COUNT

Definition at line 366 of file efm32jg12b_etm.h.

#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT   0

Shift value for ETM_COUNT

Definition at line 365 of file efm32jg12b_etm.h.

#define _ETM_ETMCNTRLDVR1_MASK   0x0000FFFFUL

Mask for ETM_ETMCNTRLDVR1

Definition at line 364 of file efm32jg12b_etm.h.

#define _ETM_ETMCNTRLDVR1_RESETVALUE   0x00000000UL

Default value for ETM_ETMCNTRLDVR1

Definition at line 363 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCR

Definition at line 128 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_BRANCHOUTPUT_MASK   0x100UL

Bit mask for ETM_BRANCHOUTPUT

Definition at line 127 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT   8

Shift value for ETM_BRANCHOUTPUT

Definition at line 126 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_DBGREQCTRL_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCR

Definition at line 133 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_DBGREQCTRL_MASK   0x200UL

Bit mask for ETM_DBGREQCTRL

Definition at line 132 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_DBGREQCTRL_SHIFT   9

Shift value for ETM_DBGREQCTRL

Definition at line 131 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_EPORTSIZE_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCR

Definition at line 160 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_EPORTSIZE_MASK   0x600000UL

Bit mask for ETM_EPORTSIZE

Definition at line 159 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_EPORTSIZE_SHIFT   21

Shift value for ETM_EPORTSIZE

Definition at line 158 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_ETMPORTSEL_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCR

Definition at line 143 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH   0x00000001UL

Mode ETMHIGH for ETM_ETMCR

Definition at line 145 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_ETMPORTSEL_ETMLOW   0x00000000UL

Mode ETMLOW for ETM_ETMCR

Definition at line 144 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_ETMPORTSEL_MASK   0x800UL

Bit mask for ETM_ETMPORTSEL

Definition at line 142 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_ETMPORTSEL_SHIFT   11

Shift value for ETM_ETMPORTSEL

Definition at line 141 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_ETMPROG_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCR

Definition at line 138 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_ETMPROG_MASK   0x400UL

Bit mask for ETM_ETMPROG

Definition at line 137 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_ETMPROG_SHIFT   10

Shift value for ETM_ETMPROG

Definition at line 136 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_MASK   0x10632FF1UL

Mask for ETM_ETMCR

Definition at line 110 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_PORTMODE2_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCR

Definition at line 152 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_PORTMODE2_MASK   0x2000UL

Bit mask for ETM_PORTMODE2

Definition at line 151 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_PORTMODE2_SHIFT   13

Shift value for ETM_PORTMODE2

Definition at line 150 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_PORTMODE_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCR

Definition at line 156 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_PORTMODE_MASK   0x30000UL

Bit mask for ETM_PORTMODE

Definition at line 155 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_PORTMODE_SHIFT   16

Shift value for ETM_PORTMODE

Definition at line 154 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_PORTSIZE_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCR

Definition at line 118 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_PORTSIZE_MASK   0x70UL

Bit mask for ETM_PORTSIZE

Definition at line 117 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_PORTSIZE_SHIFT   4

Shift value for ETM_PORTSIZE

Definition at line 116 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_POWERDWN_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMCR

Definition at line 114 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_POWERDWN_MASK   0x1UL

Bit mask for ETM_POWERDWN

Definition at line 113 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_POWERDWN_SHIFT   0

Shift value for ETM_POWERDWN

Definition at line 112 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_RESETVALUE   0x00000411UL

Default value for ETM_ETMCR

Definition at line 109 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_STALL_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCR

Definition at line 123 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_STALL_MASK   0x80UL

Bit mask for ETM_STALL

Definition at line 122 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_STALL_SHIFT   7

Shift value for ETM_STALL

Definition at line 121 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_TSTAMPEN_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMCR

Definition at line 165 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_TSTAMPEN_MASK   0x10000000UL

Bit mask for ETM_TSTAMPEN

Definition at line 164 of file efm32jg12b_etm.h.

#define _ETM_ETMCR_TSTAMPEN_SHIFT   28

Shift value for ETM_TSTAMPEN

Definition at line 163 of file efm32jg12b_etm.h.

#define _ETM_ETMDEVTYPE_MASK   0x000000FFUL

Mask for ETM_ETMDEVTYPE

Definition at line 664 of file efm32jg12b_etm.h.

#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMDEVTYPE

Definition at line 671 of file efm32jg12b_etm.h.

#define _ETM_ETMDEVTYPE_PROCTRACE_MASK   0xF0UL

Bit mask for ETM_PROCTRACE

Definition at line 670 of file efm32jg12b_etm.h.

#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT   4

Shift value for ETM_PROCTRACE

Definition at line 669 of file efm32jg12b_etm.h.

#define _ETM_ETMDEVTYPE_RESETVALUE   0x00000013UL

Default value for ETM_ETMDEVTYPE

Definition at line 663 of file efm32jg12b_etm.h.

#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT   0x00000003UL

Mode DEFAULT for ETM_ETMDEVTYPE

Definition at line 667 of file efm32jg12b_etm.h.

#define _ETM_ETMDEVTYPE_TRACESRC_MASK   0xFUL

Bit mask for ETM_TRACESRC

Definition at line 666 of file efm32jg12b_etm.h.

#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT   0

Shift value for ETM_TRACESRC

Definition at line 665 of file efm32jg12b_etm.h.

#define _ETM_ETMFFLR_BYTENUM_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMFFLR

Definition at line 359 of file efm32jg12b_etm.h.

#define _ETM_ETMFFLR_BYTENUM_MASK   0xFFUL

Bit mask for ETM_BYTENUM

Definition at line 358 of file efm32jg12b_etm.h.

#define _ETM_ETMFFLR_BYTENUM_SHIFT   0

Shift value for ETM_BYTENUM

Definition at line 357 of file efm32jg12b_etm.h.

#define _ETM_ETMFFLR_MASK   0x000000FFUL

Mask for ETM_ETMFFLR

Definition at line 356 of file efm32jg12b_etm.h.

#define _ETM_ETMFFLR_RESETVALUE   0x00000000UL

Default value for ETM_ETMFFLR

Definition at line 355 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_MASK   0x00000003UL

Mask for ETM_ETMIDR2

Definition at line 520 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_RESETVALUE   0x00000000UL

Default value for ETM_ETMIDR2

Definition at line 519 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_RFE_CPSR   0x00000001UL

Mode CPSR for ETM_ETMIDR2

Definition at line 526 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_RFE_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMIDR2

Definition at line 524 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_RFE_MASK   0x1UL

Bit mask for ETM_RFE

Definition at line 523 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_RFE_PC   0x00000000UL

Mode PC for ETM_ETMIDR2

Definition at line 525 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_RFE_SHIFT   0

Shift value for ETM_RFE

Definition at line 522 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_SWP_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMIDR2

Definition at line 533 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_SWP_LOAD   0x00000000UL

Mode LOAD for ETM_ETMIDR2

Definition at line 534 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_SWP_MASK   0x2UL

Bit mask for ETM_SWP

Definition at line 532 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_SWP_SHIFT   1

Shift value for ETM_SWP

Definition at line 531 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR2_SWP_STORE   0x00000001UL

Mode STORE for ETM_ETMIDR2

Definition at line 535 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_BPE_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMIDR

Definition at line 415 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_BPE_MASK   0x100000UL

Bit mask for ETM_BPE

Definition at line 414 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_BPE_SHIFT   20

Shift value for ETM_BPE

Definition at line 413 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_ETMMAJVER_DEFAULT   0x00000002UL

Mode DEFAULT for ETM_ETMIDR

Definition at line 391 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_ETMMAJVER_MASK   0xF00UL

Bit mask for ETM_ETMMAJVER

Definition at line 390 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_ETMMAJVER_SHIFT   8

Shift value for ETM_ETMMAJVER

Definition at line 389 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_ETMMINVER_DEFAULT   0x00000005UL

Mode DEFAULT for ETM_ETMIDR

Definition at line 387 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_ETMMINVER_MASK   0xF0UL

Bit mask for ETM_ETMMINVER

Definition at line 386 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_ETMMINVER_SHIFT   4

Shift value for ETM_ETMMINVER

Definition at line 385 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_IMPCODE_DEFAULT   0x00000041UL

Mode DEFAULT for ETM_ETMIDR

Definition at line 419 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_IMPCODE_MASK   0xFF000000UL

Bit mask for ETM_IMPCODE

Definition at line 418 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_IMPCODE_SHIFT   24

Shift value for ETM_IMPCODE

Definition at line 417 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_IMPVER_DEFAULT   0x00000003UL

Mode DEFAULT for ETM_ETMIDR

Definition at line 383 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_IMPVER_MASK   0xFUL

Bit mask for ETM_IMPVER

Definition at line 382 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_IMPVER_SHIFT   0

Shift value for ETM_IMPVER

Definition at line 381 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_LPCF_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMIDR

Definition at line 400 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_LPCF_MASK   0x10000UL

Bit mask for ETM_LPCF

Definition at line 399 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_LPCF_SHIFT   16

Shift value for ETM_LPCF

Definition at line 398 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_MASK   0xFF1DFFFFUL

Mask for ETM_ETMIDR

Definition at line 380 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_PROCFAM_DEFAULT   0x0000000FUL

Mode DEFAULT for ETM_ETMIDR

Definition at line 395 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_PROCFAM_MASK   0xF000UL

Bit mask for ETM_PROCFAM

Definition at line 394 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_PROCFAM_SHIFT   12

Shift value for ETM_PROCFAM

Definition at line 393 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_RESETVALUE   0x4114F253UL

Default value for ETM_ETMIDR

Definition at line 379 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_SECEXT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMIDR

Definition at line 410 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_SECEXT_MASK   0x80000UL

Bit mask for ETM_SECEXT

Definition at line 409 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_SECEXT_SHIFT   19

Shift value for ETM_SECEXT

Definition at line 408 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_THUMBT_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMIDR

Definition at line 405 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_THUMBT_MASK   0x40000UL

Bit mask for ETM_THUMBT

Definition at line 404 of file efm32jg12b_etm.h.

#define _ETM_ETMIDR_THUMBT_SHIFT   18

Shift value for ETM_THUMBT

Definition at line 403 of file efm32jg12b_etm.h.

#define _ETM_ETMISCIN_COREHALT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMISCIN

Definition at line 559 of file efm32jg12b_etm.h.

#define _ETM_ETMISCIN_COREHALT_MASK   0x10UL

Bit mask for ETM_COREHALT

Definition at line 558 of file efm32jg12b_etm.h.

#define _ETM_ETMISCIN_COREHALT_SHIFT   4

Shift value for ETM_COREHALT

Definition at line 557 of file efm32jg12b_etm.h.

#define _ETM_ETMISCIN_EXTIN_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMISCIN

Definition at line 554 of file efm32jg12b_etm.h.

#define _ETM_ETMISCIN_EXTIN_MASK   0x3UL

Bit mask for ETM_EXTIN

Definition at line 553 of file efm32jg12b_etm.h.

#define _ETM_ETMISCIN_EXTIN_SHIFT   0

Shift value for ETM_EXTIN

Definition at line 552 of file efm32jg12b_etm.h.

#define _ETM_ETMISCIN_MASK   0x00000013UL

Mask for ETM_ETMISCIN

Definition at line 551 of file efm32jg12b_etm.h.

#define _ETM_ETMISCIN_RESETVALUE   0x00000000UL

Default value for ETM_ETMISCIN

Definition at line 550 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMITATBCTR0

Definition at line 586 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR0_ATVALID_MASK   0x1UL

Bit mask for ETM_ATVALID

Definition at line 585 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR0_ATVALID_SHIFT   0

Shift value for ETM_ATVALID

Definition at line 584 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR0_MASK   0x00000001UL

Mask for ETM_ETMITATBCTR0

Definition at line 582 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR0_RESETVALUE   0x00000000UL

Default value for ETM_ETMITATBCTR0

Definition at line 581 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMITATBCTR2

Definition at line 577 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR2_ATREADY_MASK   0x1UL

Bit mask for ETM_ATREADY

Definition at line 576 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR2_ATREADY_SHIFT   0

Shift value for ETM_ATREADY

Definition at line 575 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR2_MASK   0x00000001UL

Mask for ETM_ETMITATBCTR2

Definition at line 573 of file efm32jg12b_etm.h.

#define _ETM_ETMITATBCTR2_RESETVALUE   0x00000001UL

Default value for ETM_ETMITATBCTR2

Definition at line 572 of file efm32jg12b_etm.h.

#define _ETM_ETMITCTRL_ITEN_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMITCTRL

Definition at line 595 of file efm32jg12b_etm.h.

#define _ETM_ETMITCTRL_ITEN_MASK   0x1UL

Bit mask for ETM_ITEN

Definition at line 594 of file efm32jg12b_etm.h.

#define _ETM_ETMITCTRL_ITEN_SHIFT   0

Shift value for ETM_ITEN

Definition at line 593 of file efm32jg12b_etm.h.

#define _ETM_ETMITCTRL_MASK   0x00000001UL

Mask for ETM_ETMITCTRL

Definition at line 591 of file efm32jg12b_etm.h.

#define _ETM_ETMITCTRL_RESETVALUE   0x00000000UL

Default value for ETM_ETMITCTRL

Definition at line 590 of file efm32jg12b_etm.h.

#define _ETM_ETMLAR_KEY_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMLAR

Definition at line 621 of file efm32jg12b_etm.h.

#define _ETM_ETMLAR_KEY_MASK   0x1UL

Bit mask for ETM_KEY

Definition at line 620 of file efm32jg12b_etm.h.

#define _ETM_ETMLAR_KEY_SHIFT   0

Shift value for ETM_KEY

Definition at line 619 of file efm32jg12b_etm.h.

#define _ETM_ETMLAR_MASK   0x00000001UL

Mask for ETM_ETMLAR

Definition at line 617 of file efm32jg12b_etm.h.

#define _ETM_ETMLAR_RESETVALUE   0x00000000UL

Default value for ETM_ETMLAR

Definition at line 616 of file efm32jg12b_etm.h.

#define _ETM_ETMLSR_LOCKED_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMLSR

Definition at line 635 of file efm32jg12b_etm.h.

#define _ETM_ETMLSR_LOCKED_MASK   0x2UL

Bit mask for ETM_LOCKED

Definition at line 634 of file efm32jg12b_etm.h.

#define _ETM_ETMLSR_LOCKED_SHIFT   1

Shift value for ETM_LOCKED

Definition at line 633 of file efm32jg12b_etm.h.

#define _ETM_ETMLSR_LOCKIMP_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMLSR

Definition at line 630 of file efm32jg12b_etm.h.

#define _ETM_ETMLSR_LOCKIMP_MASK   0x1UL

Bit mask for ETM_LOCKIMP

Definition at line 629 of file efm32jg12b_etm.h.

#define _ETM_ETMLSR_LOCKIMP_SHIFT   0

Shift value for ETM_LOCKIMP

Definition at line 628 of file efm32jg12b_etm.h.

#define _ETM_ETMLSR_MASK   0x00000003UL

Mask for ETM_ETMLSR

Definition at line 626 of file efm32jg12b_etm.h.

#define _ETM_ETMLSR_RESETVALUE   0x00000003UL

Default value for ETM_ETMLSR

Definition at line 625 of file efm32jg12b_etm.h.

#define _ETM_ETMPDSR_ETMUP_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMPDSR

Definition at line 546 of file efm32jg12b_etm.h.

#define _ETM_ETMPDSR_ETMUP_MASK   0x1UL

Bit mask for ETM_ETMUP

Definition at line 545 of file efm32jg12b_etm.h.

#define _ETM_ETMPDSR_ETMUP_SHIFT   0

Shift value for ETM_ETMUP

Definition at line 544 of file efm32jg12b_etm.h.

#define _ETM_ETMPDSR_MASK   0x00000001UL

Mask for ETM_ETMPDSR

Definition at line 542 of file efm32jg12b_etm.h.

#define _ETM_ETMPDSR_RESETVALUE   0x00000001UL

Default value for ETM_ETMPDSR

Definition at line 541 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR0_MASK   0x000000FFUL

Mask for ETM_ETMPIDR0

Definition at line 700 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR0_PARTNUM_DEFAULT   0x00000025UL

Mode DEFAULT for ETM_ETMPIDR0

Definition at line 703 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR0_PARTNUM_MASK   0xFFUL

Bit mask for ETM_PARTNUM

Definition at line 702 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR0_PARTNUM_SHIFT   0

Shift value for ETM_PARTNUM

Definition at line 701 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR0_RESETVALUE   0x00000025UL

Default value for ETM_ETMPIDR0

Definition at line 699 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR1_IDCODE_DEFAULT   0x0000000BUL

Mode DEFAULT for ETM_ETMPIDR1

Definition at line 715 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR1_IDCODE_MASK   0xF0UL

Bit mask for ETM_IDCODE

Definition at line 714 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR1_IDCODE_SHIFT   4

Shift value for ETM_IDCODE

Definition at line 713 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR1_MASK   0x000000FFUL

Mask for ETM_ETMPIDR1

Definition at line 708 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR1_PARTNUM_DEFAULT   0x00000009UL

Mode DEFAULT for ETM_ETMPIDR1

Definition at line 711 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR1_PARTNUM_MASK   0xFUL

Bit mask for ETM_PARTNUM

Definition at line 710 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR1_PARTNUM_SHIFT   0

Shift value for ETM_PARTNUM

Definition at line 709 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR1_RESETVALUE   0x000000B9UL

Default value for ETM_ETMPIDR1

Definition at line 707 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMPIDR2

Definition at line 728 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_ALWAYS1_MASK   0x8UL

Bit mask for ETM_ALWAYS1

Definition at line 727 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_ALWAYS1_SHIFT   3

Shift value for ETM_ALWAYS1

Definition at line 726 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_IDCODE_DEFAULT   0x00000003UL

Mode DEFAULT for ETM_ETMPIDR2

Definition at line 723 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_IDCODE_MASK   0x7UL

Bit mask for ETM_IDCODE

Definition at line 722 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_IDCODE_SHIFT   0

Shift value for ETM_IDCODE

Definition at line 721 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_MASK   0x000000FFUL

Mask for ETM_ETMPIDR2

Definition at line 720 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_RESETVALUE   0x0000000BUL

Default value for ETM_ETMPIDR2

Definition at line 719 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_REV_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMPIDR2

Definition at line 732 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_REV_MASK   0xF0UL

Bit mask for ETM_REV

Definition at line 731 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR2_REV_SHIFT   4

Shift value for ETM_REV

Definition at line 730 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMPIDR3

Definition at line 740 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR3_CUSTMOD_MASK   0xFUL

Bit mask for ETM_CUSTMOD

Definition at line 739 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR3_CUSTMOD_SHIFT   0

Shift value for ETM_CUSTMOD

Definition at line 738 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR3_MASK   0x000000FFUL

Mask for ETM_ETMPIDR3

Definition at line 737 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR3_RESETVALUE   0x00000000UL

Default value for ETM_ETMPIDR3

Definition at line 736 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR3_REVAND_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMPIDR3

Definition at line 744 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR3_REVAND_MASK   0xF0UL

Bit mask for ETM_REVAND

Definition at line 743 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR3_REVAND_SHIFT   4

Shift value for ETM_REVAND

Definition at line 742 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR4_CONTCODE_DEFAULT   0x00000004UL

Mode DEFAULT for ETM_ETMPIDR4

Definition at line 679 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR4_CONTCODE_MASK   0xFUL

Bit mask for ETM_CONTCODE

Definition at line 678 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR4_CONTCODE_SHIFT   0

Shift value for ETM_CONTCODE

Definition at line 677 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR4_COUNT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMPIDR4

Definition at line 683 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR4_COUNT_MASK   0xF0UL

Bit mask for ETM_COUNT

Definition at line 682 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR4_COUNT_SHIFT   4

Shift value for ETM_COUNT

Definition at line 681 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR4_MASK   0x000000FFUL

Mask for ETM_ETMPIDR4

Definition at line 676 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR4_RESETVALUE   0x00000004UL

Default value for ETM_ETMPIDR4

Definition at line 675 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR5_MASK   0x00000000UL

Mask for ETM_ETMPIDR5

Definition at line 688 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR5_RESETVALUE   0x00000000UL

Default value for ETM_ETMPIDR5

Definition at line 687 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR6_MASK   0x00000000UL

Mask for ETM_ETMPIDR6

Definition at line 692 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR6_RESETVALUE   0x00000000UL

Default value for ETM_ETMPIDR6

Definition at line 691 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR7_MASK   0x00000000UL

Mask for ETM_ETMPIDR7

Definition at line 696 of file efm32jg12b_etm.h.

#define _ETM_ETMPIDR7_RESETVALUE   0x00000000UL

Default value for ETM_ETMPIDR7

Definition at line 695 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_FIFOFULL_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMSCR

Definition at line 281 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_FIFOFULL_MASK   0x100UL

Bit mask for ETM_FIFOFULL

Definition at line 280 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_FIFOFULL_SHIFT   8

Shift value for ETM_FIFOFULL

Definition at line 279 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_MASK   0x00027F0FUL

Mask for ETM_ETMSCR

Definition at line 273 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMSCR

Definition at line 286 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_MAXPORTSIZE3_MASK   0x200UL

Bit mask for ETM_MAXPORTSIZE3

Definition at line 285 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT   9

Shift value for ETM_MAXPORTSIZE3

Definition at line 284 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMSCR

Definition at line 276 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_MAXPORTSIZE_MASK   0x7UL

Bit mask for ETM_MAXPORTSIZE

Definition at line 275 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT   0

Shift value for ETM_MAXPORTSIZE

Definition at line 274 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMSCR

Definition at line 305 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_NOFETCHCOMP_MASK   0x20000UL

Bit mask for ETM_NOFETCHCOMP

Definition at line 304 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT   17

Shift value for ETM_NOFETCHCOMP

Definition at line 303 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_PORTMODE_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMSCR

Definition at line 296 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_PORTMODE_MASK   0x800UL

Bit mask for ETM_PORTMODE

Definition at line 295 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_PORTMODE_SHIFT   11

Shift value for ETM_PORTMODE

Definition at line 294 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_PORTSIZE_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMSCR

Definition at line 291 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_PORTSIZE_MASK   0x400UL

Bit mask for ETM_PORTSIZE

Definition at line 290 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_PORTSIZE_SHIFT   10

Shift value for ETM_PORTSIZE

Definition at line 289 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_PROCNUM_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMSCR

Definition at line 300 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_PROCNUM_MASK   0x7000UL

Bit mask for ETM_PROCNUM

Definition at line 299 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_PROCNUM_SHIFT   12

Shift value for ETM_PROCNUM

Definition at line 298 of file efm32jg12b_etm.h.

#define _ETM_ETMSCR_RESETVALUE   0x00020D09UL

Default value for ETM_ETMSCR

Definition at line 272 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_ETHOF_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMSR

Definition at line 253 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_ETHOF_MASK   0x1UL

Bit mask for ETM_ETHOF

Definition at line 252 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_ETHOF_SHIFT   0

Shift value for ETM_ETHOF

Definition at line 251 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_ETMPROGBIT_DEFAULT   0x00000001UL

Mode DEFAULT for ETM_ETMSR

Definition at line 258 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_ETMPROGBIT_MASK   0x2UL

Bit mask for ETM_ETMPROGBIT

Definition at line 257 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_ETMPROGBIT_SHIFT   1

Shift value for ETM_ETMPROGBIT

Definition at line 256 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_MASK   0x0000000FUL

Mask for ETM_ETMSR

Definition at line 249 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_RESETVALUE   0x00000002UL

Default value for ETM_ETMSR

Definition at line 248 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_TRACESTAT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMSR

Definition at line 263 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_TRACESTAT_MASK   0x4UL

Bit mask for ETM_TRACESTAT

Definition at line 262 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_TRACESTAT_SHIFT   2

Shift value for ETM_TRACESTAT

Definition at line 261 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_TRIGBIT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMSR

Definition at line 268 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_TRIGBIT_MASK   0x8UL

Bit mask for ETM_TRIGBIT

Definition at line 267 of file efm32jg12b_etm.h.

#define _ETM_ETMSR_TRIGBIT_SHIFT   3

Shift value for ETM_TRIGBIT

Definition at line 266 of file efm32jg12b_etm.h.

#define _ETM_ETMSYNCFR_FREQ_DEFAULT   0x00000400UL

Mode DEFAULT for ETM_ETMSYNCFR

Definition at line 375 of file efm32jg12b_etm.h.

#define _ETM_ETMSYNCFR_FREQ_MASK   0xFFFUL

Bit mask for ETM_FREQ

Definition at line 374 of file efm32jg12b_etm.h.

#define _ETM_ETMSYNCFR_FREQ_SHIFT   0

Shift value for ETM_FREQ

Definition at line 373 of file efm32jg12b_etm.h.

#define _ETM_ETMSYNCFR_MASK   0x00000FFFUL

Mask for ETM_ETMSYNCFR

Definition at line 372 of file efm32jg12b_etm.h.

#define _ETM_ETMSYNCFR_RESETVALUE   0x00000400UL

Default value for ETM_ETMSYNCFR

Definition at line 371 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_ADRCMP_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTECR1

Definition at line 329 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_ADRCMP_MASK   0xFFUL

Bit mask for ETM_ADRCMP

Definition at line 328 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_ADRCMP_SHIFT   0

Shift value for ETM_ADRCMP

Definition at line 327 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_INCEXCTL_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTECR1

Definition at line 338 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_INCEXCTL_EXC   0x00000001UL

Mode EXC for ETM_ETMTECR1

Definition at line 340 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_INCEXCTL_INC   0x00000000UL

Mode INC for ETM_ETMTECR1

Definition at line 339 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_INCEXCTL_MASK   0x1000000UL

Bit mask for ETM_INCEXCTL

Definition at line 337 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_INCEXCTL_SHIFT   24

Shift value for ETM_INCEXCTL

Definition at line 336 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_MASK   0x03FFFFFFUL

Mask for ETM_ETMTECR1

Definition at line 326 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_MEMMAP_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTECR1

Definition at line 333 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_MEMMAP_MASK   0xFFFF00UL

Bit mask for ETM_MEMMAP

Definition at line 332 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_MEMMAP_SHIFT   8

Shift value for ETM_MEMMAP

Definition at line 331 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_RESETVALUE   0x00000000UL

Default value for ETM_ETMTECR1

Definition at line 325 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_TCE_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTECR1

Definition at line 347 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_TCE_DIS   0x00000001UL

Mode DIS for ETM_ETMTECR1

Definition at line 349 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_TCE_EN   0x00000000UL

Mode EN for ETM_ETMTECR1

Definition at line 348 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_TCE_MASK   0x2000000UL

Bit mask for ETM_TCE

Definition at line 346 of file efm32jg12b_etm.h.

#define _ETM_ETMTECR1_TCE_SHIFT   25

Shift value for ETM_TCE

Definition at line 345 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTEEVR

Definition at line 321 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_ETMFCNEN_MASK   0x1C000UL

Bit mask for ETM_ETMFCNEN

Definition at line 320 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT   14

Shift value for ETM_ETMFCNEN

Definition at line 319 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_MASK   0x0001FFFFUL

Mask for ETM_ETMTEEVR

Definition at line 310 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_RESA_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTEEVR

Definition at line 313 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_RESA_MASK   0x7FUL

Bit mask for ETM_RESA

Definition at line 312 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_RESA_SHIFT   0

Shift value for ETM_RESA

Definition at line 311 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_RESB_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTEEVR

Definition at line 317 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_RESB_MASK   0x3F80UL

Bit mask for ETM_RESB

Definition at line 316 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_RESB_SHIFT   7

Shift value for ETM_RESB

Definition at line 315 of file efm32jg12b_etm.h.

#define _ETM_ETMTEEVR_RESETVALUE   0x00000000UL

Default value for ETM_ETMTEEVR

Definition at line 309 of file efm32jg12b_etm.h.

#define _ETM_ETMTESSEICR_MASK   0x000F000FUL

Mask for ETM_ETMTESSEICR

Definition at line 484 of file efm32jg12b_etm.h.

#define _ETM_ETMTESSEICR_RESETVALUE   0x00000000UL

Default value for ETM_ETMTESSEICR

Definition at line 483 of file efm32jg12b_etm.h.

#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTESSEICR

Definition at line 487 of file efm32jg12b_etm.h.

#define _ETM_ETMTESSEICR_STARTRSEL_MASK   0xFUL

Bit mask for ETM_STARTRSEL

Definition at line 486 of file efm32jg12b_etm.h.

#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT   0

Shift value for ETM_STARTRSEL

Definition at line 485 of file efm32jg12b_etm.h.

#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTESSEICR

Definition at line 491 of file efm32jg12b_etm.h.

#define _ETM_ETMTESSEICR_STOPRSEL_MASK   0xF0000UL

Bit mask for ETM_STOPRSEL

Definition at line 490 of file efm32jg12b_etm.h.

#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT   16

Shift value for ETM_STOPRSEL

Definition at line 489 of file efm32jg12b_etm.h.

#define _ETM_ETMTRACEIDR_MASK   0x0000007FUL

Mask for ETM_ETMTRACEIDR

Definition at line 512 of file efm32jg12b_etm.h.

#define _ETM_ETMTRACEIDR_RESETVALUE   0x00000000UL

Default value for ETM_ETMTRACEIDR

Definition at line 511 of file efm32jg12b_etm.h.

#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTRACEIDR

Definition at line 515 of file efm32jg12b_etm.h.

#define _ETM_ETMTRACEIDR_TRACEID_MASK   0x7FUL

Bit mask for ETM_TRACEID

Definition at line 514 of file efm32jg12b_etm.h.

#define _ETM_ETMTRACEIDR_TRACEID_SHIFT   0

Shift value for ETM_TRACEID

Definition at line 513 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTRIGGER

Definition at line 244 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_ETMFCN_MASK   0x1C000UL

Bit mask for ETM_ETMFCN

Definition at line 243 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_ETMFCN_SHIFT   14

Shift value for ETM_ETMFCN

Definition at line 242 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_MASK   0x0001FFFFUL

Mask for ETM_ETMTRIGGER

Definition at line 233 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_RESA_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTRIGGER

Definition at line 236 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_RESA_MASK   0x7FUL

Bit mask for ETM_RESA

Definition at line 235 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_RESA_SHIFT   0

Shift value for ETM_RESA

Definition at line 234 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_RESB_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTRIGGER

Definition at line 240 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_RESB_MASK   0x3F80UL

Bit mask for ETM_RESB

Definition at line 239 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_RESB_SHIFT   7

Shift value for ETM_RESB

Definition at line 238 of file efm32jg12b_etm.h.

#define _ETM_ETMTRIGGER_RESETVALUE   0x00000000UL

Default value for ETM_ETMTRIGGER

Definition at line 232 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTSEVR

Definition at line 507 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_ETMFCNEVT_MASK   0x1C000UL

Bit mask for ETM_ETMFCNEVT

Definition at line 506 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT   14

Shift value for ETM_ETMFCNEVT

Definition at line 505 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_MASK   0x0001FFFFUL

Mask for ETM_ETMTSEVR

Definition at line 496 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_RESAEVT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTSEVR

Definition at line 499 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_RESAEVT_MASK   0x7FUL

Bit mask for ETM_RESAEVT

Definition at line 498 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_RESAEVT_SHIFT   0

Shift value for ETM_RESAEVT

Definition at line 497 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_RESBEVT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ETMTSEVR

Definition at line 503 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_RESBEVT_MASK   0x3F80UL

Bit mask for ETM_RESBEVT

Definition at line 502 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_RESBEVT_SHIFT   7

Shift value for ETM_RESBEVT

Definition at line 501 of file efm32jg12b_etm.h.

#define _ETM_ETMTSEVR_RESETVALUE   0x00000000UL

Default value for ETM_ETMTSEVR

Definition at line 495 of file efm32jg12b_etm.h.

#define _ETM_ITTRIGOUT_MASK   0x00000001UL

Mask for ETM_ITTRIGOUT

Definition at line 564 of file efm32jg12b_etm.h.

#define _ETM_ITTRIGOUT_RESETVALUE   0x00000000UL

Default value for ETM_ITTRIGOUT

Definition at line 563 of file efm32jg12b_etm.h.

#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT   0x00000000UL

Mode DEFAULT for ETM_ITTRIGOUT

Definition at line 568 of file efm32jg12b_etm.h.

#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK   0x1UL

Bit mask for ETM_TRIGGEROUT

Definition at line 567 of file efm32jg12b_etm.h.

#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT   0

Shift value for ETM_TRIGGEROUT

Definition at line 566 of file efm32jg12b_etm.h.

#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT   (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMAUTHSTATUS

Definition at line 644 of file efm32jg12b_etm.h.

#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT   (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2)

Shifted mode DEFAULT for ETM_ETMAUTHSTATUS

Definition at line 650 of file efm32jg12b_etm.h.

#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE   (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2)

Shifted mode DISABLE for ETM_ETMAUTHSTATUS

Definition at line 651 of file efm32jg12b_etm.h.

#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE   (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2)

Shifted mode ENABLE for ETM_ETMAUTHSTATUS

Definition at line 652 of file efm32jg12b_etm.h.

#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT   (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMAUTHSTATUS

Definition at line 656 of file efm32jg12b_etm.h.

#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT   (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6)

Shifted mode DEFAULT for ETM_ETMAUTHSTATUS

Definition at line 660 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_DADDRCMP   (0x1UL << 12)

Data Address comparisons

Definition at line 438 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_DADDRCMP_DEFAULT   (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 442 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_EICEIMP   (0x1UL << 21)

EmbeddedICE Behavior control Implemented

Definition at line 456 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_EICEIMP_DEFAULT   (_ETM_ETMCCER_EICEIMP_DEFAULT << 21)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 460 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_EICEWPNT_DEFAULT   (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 450 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_EXTINPBUS_DEFAULT   (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 432 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_EXTINPSEL_DEFAULT   (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 428 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_INSTRES_DEFAULT   (_ETM_ETMCCER_INSTRES_DEFAULT << 13)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 446 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_READREGS   (0x1UL << 11)

Readable Registers

Definition at line 433 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_READREGS_DEFAULT   (_ETM_ETMCCER_READREGS_DEFAULT << 11)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 437 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_RFCNT   (0x1UL << 27)

Reduced Function Counter

Definition at line 466 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_RFCNT_DEFAULT   (_ETM_ETMCCER_RFCNT_DEFAULT << 27)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 470 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_TEICEWPNT   (0x1UL << 20)

Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs

Definition at line 451 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_TEICEWPNT_DEFAULT   (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 455 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_TENC   (0x1UL << 28)

Timestamp Encoding

Definition at line 471 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_TENC_DEFAULT   (_ETM_ETMCCER_TENC_DEFAULT << 28)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 475 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_TIMP   (0x1UL << 22)

Timestamping Implemented

Definition at line 461 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_TIMP_DEFAULT   (_ETM_ETMCCER_TIMP_DEFAULT << 22)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 465 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_TSIZE   (0x1UL << 29)

Timestamp Size

Definition at line 476 of file efm32jg12b_etm.h.

#define ETM_ETMCCER_TSIZE_DEFAULT   (_ETM_ETMCCER_TSIZE_DEFAULT << 29)

Shifted mode DEFAULT for ETM_ETMCCER

Definition at line 480 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT   (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 174 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_COUNTNUM_DEFAULT   (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 186 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_DATACMPNUM_DEFAULT   (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 178 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_ETMID   (0x1UL << 31)

ETM ID Register Present

Definition at line 225 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_ETMID_DEFAULT   (_ETM_ETMCCR_ETMID_DEFAULT << 31)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 229 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_EXTINPNUM_DEFAULT   (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 198 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_EXTINPNUM_ONE   (_ETM_ETMCCR_EXTINPNUM_ONE << 17)

Shifted mode ONE for ETM_ETMCCR

Definition at line 200 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_EXTINPNUM_TWO   (_ETM_ETMCCR_EXTINPNUM_TWO << 17)

Shifted mode TWO for ETM_ETMCCR

Definition at line 201 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_EXTINPNUM_ZERO   (_ETM_ETMCCR_EXTINPNUM_ZERO << 17)

Shifted mode ZERO for ETM_ETMCCR

Definition at line 199 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_EXTOUTNUM_DEFAULT   (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 205 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_FIFOFULLPRES   (0x1UL << 23)

FIFIO FULL present

Definition at line 206 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT   (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 210 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_IDCOMPNUM_DEFAULT   (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 214 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_MMACCESS   (0x1UL << 27)

Coprocessor and Memeory Access

Definition at line 220 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_MMACCESS_DEFAULT   (_ETM_ETMCCR_MMACCESS_DEFAULT << 27)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 224 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_MMDECCNT_DEFAULT   (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 182 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_SEQPRES   (0x1UL << 16)

Sequencer Present

Definition at line 187 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_SEQPRES_DEFAULT   (_ETM_ETMCCR_SEQPRES_DEFAULT << 16)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 191 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_TRACESS   (0x1UL << 26)

Trace Start/Stop Block Present

Definition at line 215 of file efm32jg12b_etm.h.

#define ETM_ETMCCR_TRACESS_DEFAULT   (_ETM_ETMCCR_TRACESS_DEFAULT << 26)

Shifted mode DEFAULT for ETM_ETMCCR

Definition at line 219 of file efm32jg12b_etm.h.

#define ETM_ETMCIDR0_PREAMB_DEFAULT   (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCIDR0

Definition at line 753 of file efm32jg12b_etm.h.

#define ETM_ETMCIDR1_PREAMB_DEFAULT   (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCIDR1

Definition at line 761 of file efm32jg12b_etm.h.

#define ETM_ETMCIDR2_PREAMB_DEFAULT   (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCIDR2

Definition at line 769 of file efm32jg12b_etm.h.

#define ETM_ETMCIDR3_PREAMB_DEFAULT   (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCIDR3

Definition at line 777 of file efm32jg12b_etm.h.

#define ETM_ETMCLAIMCLR_CLRTAG   (0x1UL << 0)

Tag Bits

Definition at line 609 of file efm32jg12b_etm.h.

#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT   (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCLAIMCLR

Definition at line 613 of file efm32jg12b_etm.h.

#define ETM_ETMCLAIMSET_SETTAG_DEFAULT   (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCLAIMSET

Definition at line 604 of file efm32jg12b_etm.h.

#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT   (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCNTRLDVR1

Definition at line 368 of file efm32jg12b_etm.h.

#define ETM_ETMCR_BRANCHOUTPUT   (0x1UL << 8)

Branch Output

Definition at line 125 of file efm32jg12b_etm.h.

#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT   (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 129 of file efm32jg12b_etm.h.

#define ETM_ETMCR_DBGREQCTRL   (0x1UL << 9)

Debug Request Control

Definition at line 130 of file efm32jg12b_etm.h.

#define ETM_ETMCR_DBGREQCTRL_DEFAULT   (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 134 of file efm32jg12b_etm.h.

#define ETM_ETMCR_EPORTSIZE_DEFAULT   (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 161 of file efm32jg12b_etm.h.

#define ETM_ETMCR_ETMPORTSEL   (0x1UL << 11)

ETM Port Selection

Definition at line 140 of file efm32jg12b_etm.h.

#define ETM_ETMCR_ETMPORTSEL_DEFAULT   (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 146 of file efm32jg12b_etm.h.

#define ETM_ETMCR_ETMPORTSEL_ETMHIGH   (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11)

Shifted mode ETMHIGH for ETM_ETMCR

Definition at line 148 of file efm32jg12b_etm.h.

#define ETM_ETMCR_ETMPORTSEL_ETMLOW   (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11)

Shifted mode ETMLOW for ETM_ETMCR

Definition at line 147 of file efm32jg12b_etm.h.

#define ETM_ETMCR_ETMPROG   (0x1UL << 10)

ETM Programming

Definition at line 135 of file efm32jg12b_etm.h.

#define ETM_ETMCR_ETMPROG_DEFAULT   (_ETM_ETMCR_ETMPROG_DEFAULT << 10)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 139 of file efm32jg12b_etm.h.

#define ETM_ETMCR_PORTMODE2   (0x1UL << 13)

Port Mode[2]

Definition at line 149 of file efm32jg12b_etm.h.

#define ETM_ETMCR_PORTMODE2_DEFAULT   (_ETM_ETMCR_PORTMODE2_DEFAULT << 13)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 153 of file efm32jg12b_etm.h.

#define ETM_ETMCR_PORTMODE_DEFAULT   (_ETM_ETMCR_PORTMODE_DEFAULT << 16)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 157 of file efm32jg12b_etm.h.

#define ETM_ETMCR_PORTSIZE_DEFAULT   (_ETM_ETMCR_PORTSIZE_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 119 of file efm32jg12b_etm.h.

#define ETM_ETMCR_POWERDWN   (0x1UL << 0)

ETM Control in low power mode

Definition at line 111 of file efm32jg12b_etm.h.

#define ETM_ETMCR_POWERDWN_DEFAULT   (_ETM_ETMCR_POWERDWN_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 115 of file efm32jg12b_etm.h.

#define ETM_ETMCR_STALL   (0x1UL << 7)

Stall Processor

Definition at line 120 of file efm32jg12b_etm.h.

#define ETM_ETMCR_STALL_DEFAULT   (_ETM_ETMCR_STALL_DEFAULT << 7)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 124 of file efm32jg12b_etm.h.

#define ETM_ETMCR_TSTAMPEN   (0x1UL << 28)

Time Stamp Enable

Definition at line 162 of file efm32jg12b_etm.h.

#define ETM_ETMCR_TSTAMPEN_DEFAULT   (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28)

Shifted mode DEFAULT for ETM_ETMCR

Definition at line 166 of file efm32jg12b_etm.h.

#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT   (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMDEVTYPE

Definition at line 672 of file efm32jg12b_etm.h.

#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT   (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMDEVTYPE

Definition at line 668 of file efm32jg12b_etm.h.

#define ETM_ETMFFLR_BYTENUM_DEFAULT   (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMFFLR

Definition at line 360 of file efm32jg12b_etm.h.

#define ETM_ETMIDR2_RFE   (0x1UL << 0)

RFE Transfer Order

Definition at line 521 of file efm32jg12b_etm.h.

#define ETM_ETMIDR2_RFE_CPSR   (_ETM_ETMIDR2_RFE_CPSR << 0)

Shifted mode CPSR for ETM_ETMIDR2

Definition at line 529 of file efm32jg12b_etm.h.

#define ETM_ETMIDR2_RFE_DEFAULT   (_ETM_ETMIDR2_RFE_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMIDR2

Definition at line 527 of file efm32jg12b_etm.h.

#define ETM_ETMIDR2_RFE_PC   (_ETM_ETMIDR2_RFE_PC << 0)

Shifted mode PC for ETM_ETMIDR2

Definition at line 528 of file efm32jg12b_etm.h.

#define ETM_ETMIDR2_SWP   (0x1UL << 1)

SWP Transfer Order

Definition at line 530 of file efm32jg12b_etm.h.

#define ETM_ETMIDR2_SWP_DEFAULT   (_ETM_ETMIDR2_SWP_DEFAULT << 1)

Shifted mode DEFAULT for ETM_ETMIDR2

Definition at line 536 of file efm32jg12b_etm.h.

#define ETM_ETMIDR2_SWP_LOAD   (_ETM_ETMIDR2_SWP_LOAD << 1)

Shifted mode LOAD for ETM_ETMIDR2

Definition at line 537 of file efm32jg12b_etm.h.

#define ETM_ETMIDR2_SWP_STORE   (_ETM_ETMIDR2_SWP_STORE << 1)

Shifted mode STORE for ETM_ETMIDR2

Definition at line 538 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_BPE   (0x1UL << 20)

Branch Packet Encoding

Definition at line 412 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_BPE_DEFAULT   (_ETM_ETMIDR_BPE_DEFAULT << 20)

Shifted mode DEFAULT for ETM_ETMIDR

Definition at line 416 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_ETMMAJVER_DEFAULT   (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8)

Shifted mode DEFAULT for ETM_ETMIDR

Definition at line 392 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_ETMMINVER_DEFAULT   (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMIDR

Definition at line 388 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_IMPCODE_DEFAULT   (_ETM_ETMIDR_IMPCODE_DEFAULT << 24)

Shifted mode DEFAULT for ETM_ETMIDR

Definition at line 420 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_IMPVER_DEFAULT   (_ETM_ETMIDR_IMPVER_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMIDR

Definition at line 384 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_LPCF   (0x1UL << 16)

Load PC First

Definition at line 397 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_LPCF_DEFAULT   (_ETM_ETMIDR_LPCF_DEFAULT << 16)

Shifted mode DEFAULT for ETM_ETMIDR

Definition at line 401 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_PROCFAM_DEFAULT   (_ETM_ETMIDR_PROCFAM_DEFAULT << 12)

Shifted mode DEFAULT for ETM_ETMIDR

Definition at line 396 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_SECEXT   (0x1UL << 19)

Security Extension Support

Definition at line 407 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_SECEXT_DEFAULT   (_ETM_ETMIDR_SECEXT_DEFAULT << 19)

Shifted mode DEFAULT for ETM_ETMIDR

Definition at line 411 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_THUMBT   (0x1UL << 18)

32-bit Thumb Instruction Tracing

Definition at line 402 of file efm32jg12b_etm.h.

#define ETM_ETMIDR_THUMBT_DEFAULT   (_ETM_ETMIDR_THUMBT_DEFAULT << 18)

Shifted mode DEFAULT for ETM_ETMIDR

Definition at line 406 of file efm32jg12b_etm.h.

#define ETM_ETMISCIN_COREHALT   (0x1UL << 4)

Core Halt

Definition at line 556 of file efm32jg12b_etm.h.

#define ETM_ETMISCIN_COREHALT_DEFAULT   (_ETM_ETMISCIN_COREHALT_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMISCIN

Definition at line 560 of file efm32jg12b_etm.h.

#define ETM_ETMISCIN_EXTIN_DEFAULT   (_ETM_ETMISCIN_EXTIN_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMISCIN

Definition at line 555 of file efm32jg12b_etm.h.

#define ETM_ETMITATBCTR0_ATVALID   (0x1UL << 0)

ATVALID Output Value

Definition at line 583 of file efm32jg12b_etm.h.

#define ETM_ETMITATBCTR0_ATVALID_DEFAULT   (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMITATBCTR0

Definition at line 587 of file efm32jg12b_etm.h.

#define ETM_ETMITATBCTR2_ATREADY   (0x1UL << 0)

ATREADY Input Value

Definition at line 574 of file efm32jg12b_etm.h.

#define ETM_ETMITATBCTR2_ATREADY_DEFAULT   (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMITATBCTR2

Definition at line 578 of file efm32jg12b_etm.h.

#define ETM_ETMITCTRL_ITEN   (0x1UL << 0)

Integration Mode Enable

Definition at line 592 of file efm32jg12b_etm.h.

#define ETM_ETMITCTRL_ITEN_DEFAULT   (_ETM_ETMITCTRL_ITEN_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMITCTRL

Definition at line 596 of file efm32jg12b_etm.h.

#define ETM_ETMLAR_KEY   (0x1UL << 0)

Key Value

Definition at line 618 of file efm32jg12b_etm.h.

#define ETM_ETMLAR_KEY_DEFAULT   (_ETM_ETMLAR_KEY_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMLAR

Definition at line 622 of file efm32jg12b_etm.h.

#define ETM_ETMLSR_LOCKED   (0x1UL << 1)

ETM locked

Definition at line 632 of file efm32jg12b_etm.h.

#define ETM_ETMLSR_LOCKED_DEFAULT   (_ETM_ETMLSR_LOCKED_DEFAULT << 1)

Shifted mode DEFAULT for ETM_ETMLSR

Definition at line 636 of file efm32jg12b_etm.h.

#define ETM_ETMLSR_LOCKIMP   (0x1UL << 0)

ETM Locking Implemented

Definition at line 627 of file efm32jg12b_etm.h.

#define ETM_ETMLSR_LOCKIMP_DEFAULT   (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMLSR

Definition at line 631 of file efm32jg12b_etm.h.

#define ETM_ETMPDSR_ETMUP   (0x1UL << 0)

ETM Powered Up

Definition at line 543 of file efm32jg12b_etm.h.

#define ETM_ETMPDSR_ETMUP_DEFAULT   (_ETM_ETMPDSR_ETMUP_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMPDSR

Definition at line 547 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR0_PARTNUM_DEFAULT   (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMPIDR0

Definition at line 704 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR1_IDCODE_DEFAULT   (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMPIDR1

Definition at line 716 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR1_PARTNUM_DEFAULT   (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMPIDR1

Definition at line 712 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR2_ALWAYS1   (0x1UL << 3)

Always 1

Definition at line 725 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR2_ALWAYS1_DEFAULT   (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3)

Shifted mode DEFAULT for ETM_ETMPIDR2

Definition at line 729 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR2_IDCODE_DEFAULT   (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMPIDR2

Definition at line 724 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR2_REV_DEFAULT   (_ETM_ETMPIDR2_REV_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMPIDR2

Definition at line 733 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR3_CUSTMOD_DEFAULT   (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMPIDR3

Definition at line 741 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR3_REVAND_DEFAULT   (_ETM_ETMPIDR3_REVAND_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMPIDR3

Definition at line 745 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR4_CONTCODE_DEFAULT   (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMPIDR4

Definition at line 680 of file efm32jg12b_etm.h.

#define ETM_ETMPIDR4_COUNT_DEFAULT   (_ETM_ETMPIDR4_COUNT_DEFAULT << 4)

Shifted mode DEFAULT for ETM_ETMPIDR4

Definition at line 684 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_FIFOFULL   (0x1UL << 8)

FIFO FULL Supported

Definition at line 278 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_FIFOFULL_DEFAULT   (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8)

Shifted mode DEFAULT for ETM_ETMSCR

Definition at line 282 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_MAXPORTSIZE3   (0x1UL << 9)

Max Port Size[3]

Definition at line 283 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT   (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9)

Shifted mode DEFAULT for ETM_ETMSCR

Definition at line 287 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT   (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMSCR

Definition at line 277 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_NOFETCHCOMP   (0x1UL << 17)

No Fetch Comparison

Definition at line 302 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT   (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17)

Shifted mode DEFAULT for ETM_ETMSCR

Definition at line 306 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_PORTMODE   (0x1UL << 11)

Port Mode Supported

Definition at line 293 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_PORTMODE_DEFAULT   (_ETM_ETMSCR_PORTMODE_DEFAULT << 11)

Shifted mode DEFAULT for ETM_ETMSCR

Definition at line 297 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_PORTSIZE   (0x1UL << 10)

Port Size Supported

Definition at line 288 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_PORTSIZE_DEFAULT   (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10)

Shifted mode DEFAULT for ETM_ETMSCR

Definition at line 292 of file efm32jg12b_etm.h.

#define ETM_ETMSCR_PROCNUM_DEFAULT   (_ETM_ETMSCR_PROCNUM_DEFAULT << 12)

Shifted mode DEFAULT for ETM_ETMSCR

Definition at line 301 of file efm32jg12b_etm.h.

#define ETM_ETMSR_ETHOF   (0x1UL << 0)

ETM Overflow

Definition at line 250 of file efm32jg12b_etm.h.

#define ETM_ETMSR_ETHOF_DEFAULT   (_ETM_ETMSR_ETHOF_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMSR

Definition at line 254 of file efm32jg12b_etm.h.

#define ETM_ETMSR_ETMPROGBIT   (0x1UL << 1)

ETM Programming Bit Status

Definition at line 255 of file efm32jg12b_etm.h.

#define ETM_ETMSR_ETMPROGBIT_DEFAULT   (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1)

Shifted mode DEFAULT for ETM_ETMSR

Definition at line 259 of file efm32jg12b_etm.h.

#define ETM_ETMSR_TRACESTAT   (0x1UL << 2)

Trace Start/Stop Status

Definition at line 260 of file efm32jg12b_etm.h.

#define ETM_ETMSR_TRACESTAT_DEFAULT   (_ETM_ETMSR_TRACESTAT_DEFAULT << 2)

Shifted mode DEFAULT for ETM_ETMSR

Definition at line 264 of file efm32jg12b_etm.h.

#define ETM_ETMSR_TRIGBIT   (0x1UL << 3)

Trigger Bit

Definition at line 265 of file efm32jg12b_etm.h.

#define ETM_ETMSR_TRIGBIT_DEFAULT   (_ETM_ETMSR_TRIGBIT_DEFAULT << 3)

Shifted mode DEFAULT for ETM_ETMSR

Definition at line 269 of file efm32jg12b_etm.h.

#define ETM_ETMSYNCFR_FREQ_DEFAULT   (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMSYNCFR

Definition at line 376 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_ADRCMP_DEFAULT   (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMTECR1

Definition at line 330 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_INCEXCTL   (0x1UL << 24)

Trace Include/Exclude Flag

Definition at line 335 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_INCEXCTL_DEFAULT   (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24)

Shifted mode DEFAULT for ETM_ETMTECR1

Definition at line 341 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_INCEXCTL_EXC   (_ETM_ETMTECR1_INCEXCTL_EXC << 24)

Shifted mode EXC for ETM_ETMTECR1

Definition at line 343 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_INCEXCTL_INC   (_ETM_ETMTECR1_INCEXCTL_INC << 24)

Shifted mode INC for ETM_ETMTECR1

Definition at line 342 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_MEMMAP_DEFAULT   (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8)

Shifted mode DEFAULT for ETM_ETMTECR1

Definition at line 334 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_TCE   (0x1UL << 25)

Trace Control Enable

Definition at line 344 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_TCE_DEFAULT   (_ETM_ETMTECR1_TCE_DEFAULT << 25)

Shifted mode DEFAULT for ETM_ETMTECR1

Definition at line 350 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_TCE_DIS   (_ETM_ETMTECR1_TCE_DIS << 25)

Shifted mode DIS for ETM_ETMTECR1

Definition at line 352 of file efm32jg12b_etm.h.

#define ETM_ETMTECR1_TCE_EN   (_ETM_ETMTECR1_TCE_EN << 25)

Shifted mode EN for ETM_ETMTECR1

Definition at line 351 of file efm32jg12b_etm.h.

#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT   (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14)

Shifted mode DEFAULT for ETM_ETMTEEVR

Definition at line 322 of file efm32jg12b_etm.h.

#define ETM_ETMTEEVR_RESA_DEFAULT   (_ETM_ETMTEEVR_RESA_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMTEEVR

Definition at line 314 of file efm32jg12b_etm.h.

#define ETM_ETMTEEVR_RESB_DEFAULT   (_ETM_ETMTEEVR_RESB_DEFAULT << 7)

Shifted mode DEFAULT for ETM_ETMTEEVR

Definition at line 318 of file efm32jg12b_etm.h.

#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT   (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMTESSEICR

Definition at line 488 of file efm32jg12b_etm.h.

#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT   (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16)

Shifted mode DEFAULT for ETM_ETMTESSEICR

Definition at line 492 of file efm32jg12b_etm.h.

#define ETM_ETMTRACEIDR_TRACEID_DEFAULT   (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMTRACEIDR

Definition at line 516 of file efm32jg12b_etm.h.

#define ETM_ETMTRIGGER_ETMFCN_DEFAULT   (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14)

Shifted mode DEFAULT for ETM_ETMTRIGGER

Definition at line 245 of file efm32jg12b_etm.h.

#define ETM_ETMTRIGGER_RESA_DEFAULT   (_ETM_ETMTRIGGER_RESA_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMTRIGGER

Definition at line 237 of file efm32jg12b_etm.h.

#define ETM_ETMTRIGGER_RESB_DEFAULT   (_ETM_ETMTRIGGER_RESB_DEFAULT << 7)

Shifted mode DEFAULT for ETM_ETMTRIGGER

Definition at line 241 of file efm32jg12b_etm.h.

#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT   (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14)

Shifted mode DEFAULT for ETM_ETMTSEVR

Definition at line 508 of file efm32jg12b_etm.h.

#define ETM_ETMTSEVR_RESAEVT_DEFAULT   (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ETMTSEVR

Definition at line 500 of file efm32jg12b_etm.h.

#define ETM_ETMTSEVR_RESBEVT_DEFAULT   (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7)

Shifted mode DEFAULT for ETM_ETMTSEVR

Definition at line 504 of file efm32jg12b_etm.h.

#define ETM_ITTRIGOUT_TRIGGEROUT   (0x1UL << 0)

Trigger output value

Definition at line 565 of file efm32jg12b_etm.h.

#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT   (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0)

Shifted mode DEFAULT for ETM_ITTRIGOUT

Definition at line 569 of file efm32jg12b_etm.h.