EFM32 Jade Gecko 12 Software Documentation  efm32jg12-doc-5.1.2
em_core.h
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1 /***************************************************************************/
32 #ifndef EM_CORE_H
33 #define EM_CORE_H
34 
35 #include "em_device.h"
36 #include "em_common.h"
37 
38 #include <stdbool.h>
39 
40 /***************************************************************************/
45 /***************************************************************************/
50 /*******************************************************************************
51  ******************************* DEFINES ***********************************
52  ******************************************************************************/
53 
55 #define CORE_ATOMIC_METHOD_PRIMASK 0
56 
58 #define CORE_ATOMIC_METHOD_BASEPRI 1
59 
61 #define CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32)
62 
64 #define CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16)
65 
66 // Compile time sanity check.
67 #if (CORE_NVIC_REG_WORDS > 3)
68 #error "em_core: Unexpected NVIC external interrupt count."
69 #endif
70 
71 #ifdef __cplusplus
72 extern "C" {
73 #endif
74 
75 /*******************************************************************************
76  ************************ MACRO API ***************************************
77  ******************************************************************************/
78 
79 //
80 // CRITICAL section macro API.
81 //
82 
85 #define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState
86 
88 #define CORE_CRITICAL_IRQ_DISABLE() CORE_CriticalDisableIrq()
89 
91 #define CORE_CRITICAL_IRQ_ENABLE() CORE_CriticalEnableIrq()
92 
94 #define CORE_CRITICAL_SECTION(yourcode) \
95 { \
96  CORE_DECLARE_IRQ_STATE; \
97  CORE_ENTER_CRITICAL(); \
98  { \
99  yourcode \
100  } \
101  CORE_EXIT_CRITICAL(); \
102 }
103 
106 #define CORE_ENTER_CRITICAL() irqState = CORE_EnterCritical()
107 
110 #define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState)
111 
113 #define CORE_YIELD_CRITICAL() CORE_YieldCritical(void)
114 
115 //
116 // ATOMIC section macro API.
117 //
118 
120 #define CORE_ATOMIC_IRQ_DISABLE() CORE_AtomicDisableIrq()
121 
123 #define CORE_ATOMIC_IRQ_ENABLE() CORE_AtomicEnableIrq()
124 
126 #define CORE_ATOMIC_SECTION(yourcode) \
127 { \
128  CORE_DECLARE_IRQ_STATE; \
129  CORE_ENTER_ATOMIC(); \
130  { \
131  yourcode \
132  } \
133  CORE_EXIT_ATOMIC(); \
134 }
135 
138 #define CORE_ENTER_ATOMIC() irqState = CORE_EnterAtomic()
139 
142 #define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState)
143 
145 #define CORE_YIELD_ATOMIC() CORE_YieldAtomic(void)
146 
147 //
148 // NVIC mask section macro API.
149 //
150 
153 #define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState
154 
158 #define CORE_DECLARE_NVIC_MASK(x) CORE_nvicMask_t x
159 
163 #define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = {{0}}
164 
168 #define CORE_NVIC_DISABLE(mask) CORE_NvicDisableMask(mask)
169 
173 #define CORE_NVIC_ENABLE(mask) CORE_NvicEnableMask(mask)
174 
180 #define CORE_NVIC_SECTION(mask, yourcode) \
181 { \
182  CORE_DECLARE_NVIC_STATE; \
183  CORE_ENTER_NVIC(mask); \
184  { \
185  yourcode \
186  } \
187  CORE_EXIT_NVIC(); \
188 }
189 
194 #define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState,disable)
195 
198 #define CORE_EXIT_NVIC() CORE_NvicEnableMask(&nvicState)
199 
203 #define CORE_YIELD_NVIC(enable) CORE_YieldNvicMask(enable)
204 
205 //
206 // Miscellaneous macros.
207 //
208 
210 #define CORE_IRQ_DISABLED() CORE_IrqIsDisabled()
211 
213 #define CORE_IN_IRQ_CONTEXT() CORE_InIrqContext()
214 
215 /*******************************************************************************
216  ************************* TYPEDEFS ****************************************
217  ******************************************************************************/
218 
220 typedef uint32_t CORE_irqState_t;
221 
223 typedef struct {
224  uint32_t a[CORE_NVIC_REG_WORDS];
226 
227 /*******************************************************************************
228  ***************************** PROTOTYPES **********************************
229  ******************************************************************************/
230 
231 void CORE_CriticalDisableIrq(void);
232 void CORE_CriticalEnableIrq(void);
233 void CORE_ExitCritical(CORE_irqState_t irqState);
234 void CORE_YieldCritical(void);
235 CORE_irqState_t CORE_EnterCritical(void);
236 
237 void CORE_AtomicDisableIrq(void);
238 void CORE_AtomicEnableIrq(void);
239 void CORE_ExitAtomic(CORE_irqState_t irqState);
240 void CORE_YieldAtomic(void);
241 CORE_irqState_t CORE_EnterAtomic(void);
242 
243 bool CORE_InIrqContext(void);
244 bool CORE_IrqIsBlocked(IRQn_Type irqN);
245 bool CORE_IrqIsDisabled(void);
246 
249 
250 void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState,
251  const CORE_nvicMask_t *disable);
252 void CORE_NvicDisableMask(const CORE_nvicMask_t *disable);
253 void CORE_NvicEnableMask(const CORE_nvicMask_t *enable);
254 void CORE_YieldNvicMask(const CORE_nvicMask_t *enable);
258 
260 void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler);
261 void CORE_InitNvicVectorTable(uint32_t *sourceTable,
262  uint32_t sourceSize,
263  uint32_t *targetTable,
264  uint32_t targetSize,
265  void *defaultHandler,
266  bool overwriteActive);
267 
268 #ifdef __cplusplus
269 }
270 #endif
271 
275 #endif /* EM_CORE_H */
bool CORE_NvicIRQDisabled(IRQn_Type irqN)
Check if a NVIC interrupt is disabled.
Definition: em_core.c:778
void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler)
Utility function to set the handler for a specific interrupt.
Definition: em_core.c:819
void CORE_CriticalDisableIrq(void)
Disable interrupts.
Definition: em_core.c:313
void CORE_YieldAtomic(void)
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
Definition: em_core.c:486
uint32_t CORE_irqState_t
Definition: em_core.h:220
void CORE_YieldNvicMask(const CORE_nvicMask_t *enable)
Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.
Definition: em_core.c:563
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)
Utility function to clear an IRQn bit in a NVIC enable/disable mask.
Definition: em_core.c:633
General purpose utilities.
void CORE_NvicDisableMask(const CORE_nvicMask_t *disable)
Disable NVIC interrupts.
Definition: em_core.c:531
bool CORE_InIrqContext(void)
Check if current cpu operation mode is handler mode.
Definition: em_core.c:647
bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask)
Get NVIC disable state for a given mask.
Definition: em_core.c:745
void CORE_ExitAtomic(CORE_irqState_t irqState)
Exit an ATOMIC section.
Definition: em_core.c:463
#define CORE_NVIC_REG_WORDS
Definition: em_core.h:61
void CORE_YieldCritical(void)
Brief interrupt enable/disable sequence to allow handling of pending interrupts.
Definition: em_core.c:370
void CORE_CriticalEnableIrq(void)
Enable interrupts.
Definition: em_core.c:324
CORE_irqState_t CORE_EnterCritical(void)
Enter a CRITICAL section.
Definition: em_core.c:339
void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask)
Get current NVIC enable mask state.
Definition: em_core.c:728
void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable)
Enter a NVIC mask section.
Definition: em_core.c:515
bool CORE_IrqIsBlocked(IRQn_Type irqN)
Check if a specific interrupt is disabled or blocked.
Definition: em_core.c:662
bool CORE_IrqIsDisabled(void)
Check if interrupts are disabled.
Definition: em_core.c:709
void CORE_InitNvicVectorTable(uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive)
Initialize an interrupt vector table by copying table entries from a source to a target table...
Definition: em_core.c:856
void * CORE_GetNvicRamTableHandler(IRQn_Type irqN)
Utility function to get the handler for a specific interrupt.
Definition: em_core.c:800
enum IRQn IRQn_Type
void CORE_AtomicEnableIrq(void)
Enable interrupts.
Definition: em_core.c:414
void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)
Utility function to set an IRQn bit in a NVIC enable/disable mask.
Definition: em_core.c:617
void CORE_NvicEnableMask(const CORE_nvicMask_t *enable)
Set current NVIC interrupt enable mask.
Definition: em_core.c:545
void CORE_ExitCritical(CORE_irqState_t irqState)
Exit a CRITICAL section.
Definition: em_core.c:355
void CORE_AtomicDisableIrq(void)
Disable interrupts.
Definition: em_core.c:390
CORE_irqState_t CORE_EnterAtomic(void)
Enter an ATOMIC section.
Definition: em_core.c:437