LDMA_TypeDef Struct Reference

Detailed Description

Definition at line 41 of file efm32jg1b_ldma.h.

Data Fields
LDMA_CH_TypeDef	CH [8]
__IM uint32_t	CHBUSY
__IOM uint32_t	CHDONE
__IOM uint32_t	CHEN
__IOM uint32_t	CTRL
__IOM uint32_t	DBGHALT
__IOM uint32_t	IEN
__IM uint32_t	IF
__IOM uint32_t	IFC
__IOM uint32_t	IFS
__IOM uint32_t	LINKLOAD
__IOM uint32_t	REQCLEAR
__IOM uint32_t	REQDIS
__IM uint32_t	REQPEND
uint32_t	RESERVED0 [5]
uint32_t	RESERVED1 [7]
uint32_t	RESERVED2 [4]
__IM uint32_t	STATUS
__IOM uint32_t	SWREQ
__IOM uint32_t	SYNC

Field Documentation

LDMA_CH_TypeDef LDMA_TypeDef::CH[8]

DMA Channel Registers

Definition at line 63 of file efm32jg1b_ldma.h.

__IM uint32_t LDMA_TypeDef::CHBUSY

DMA Channel Busy Register

Definition at line 48 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::CHDONE

DMA Channel Linking Done Register (Single-Cycle RMW)

Definition at line 49 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::CHEN

DMA Channel Enable Register (Single-Cycle RMW)

Definition at line 47 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::CTRL

DMA Control Register

Definition at line 43 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::DBGHALT

DMA Channel Debug Halt Register

Definition at line 50 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::IEN

Interrupt Enable register

Definition at line 60 of file efm32jg1b_ldma.h.

__IM uint32_t LDMA_TypeDef::IF

Interrupt Flag Register

Definition at line 57 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::IFC

Interrupt Flag Clear Register

Definition at line 59 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::IFS

Interrupt Flag Set Register

Definition at line 58 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::LINKLOAD

DMA Channel Link Load Register

Definition at line 54 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::REQCLEAR

DMA Channel Request Clear Register

Definition at line 55 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::REQDIS

DMA Channel Request Disable Register

Definition at line 52 of file efm32jg1b_ldma.h.

__IM uint32_t LDMA_TypeDef::REQPEND

DMA Channel Requests Pending Register

Definition at line 53 of file efm32jg1b_ldma.h.

uint32_t LDMA_TypeDef::RESERVED0[5]

Reserved for future use

Definition at line 46 of file efm32jg1b_ldma.h.

uint32_t LDMA_TypeDef::RESERVED1[7]

Reserved for future use

Definition at line 56 of file efm32jg1b_ldma.h.

uint32_t LDMA_TypeDef::RESERVED2[4]

Reserved registers

Definition at line 62 of file efm32jg1b_ldma.h.

__IM uint32_t LDMA_TypeDef::STATUS

DMA Status Register

Definition at line 44 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::SWREQ

DMA Channel Software Transfer Request Register

Definition at line 51 of file efm32jg1b_ldma.h.

__IOM uint32_t LDMA_TypeDef::SYNC

DMA Synchronization Trigger Register (Single-Cycle RMW)

Definition at line 45 of file efm32jg1b_ldma.h.

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The documentation for this struct was generated from the following file:

• D:/jenkins-slave/workspaces/Executor-0/super/platform/Device/SiliconLabs/EFM32JG1B/Include/efm32jg1b_ldma.h