efm32jg1/html/efm32jg1b__devinfo_8h_source.html

 /**************************************************************************/

 /**************************************************************************/

 /**************************************************************************/

 typedef struct

 {

   __IM uint32_t CAL;

   uint32_t      RESERVED0[9];

   __IM uint32_t EUI48L;

   __IM uint32_t EUI48H;

   __IM uint32_t CUSTOMINFO;

   __IM uint32_t MEMINFO;

   uint32_t      RESERVED1[2];

   __IM uint32_t UNIQUEL;

   __IM uint32_t UNIQUEH;

   __IM uint32_t MSIZE;

   __IM uint32_t PART;

   __IM uint32_t DEVINFOREV;

   __IM uint32_t EMUTEMP;

   uint32_t      RESERVED2[2];

   __IM uint32_t ADC0CAL0;

   __IM uint32_t ADC0CAL1;

   __IM uint32_t ADC0CAL2;

   __IM uint32_t ADC0CAL3;

   uint32_t      RESERVED3[4];

   __IM uint32_t HFRCOCAL0;

   uint32_t      RESERVED4[2];

   __IM uint32_t HFRCOCAL3;

   uint32_t      RESERVED5[2];

   __IM uint32_t HFRCOCAL6;

   __IM uint32_t HFRCOCAL7;

   __IM uint32_t HFRCOCAL8;

   uint32_t      RESERVED6[1];

   __IM uint32_t HFRCOCAL10;

   __IM uint32_t HFRCOCAL11;

   __IM uint32_t HFRCOCAL12;

   uint32_t      RESERVED7[11];

   __IM uint32_t AUXHFRCOCAL0;

   uint32_t      RESERVED8[2];

   __IM uint32_t AUXHFRCOCAL3;

   uint32_t      RESERVED9[2];

   __IM uint32_t AUXHFRCOCAL6;

   __IM uint32_t AUXHFRCOCAL7;

   __IM uint32_t AUXHFRCOCAL8;

   uint32_t      RESERVED10[1];

   __IM uint32_t AUXHFRCOCAL10;

   __IM uint32_t AUXHFRCOCAL11;

   __IM uint32_t AUXHFRCOCAL12;

   uint32_t      RESERVED11[11];

   __IM uint32_t VMONCAL0;

   __IM uint32_t VMONCAL1;

   __IM uint32_t VMONCAL2;

   uint32_t      RESERVED12[3];

   __IM uint32_t IDAC0CAL0;

   __IM uint32_t IDAC0CAL1;

   uint32_t      RESERVED13[2];

   __IM uint32_t DCDCLNVCTRL0;

   __IM uint32_t DCDCLPVCTRL0;

   __IM uint32_t DCDCLPVCTRL1;

   __IM uint32_t DCDCLPVCTRL2;

   __IM uint32_t DCDCLPVCTRL3;

   __IM uint32_t DCDCLPCMPHYSSEL0;

   __IM uint32_t DCDCLPCMPHYSSEL1;

 } DEVINFO_TypeDef;

 /**************************************************************************/

 /* Bit fields for DEVINFO CAL */

 #define _DEVINFO_CAL_MASK                                        0x00FFFFFFUL

 #define _DEVINFO_CAL_CRC_SHIFT                                   0

 #define _DEVINFO_CAL_CRC_MASK                                    0xFFFFUL

 #define _DEVINFO_CAL_TEMP_SHIFT                                  16

 #define _DEVINFO_CAL_TEMP_MASK                                   0xFF0000UL

 /* Bit fields for DEVINFO EUI48L */

 #define _DEVINFO_EUI48L_MASK                                     0xFFFFFFFFUL

 #define _DEVINFO_EUI48L_UNIQUEID_SHIFT                           0

 #define _DEVINFO_EUI48L_UNIQUEID_MASK                            0xFFFFFFUL

 #define _DEVINFO_EUI48L_OUI48L_SHIFT                             24

 #define _DEVINFO_EUI48L_OUI48L_MASK                              0xFF000000UL

 /* Bit fields for DEVINFO EUI48H */

 #define _DEVINFO_EUI48H_MASK                                     0x0000FFFFUL

 #define _DEVINFO_EUI48H_OUI48H_SHIFT                             0

 #define _DEVINFO_EUI48H_OUI48H_MASK                              0xFFFFUL

 /* Bit fields for DEVINFO CUSTOMINFO */

 #define _DEVINFO_CUSTOMINFO_MASK                                 0xFFFF0000UL

 #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT                         16

 #define _DEVINFO_CUSTOMINFO_PARTNO_MASK                          0xFFFF0000UL

 /* Bit fields for DEVINFO MEMINFO */

 #define _DEVINFO_MEMINFO_MASK                                    0xFFFFFFFFUL

 #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT                         0

 #define _DEVINFO_MEMINFO_TEMPGRADE_MASK                          0xFFUL

 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85                       0x00000000UL

 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125                      0x00000001UL

 #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105                      0x00000002UL

 #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70                        0x00000003UL

 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85                        (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0)

 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125                       (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0)

 #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105                       (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0)

 #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70                         (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0)

 #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT                           8

 #define _DEVINFO_MEMINFO_PKGTYPE_MASK                            0xFF00UL

 #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP                           0x0000004AUL

 #define _DEVINFO_MEMINFO_PKGTYPE_QFN                             0x0000004DUL

 #define _DEVINFO_MEMINFO_PKGTYPE_QFP                             0x00000051UL

 #define DEVINFO_MEMINFO_PKGTYPE_WLCSP                            (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8)

 #define DEVINFO_MEMINFO_PKGTYPE_QFN                              (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8)

 #define DEVINFO_MEMINFO_PKGTYPE_QFP                              (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8)

 #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT                          16

 #define _DEVINFO_MEMINFO_PINCOUNT_MASK                           0xFF0000UL

 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT                   24

 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK                    0xFF000000UL

 /* Bit fields for DEVINFO UNIQUEL */

 #define _DEVINFO_UNIQUEL_MASK                                    0xFFFFFFFFUL

 #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT                           0

 #define _DEVINFO_UNIQUEL_UNIQUEL_MASK                            0xFFFFFFFFUL

 /* Bit fields for DEVINFO UNIQUEH */

 #define _DEVINFO_UNIQUEH_MASK                                    0xFFFFFFFFUL

 #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT                           0

 #define _DEVINFO_UNIQUEH_UNIQUEH_MASK                            0xFFFFFFFFUL

 /* Bit fields for DEVINFO MSIZE */

 #define _DEVINFO_MSIZE_MASK                                      0xFFFFFFFFUL

 #define _DEVINFO_MSIZE_FLASH_SHIFT                               0

 #define _DEVINFO_MSIZE_FLASH_MASK                                0xFFFFUL

 #define _DEVINFO_MSIZE_SRAM_SHIFT                                16

 #define _DEVINFO_MSIZE_SRAM_MASK                                 0xFFFF0000UL

 /* Bit fields for DEVINFO PART */

 #define _DEVINFO_PART_MASK                                       0xFFFFFFFFUL

 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT                        0

 #define _DEVINFO_PART_DEVICE_NUMBER_MASK                         0xFFFFUL

 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT                        16

 #define _DEVINFO_PART_DEVICE_FAMILY_MASK                         0xFF0000UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P                    0x00000010UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B                    0x00000011UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V                    0x00000012UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P                    0x00000013UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B                    0x00000014UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V                    0x00000015UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P                    0x00000019UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B                    0x0000001AUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V                    0x0000001BUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P                   0x0000001CUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P                    0x0000001CUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B                   0x0000001DUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V                   0x0000001EUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P                   0x0000001FUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B                   0x00000020UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V                   0x00000021UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P                   0x00000025UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B                   0x00000026UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V                   0x00000027UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P                   0x00000028UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B                   0x00000029UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V                   0x0000002AUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P                   0x0000002BUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B                   0x0000002CUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V                   0x0000002DUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P                   0x00000031UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B                   0x00000032UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V                   0x00000033UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G                       0x00000047UL

 #define _DEVINFO_PART_DEVICE_FAMILY_G                            0x00000047UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG                      0x00000048UL

 #define _DEVINFO_PART_DEVICE_FAMILY_GG                           0x00000048UL

 #define _DEVINFO_PART_DEVICE_FAMILY_TG                           0x00000049UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG                      0x00000049UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG                      0x0000004AUL

 #define _DEVINFO_PART_DEVICE_FAMILY_LG                           0x0000004AUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG                      0x0000004BUL

 #define _DEVINFO_PART_DEVICE_FAMILY_WG                           0x0000004BUL

 #define _DEVINFO_PART_DEVICE_FAMILY_ZG                           0x0000004CUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG                      0x0000004CUL

 #define _DEVINFO_PART_DEVICE_FAMILY_HG                           0x0000004DUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG                      0x0000004DUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B                    0x00000051UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B                    0x00000053UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B                   0x00000055UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B                   0x00000057UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B                   0x00000059UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B                   0x0000005BUL

 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG                      0x00000078UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG                      0x00000079UL

 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG                      0x0000007AUL

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P                     (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V                    (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32G                        (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_G                             (_DEVINFO_PART_DEVICE_FAMILY_G << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_GG                            (_DEVINFO_PART_DEVICE_FAMILY_GG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_TG                            (_DEVINFO_PART_DEVICE_FAMILY_TG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_LG                            (_DEVINFO_PART_DEVICE_FAMILY_LG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_WG                            (_DEVINFO_PART_DEVICE_FAMILY_WG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_ZG                            (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_HG                            (_DEVINFO_PART_DEVICE_FAMILY_HG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG                       (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B                     (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B                    (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B                    (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B                    (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B                    (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG                       (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG                       (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16)

 #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG                       (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16)

 #define _DEVINFO_PART_PROD_REV_SHIFT                             24

 #define _DEVINFO_PART_PROD_REV_MASK                              0xFF000000UL

 /* Bit fields for DEVINFO DEVINFOREV */

 #define _DEVINFO_DEVINFOREV_MASK                                 0x000000FFUL

 #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT                     0

 #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK                      0xFFUL

 /* Bit fields for DEVINFO EMUTEMP */

 #define _DEVINFO_EMUTEMP_MASK                                    0x000000FFUL

 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT                       0

 #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK                        0xFFUL

 /* Bit fields for DEVINFO ADC0CAL0 */

 #define _DEVINFO_ADC0CAL0_MASK                                   0x7FFF7FFFUL

 #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT                       0

 #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK                        0xFUL

 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT                  4

 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK                   0xF0UL

 #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT                         8

 #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK                          0x7F00UL

 #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT                        16

 #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK                         0xF0000UL

 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT                   20

 #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK                    0xF00000UL

 #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT                          24

 #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK                           0x7F000000UL

 /* Bit fields for DEVINFO ADC0CAL1 */

 #define _DEVINFO_ADC0CAL1_MASK                                   0x7FFF7FFFUL

 #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT                        0

 #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK                         0xFUL

 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT                   4

 #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK                    0xF0UL

 #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT                          8

 #define _DEVINFO_ADC0CAL1_GAINVDD_MASK                           0x7F00UL

 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT                     16

 #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK                      0xF0000UL

 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT                20

 #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK                 0xF00000UL

 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT                       24

 #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK                        0x7F000000UL

 /* Bit fields for DEVINFO ADC0CAL2 */

 #define _DEVINFO_ADC0CAL2_MASK                                   0x000000FFUL

 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT                      0

 #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK                       0xFUL

 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT                 4

 #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK                  0xF0UL

 /* Bit fields for DEVINFO ADC0CAL3 */

 #define _DEVINFO_ADC0CAL3_MASK                                   0x0000FFF0UL

 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT                     4

 #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK                      0xFFF0UL

 /* Bit fields for DEVINFO HFRCOCAL0 */

 #define _DEVINFO_HFRCOCAL0_MASK                                  0xFFFF3F7FUL

 #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT                          0

 #define _DEVINFO_HFRCOCAL0_TUNING_MASK                           0x7FUL

 #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT                      8

 #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK                       0x3F00UL

 #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT                       16

 #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK                        0x1F0000UL

 #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT                         21

 #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK                          0xE00000UL

 #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT                           24

 #define _DEVINFO_HFRCOCAL0_LDOHP_MASK                            0x1000000UL

 #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT                          25

 #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK                           0x6000000UL

 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT                    27

 #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK                     0x8000000UL

 #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT                          28

 #define _DEVINFO_HFRCOCAL0_VREFTC_MASK                           0xF0000000UL

 /* Bit fields for DEVINFO HFRCOCAL3 */

 #define _DEVINFO_HFRCOCAL3_MASK                                  0xFFFF3F7FUL

 #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT                          0

 #define _DEVINFO_HFRCOCAL3_TUNING_MASK                           0x7FUL

 #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT                      8

 #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK                       0x3F00UL

 #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT                       16

 #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK                        0x1F0000UL

 #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT                         21

 #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK                          0xE00000UL

 #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT                           24

 #define _DEVINFO_HFRCOCAL3_LDOHP_MASK                            0x1000000UL

 #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT                          25

 #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK                           0x6000000UL

 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT                    27

 #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK                     0x8000000UL

 #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT                          28

 #define _DEVINFO_HFRCOCAL3_VREFTC_MASK                           0xF0000000UL

 /* Bit fields for DEVINFO HFRCOCAL6 */

 #define _DEVINFO_HFRCOCAL6_MASK                                  0xFFFF3F7FUL

 #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT                          0

 #define _DEVINFO_HFRCOCAL6_TUNING_MASK                           0x7FUL

 #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT                      8

 #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK                       0x3F00UL

 #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT                       16

 #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK                        0x1F0000UL

 #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT                         21

 #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK                          0xE00000UL

 #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT                           24

 #define _DEVINFO_HFRCOCAL6_LDOHP_MASK                            0x1000000UL

 #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT                          25

 #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK                           0x6000000UL

 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT                    27

 #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK                     0x8000000UL

 #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT                          28

 #define _DEVINFO_HFRCOCAL6_VREFTC_MASK                           0xF0000000UL

 /* Bit fields for DEVINFO HFRCOCAL7 */

 #define _DEVINFO_HFRCOCAL7_MASK                                  0xFFFF3F7FUL

 #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT                          0

 #define _DEVINFO_HFRCOCAL7_TUNING_MASK                           0x7FUL

 #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT                      8

 #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK                       0x3F00UL

 #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT                       16

 #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK                        0x1F0000UL

 #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT                         21

 #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK                          0xE00000UL

 #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT                           24

 #define _DEVINFO_HFRCOCAL7_LDOHP_MASK                            0x1000000UL

 #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT                          25

 #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK                           0x6000000UL

 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT                    27

 #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK                     0x8000000UL

 #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT                          28

 #define _DEVINFO_HFRCOCAL7_VREFTC_MASK                           0xF0000000UL

 /* Bit fields for DEVINFO HFRCOCAL8 */

 #define _DEVINFO_HFRCOCAL8_MASK                                  0xFFFF3F7FUL

 #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT                          0

 #define _DEVINFO_HFRCOCAL8_TUNING_MASK                           0x7FUL

 #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT                      8

 #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK                       0x3F00UL

 #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT                       16

 #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK                        0x1F0000UL

 #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT                         21

 #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK                          0xE00000UL

 #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT                           24

 #define _DEVINFO_HFRCOCAL8_LDOHP_MASK                            0x1000000UL

 #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT                          25

 #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK                           0x6000000UL

 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT                    27

 #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK                     0x8000000UL

 #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT                          28

 #define _DEVINFO_HFRCOCAL8_VREFTC_MASK                           0xF0000000UL

 /* Bit fields for DEVINFO HFRCOCAL10 */

 #define _DEVINFO_HFRCOCAL10_MASK                                 0xFFFF3F7FUL

 #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT                         0

 #define _DEVINFO_HFRCOCAL10_TUNING_MASK                          0x7FUL

 #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT                     8

 #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK                      0x3F00UL

 #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT                      16

 #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK                       0x1F0000UL

 #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT                        21

 #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK                         0xE00000UL

 #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT                          24

 #define _DEVINFO_HFRCOCAL10_LDOHP_MASK                           0x1000000UL

 #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT                         25

 #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK                          0x6000000UL

 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT                   27

 #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK                    0x8000000UL

 #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT                         28

 #define _DEVINFO_HFRCOCAL10_VREFTC_MASK                          0xF0000000UL

 /* Bit fields for DEVINFO HFRCOCAL11 */

 #define _DEVINFO_HFRCOCAL11_MASK                                 0xFFFF3F7FUL

 #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT                         0

 #define _DEVINFO_HFRCOCAL11_TUNING_MASK                          0x7FUL

 #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT                     8

 #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK                      0x3F00UL

 #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT                      16

 #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK                       0x1F0000UL

 #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT                        21

 #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK                         0xE00000UL

 #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT                          24

 #define _DEVINFO_HFRCOCAL11_LDOHP_MASK                           0x1000000UL

 #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT                         25

 #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK                          0x6000000UL

 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT                   27

 #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK                    0x8000000UL

 #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT                         28

 #define _DEVINFO_HFRCOCAL11_VREFTC_MASK                          0xF0000000UL

 /* Bit fields for DEVINFO HFRCOCAL12 */

 #define _DEVINFO_HFRCOCAL12_MASK                                 0xFFFF3F7FUL

 #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT                         0

 #define _DEVINFO_HFRCOCAL12_TUNING_MASK                          0x7FUL

 #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT                     8

 #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK                      0x3F00UL

 #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT                      16

 #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK                       0x1F0000UL

 #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT                        21

 #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK                         0xE00000UL

 #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT                          24

 #define _DEVINFO_HFRCOCAL12_LDOHP_MASK                           0x1000000UL

 #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT                         25

 #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK                          0x6000000UL

 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT                   27

 #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK                    0x8000000UL

 #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT                         28

 #define _DEVINFO_HFRCOCAL12_VREFTC_MASK                          0xF0000000UL

 /* Bit fields for DEVINFO AUXHFRCOCAL0 */

 #define _DEVINFO_AUXHFRCOCAL0_MASK                               0xFFFF3F7FUL

 #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT                       0

 #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK                        0x7FUL

 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT                   8

 #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK                    0x3F00UL

 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT                    16

 #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK                     0x1F0000UL

 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT                      21

 #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK                       0xE00000UL

 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT                        24

 #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK                         0x1000000UL

 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT                       25

 #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK                        0x6000000UL

 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT                 27

 #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK                  0x8000000UL

 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT                       28

 #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK                        0xF0000000UL

 /* Bit fields for DEVINFO AUXHFRCOCAL3 */

 #define _DEVINFO_AUXHFRCOCAL3_MASK                               0xFFFF3F7FUL

 #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT                       0

 #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK                        0x7FUL

 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT                   8

 #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK                    0x3F00UL

 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT                    16

 #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK                     0x1F0000UL

 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT                      21

 #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK                       0xE00000UL

 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT                        24

 #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK                         0x1000000UL

 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT                       25

 #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK                        0x6000000UL

 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT                 27

 #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK                  0x8000000UL

 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT                       28

 #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK                        0xF0000000UL

 /* Bit fields for DEVINFO AUXHFRCOCAL6 */

 #define _DEVINFO_AUXHFRCOCAL6_MASK                               0xFFFF3F7FUL

 #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT                       0

 #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK                        0x7FUL

 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT                   8

 #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK                    0x3F00UL

 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT                    16

 #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK                     0x1F0000UL

 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT                      21

 #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK                       0xE00000UL

 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT                        24

 #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK                         0x1000000UL

 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT                       25

 #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK                        0x6000000UL

 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT                 27

 #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK                  0x8000000UL

 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT                       28

 #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK                        0xF0000000UL

 /* Bit fields for DEVINFO AUXHFRCOCAL7 */

 #define _DEVINFO_AUXHFRCOCAL7_MASK                               0xFFFF3F7FUL

 #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT                       0

 #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK                        0x7FUL

 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT                   8

 #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK                    0x3F00UL

 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT                    16

 #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK                     0x1F0000UL

 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT                      21

 #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK                       0xE00000UL

 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT                        24

 #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK                         0x1000000UL

 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT                       25

 #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK                        0x6000000UL

 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT                 27

 #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK                  0x8000000UL

 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT                       28

 #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK                        0xF0000000UL

 /* Bit fields for DEVINFO AUXHFRCOCAL8 */

 #define _DEVINFO_AUXHFRCOCAL8_MASK                               0xFFFF3F7FUL

 #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT                       0

 #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK                        0x7FUL

 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT                   8

 #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK                    0x3F00UL

 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT                    16

 #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK                     0x1F0000UL

 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT                      21

 #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK                       0xE00000UL

 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT                        24

 #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK                         0x1000000UL

 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT                       25

 #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK                        0x6000000UL

 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT                 27

 #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK                  0x8000000UL

 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT                       28

 #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK                        0xF0000000UL

 /* Bit fields for DEVINFO AUXHFRCOCAL10 */

 #define _DEVINFO_AUXHFRCOCAL10_MASK                              0xFFFF3F7FUL

 #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT                      0

 #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK                       0x7FUL

 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT                  8

 #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK                   0x3F00UL

 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT                   16

 #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK                    0x1F0000UL

 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT                     21

 #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK                      0xE00000UL

 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT                       24

 #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK                        0x1000000UL

 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT                      25

 #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK                       0x6000000UL

 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT                27

 #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK                 0x8000000UL

 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT                      28

 #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK                       0xF0000000UL

 /* Bit fields for DEVINFO AUXHFRCOCAL11 */

 #define _DEVINFO_AUXHFRCOCAL11_MASK                              0xFFFF3F7FUL

 #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT                      0

 #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK                       0x7FUL

 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT                  8

 #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK                   0x3F00UL

 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT                   16

 #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK                    0x1F0000UL

 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT                     21

 #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK                      0xE00000UL

 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT                       24

 #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK                        0x1000000UL

 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT                      25

 #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK                       0x6000000UL

 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT                27

 #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK                 0x8000000UL

 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT                      28

 #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK                       0xF0000000UL

 /* Bit fields for DEVINFO AUXHFRCOCAL12 */

 #define _DEVINFO_AUXHFRCOCAL12_MASK                              0xFFFF3F7FUL

 #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT                      0

 #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK                       0x7FUL

 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT                  8

 #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK                   0x3F00UL

 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT                   16

 #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK                    0x1F0000UL

 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT                     21

 #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK                      0xE00000UL

 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT                       24

 #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK                        0x1000000UL

 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT                      25

 #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK                       0x6000000UL

 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT                27

 #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK                 0x8000000UL

 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT                      28

 #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK                       0xF0000000UL

 /* Bit fields for DEVINFO VMONCAL0 */

 #define _DEVINFO_VMONCAL0_MASK                                   0xFFFFFFFFUL

 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT                0

 #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK                 0xFUL

 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT              4

 #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK               0xF0UL

 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT                8

 #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK                 0xF00UL

 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT              12

 #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK               0xF000UL

 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT             16

 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK              0xF0000UL

 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT           20

 #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK            0xF00000UL

 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT             24

 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK              0xF000000UL

 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT           28

 #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK            0xF0000000UL

 /* Bit fields for DEVINFO VMONCAL1 */

 #define _DEVINFO_VMONCAL1_MASK                                   0xFFFFFFFFUL

 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT                0

 #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK                 0xFUL

 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT              4

 #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK               0xF0UL

 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT                8

 #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK                 0xF00UL

 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT              12

 #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK               0xF000UL

 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT                 16

 #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK                  0xF0000UL

 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT               20

 #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK                0xF00000UL

 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT                 24

 #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK                  0xF000000UL

 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT               28

 #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK                0xF0000000UL

 /* Bit fields for DEVINFO VMONCAL2 */

 #define _DEVINFO_VMONCAL2_MASK                                   0xFFFFFFFFUL

 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT               0

 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK                0xFUL

 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT             4

 #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK              0xF0UL

 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT               8

 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK                0xF00UL

 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT             12

 #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK              0xF000UL

 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT                16

 #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK                 0xF0000UL

 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT              20

 #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK               0xF00000UL

 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT                24

 #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK                 0xF000000UL

 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT              28

 #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK               0xF0000000UL

 /* Bit fields for DEVINFO IDAC0CAL0 */

 #define _DEVINFO_IDAC0CAL0_MASK                                  0xFFFFFFFFUL

 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT              0

 #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK               0xFFUL

 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT              8

 #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK               0xFF00UL

 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT              16

 #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK               0xFF0000UL

 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT              24

 #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK               0xFF000000UL

 /* Bit fields for DEVINFO IDAC0CAL1 */

 #define _DEVINFO_IDAC0CAL1_MASK                                  0xFFFFFFFFUL

 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT                0

 #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK                 0xFFUL

 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT                8

 #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK                 0xFF00UL

 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT                16

 #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK                 0xFF0000UL

 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT                24

 #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK                 0xFF000000UL

 /* Bit fields for DEVINFO DCDCLNVCTRL0 */

 #define _DEVINFO_DCDCLNVCTRL0_MASK                               0xFFFFFFFFUL

 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT                    0

 #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK                     0xFFUL

 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT                    8

 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK                     0xFF00UL

 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT                    16

 #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK                     0xFF0000UL

 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT                    24

 #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK                     0xFF000000UL

 /* Bit fields for DEVINFO DCDCLPVCTRL0 */

 #define _DEVINFO_DCDCLPVCTRL0_MASK                               0xFFFFFFFFUL

 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT          0

 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK           0xFFUL

 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT          8

 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK           0xFF00UL

 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT          16

 #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK           0xFF0000UL

 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT          24

 #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK           0xFF000000UL

 /* Bit fields for DEVINFO DCDCLPVCTRL1 */

 #define _DEVINFO_DCDCLPVCTRL1_MASK                               0xFFFFFFFFUL

 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT          0

 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK           0xFFUL

 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT          8

 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK           0xFF00UL

 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT          16

 #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK           0xFF0000UL

 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT          24

 #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK           0xFF000000UL

 /* Bit fields for DEVINFO DCDCLPVCTRL2 */

 #define _DEVINFO_DCDCLPVCTRL2_MASK                               0xFFFFFFFFUL

 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT          0

 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK           0xFFUL

 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT          8

 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK           0xFF00UL

 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT          16

 #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK           0xFF0000UL

 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT          24

 #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK           0xFF000000UL

 /* Bit fields for DEVINFO DCDCLPVCTRL3 */

 #define _DEVINFO_DCDCLPVCTRL3_MASK                               0xFFFFFFFFUL

 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT          0

 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK           0xFFUL

 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT          8

 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK           0xFF00UL

 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT          16

 #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK           0xFF0000UL

 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT          24

 #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK           0xFF000000UL

 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */

 #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK                           0x0000FFFFUL

 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT        0

 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK         0xFFUL

 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT        8

 #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK         0xFF00UL

 /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */

 #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK                           0xFFFFFFFFUL

 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT    0

 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK     0xFFUL

 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT    8

 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK     0xFF00UL

 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT    16

 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK     0xFF0000UL

 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT    24

 #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK     0xFF000000UL

DEVINFO_TypeDef::UNIQUEH
__IM uint32_t UNIQUEH
Definition: efm32jg1b_devinfo.h:51

DEVINFO_TypeDef::HFRCOCAL12
__IM uint32_t HFRCOCAL12
Definition: efm32jg1b_devinfo.h:72

DEVINFO_TypeDef::DCDCLPVCTRL1
__IM uint32_t DCDCLPVCTRL1
Definition: efm32jg1b_devinfo.h:95

DEVINFO_TypeDef::EUI48L
__IM uint32_t EUI48L
Definition: efm32jg1b_devinfo.h:45

DEVINFO_TypeDef::AUXHFRCOCAL11
__IM uint32_t AUXHFRCOCAL11
Definition: efm32jg1b_devinfo.h:83

DEVINFO_TypeDef::AUXHFRCOCAL8
__IM uint32_t AUXHFRCOCAL8
Definition: efm32jg1b_devinfo.h:80

DEVINFO_TypeDef::EUI48H
__IM uint32_t EUI48H
Definition: efm32jg1b_devinfo.h:46

DEVINFO_TypeDef::VMONCAL1
__IM uint32_t VMONCAL1
Definition: efm32jg1b_devinfo.h:87

DEVINFO_TypeDef::HFRCOCAL10
__IM uint32_t HFRCOCAL10
Definition: efm32jg1b_devinfo.h:70

DEVINFO_TypeDef::AUXHFRCOCAL6
__IM uint32_t AUXHFRCOCAL6
Definition: efm32jg1b_devinfo.h:78

DEVINFO_TypeDef::DCDCLPVCTRL2
__IM uint32_t DCDCLPVCTRL2
Definition: efm32jg1b_devinfo.h:96

DEVINFO_TypeDef::DCDCLPCMPHYSSEL0
__IM uint32_t DCDCLPCMPHYSSEL0
Definition: efm32jg1b_devinfo.h:98

DEVINFO_TypeDef::DCDCLPCMPHYSSEL1
__IM uint32_t DCDCLPCMPHYSSEL1
Definition: efm32jg1b_devinfo.h:99

DEVINFO_TypeDef::IDAC0CAL1
__IM uint32_t IDAC0CAL1
Definition: efm32jg1b_devinfo.h:91

DEVINFO_TypeDef::EMUTEMP
__IM uint32_t EMUTEMP
Definition: efm32jg1b_devinfo.h:55

DEVINFO_TypeDef::HFRCOCAL3
__IM uint32_t HFRCOCAL3
Definition: efm32jg1b_devinfo.h:64

DEVINFO_TypeDef::AUXHFRCOCAL0
__IM uint32_t AUXHFRCOCAL0
Definition: efm32jg1b_devinfo.h:74

DEVINFO_TypeDef::DCDCLPVCTRL3
__IM uint32_t DCDCLPVCTRL3
Definition: efm32jg1b_devinfo.h:97

DEVINFO_TypeDef::AUXHFRCOCAL7
__IM uint32_t AUXHFRCOCAL7
Definition: efm32jg1b_devinfo.h:79

DEVINFO_TypeDef::AUXHFRCOCAL10
__IM uint32_t AUXHFRCOCAL10
Definition: efm32jg1b_devinfo.h:82

DEVINFO_TypeDef::ADC0CAL3
__IM uint32_t ADC0CAL3
Definition: efm32jg1b_devinfo.h:60

DEVINFO_TypeDef::CUSTOMINFO
__IM uint32_t CUSTOMINFO
Definition: efm32jg1b_devinfo.h:47

DEVINFO_TypeDef::HFRCOCAL7
__IM uint32_t HFRCOCAL7
Definition: efm32jg1b_devinfo.h:67

DEVINFO_TypeDef::AUXHFRCOCAL3
__IM uint32_t AUXHFRCOCAL3
Definition: efm32jg1b_devinfo.h:76

DEVINFO_TypeDef::VMONCAL0
__IM uint32_t VMONCAL0
Definition: efm32jg1b_devinfo.h:86

DEVINFO_TypeDef::MSIZE
__IM uint32_t MSIZE
Definition: efm32jg1b_devinfo.h:52

DEVINFO_TypeDef::DCDCLNVCTRL0
__IM uint32_t DCDCLNVCTRL0
Definition: efm32jg1b_devinfo.h:93

DEVINFO_TypeDef
Definition: efm32jg1b_devinfo.h:41

DEVINFO_TypeDef::ADC0CAL0
__IM uint32_t ADC0CAL0
Definition: efm32jg1b_devinfo.h:57

DEVINFO_TypeDef::HFRCOCAL6
__IM uint32_t HFRCOCAL6
Definition: efm32jg1b_devinfo.h:66

DEVINFO_TypeDef::MEMINFO
__IM uint32_t MEMINFO
Definition: efm32jg1b_devinfo.h:48

DEVINFO_TypeDef::IDAC0CAL0
__IM uint32_t IDAC0CAL0
Definition: efm32jg1b_devinfo.h:90

DEVINFO_TypeDef::HFRCOCAL11
__IM uint32_t HFRCOCAL11
Definition: efm32jg1b_devinfo.h:71

DEVINFO_TypeDef::ADC0CAL1
__IM uint32_t ADC0CAL1
Definition: efm32jg1b_devinfo.h:58

DEVINFO_TypeDef::DEVINFOREV
__IM uint32_t DEVINFOREV
Definition: efm32jg1b_devinfo.h:54

DEVINFO_TypeDef::VMONCAL2
__IM uint32_t VMONCAL2
Definition: efm32jg1b_devinfo.h:88

DEVINFO_TypeDef::PART
__IM uint32_t PART
Definition: efm32jg1b_devinfo.h:53

DEVINFO_TypeDef::HFRCOCAL8
__IM uint32_t HFRCOCAL8
Definition: efm32jg1b_devinfo.h:68

DEVINFO_TypeDef::AUXHFRCOCAL12
__IM uint32_t AUXHFRCOCAL12
Definition: efm32jg1b_devinfo.h:84

DEVINFO_TypeDef::UNIQUEL
__IM uint32_t UNIQUEL
Definition: efm32jg1b_devinfo.h:50

DEVINFO_TypeDef::CAL
__IM uint32_t CAL
Definition: efm32jg1b_devinfo.h:43

DEVINFO_TypeDef::ADC0CAL2
__IM uint32_t ADC0CAL2
Definition: efm32jg1b_devinfo.h:59

DEVINFO_TypeDef::HFRCOCAL0
__IM uint32_t HFRCOCAL0
Definition: efm32jg1b_devinfo.h:62

DEVINFO_TypeDef::DCDCLPVCTRL0
__IM uint32_t DCDCLPVCTRL0
Definition: efm32jg1b_devinfo.h:94