efm32jg1b200f256gm48.h

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/**************************************************************************/
#ifndef EFM32JG1B200F256GM48_H
#define EFM32JG1B200F256GM48_H

#ifdef __cplusplus
extern "C" {
#endif

/**************************************************************************/
/**************************************************************************/
typedef enum IRQn
{
/******  Cortex-M3 Processor Exceptions Numbers ********************************************/
  NonMaskableInt_IRQn   = -14,              
  HardFault_IRQn        = -13,              
  MemoryManagement_IRQn = -12,              
  BusFault_IRQn         = -11,              
  UsageFault_IRQn       = -10,              
  SVCall_IRQn           = -5,               
  DebugMonitor_IRQn     = -4,               
  PendSV_IRQn           = -2,               
  SysTick_IRQn          = -1,               
/******  EFM32JG1B Peripheral Interrupt Numbers ********************************************/

  EMU_IRQn              = 0,  
  WDOG0_IRQn            = 2,  
  LDMA_IRQn             = 8,  
  GPIO_EVEN_IRQn        = 9,  
  TIMER0_IRQn           = 10, 
  USART0_RX_IRQn        = 11, 
  USART0_TX_IRQn        = 12, 
  ACMP0_IRQn            = 13, 
  ADC0_IRQn             = 14, 
  IDAC0_IRQn            = 15, 
  I2C0_IRQn             = 16, 
  GPIO_ODD_IRQn         = 17, 
  TIMER1_IRQn           = 18, 
  USART1_RX_IRQn        = 19, 
  USART1_TX_IRQn        = 20, 
  LEUART0_IRQn          = 21, 
  PCNT0_IRQn            = 22, 
  CMU_IRQn              = 23, 
  MSC_IRQn              = 24, 
  CRYPTO_IRQn           = 25, 
  LETIMER0_IRQn         = 26, 
  RTCC_IRQn             = 29, 
  CRYOTIMER_IRQn        = 31, 
} IRQn_Type;

/**************************************************************************/
#define __MPU_PRESENT             1 
#define __VTOR_PRESENT            1 
#define __NVIC_PRIO_BITS          3 
#define __Vendor_SysTickConfig    0 
/**************************************************************************/
#define _EFM32_JADE_FAMILY                      1  
#define _EFM_DEVICE                                
#define _SILICON_LABS_32B_SERIES_1                 
#define _SILICON_LABS_32B_SERIES                1  
#define _SILICON_LABS_32B_SERIES_1_CONFIG_1        
#define _SILICON_LABS_32B_SERIES_1_CONFIG       1  
#define _SILICON_LABS_GECKO_INTERNAL_SDID       80 
#define _SILICON_LABS_GECKO_INTERNAL_SDID_80       
#define _SILICON_LABS_32B_PLATFORM_2               
#define _SILICON_LABS_32B_PLATFORM              2  
#define _SILICON_LABS_32B_PLATFORM_2_GEN_1         
#define _SILICON_LABS_32B_PLATFORM_2_GEN        1  
/* If part number is not defined as compiler option, define it */
#if !defined(EFM32JG1B200F256GM48)
#define EFM32JG1B200F256GM48    1 
#endif

#define PART_NUMBER               "EFM32JG1B200F256GM48" 
#define FLASH_MEM_BASE            ((uint32_t) 0x00000000UL) 
#define FLASH_MEM_SIZE            ((uint32_t) 0x10000000UL) 
#define FLASH_MEM_END             ((uint32_t) 0x0FFFFFFFUL) 
#define FLASH_MEM_BITS            ((uint32_t) 0x0000001CUL) 
#define RAM_CODE_MEM_BASE         ((uint32_t) 0x10000000UL) 
#define RAM_CODE_MEM_SIZE         ((uint32_t) 0x7C00UL)     
#define RAM_CODE_MEM_END          ((uint32_t) 0x10007BFFUL) 
#define RAM_CODE_MEM_BITS         ((uint32_t) 0x0000000FUL) 
#define PER_BITCLR_MEM_BASE       ((uint32_t) 0x44000000UL) 
#define PER_BITCLR_MEM_SIZE       ((uint32_t) 0xE8000UL)    
#define PER_BITCLR_MEM_END        ((uint32_t) 0x440E7FFFUL) 
#define PER_BITCLR_MEM_BITS       ((uint32_t) 0x00000014UL) 
#define CRYPTO_BITSET_MEM_BASE    ((uint32_t) 0x460F0000UL) 
#define CRYPTO_BITSET_MEM_SIZE    ((uint32_t) 0x400UL)      
#define CRYPTO_BITSET_MEM_END     ((uint32_t) 0x460F03FFUL) 
#define CRYPTO_BITSET_MEM_BITS    ((uint32_t) 0x0000000AUL) 
#define CRYPTO_MEM_BASE           ((uint32_t) 0x400F0000UL) 
#define CRYPTO_MEM_SIZE           ((uint32_t) 0x400UL)      
#define CRYPTO_MEM_END            ((uint32_t) 0x400F03FFUL) 
#define CRYPTO_MEM_BITS           ((uint32_t) 0x0000000AUL) 
#define CRYPTO_BITCLR_MEM_BASE    ((uint32_t) 0x440F0000UL) 
#define CRYPTO_BITCLR_MEM_SIZE    ((uint32_t) 0x400UL)      
#define CRYPTO_BITCLR_MEM_END     ((uint32_t) 0x440F03FFUL) 
#define CRYPTO_BITCLR_MEM_BITS    ((uint32_t) 0x0000000AUL) 
#define PER_BITSET_MEM_BASE       ((uint32_t) 0x46000000UL) 
#define PER_BITSET_MEM_SIZE       ((uint32_t) 0xE8000UL)    
#define PER_BITSET_MEM_END        ((uint32_t) 0x460E7FFFUL) 
#define PER_BITSET_MEM_BITS       ((uint32_t) 0x00000014UL) 
#define PER_MEM_BASE              ((uint32_t) 0x40000000UL) 
#define PER_MEM_SIZE              ((uint32_t) 0xE8000UL)    
#define PER_MEM_END               ((uint32_t) 0x400E7FFFUL) 
#define PER_MEM_BITS              ((uint32_t) 0x00000014UL) 
#define RAM_MEM_BASE              ((uint32_t) 0x20000000UL) 
#define RAM_MEM_SIZE              ((uint32_t) 0x7C00UL)     
#define RAM_MEM_END               ((uint32_t) 0x20007BFFUL) 
#define RAM_MEM_BITS              ((uint32_t) 0x0000000FUL) 
#define BITBAND_PER_BASE          ((uint32_t) 0x42000000UL) 
#define BITBAND_RAM_BASE          ((uint32_t) 0x22000000UL) 
#define FLASH_BASE                (0x00000000UL) 
#define FLASH_SIZE                (0x00040000UL) 
#define FLASH_PAGE_SIZE           2048           
#define SRAM_BASE                 (0x20000000UL) 
#define SRAM_SIZE                 (0x00008000UL) 
#define __CM3_REV                 0x201          
#define PRS_CHAN_COUNT            12             
#define DMA_CHAN_COUNT            8              
#define EXT_IRQ_COUNT             34             
#define AFCHAN_MAX                72
#define AFCHANLOC_MAX             32

#define AFACHAN_MAX               61

/* Part number capabilities */

#define TIMER_PRESENT         
#define TIMER_COUNT         2 
#define USART_PRESENT         
#define USART_COUNT         2 
#define LEUART_PRESENT        
#define LEUART_COUNT        1 
#define LETIMER_PRESENT       
#define LETIMER_COUNT       1 
#define PCNT_PRESENT          
#define PCNT_COUNT          1 
#define I2C_PRESENT           
#define I2C_COUNT           1 
#define ADC_PRESENT           
#define ADC_COUNT           1 
#define ACMP_PRESENT          
#define ACMP_COUNT          2 
#define IDAC_PRESENT          
#define IDAC_COUNT          1 
#define WDOG_PRESENT          
#define WDOG_COUNT          1 
#define MSC_PRESENT
#define MSC_COUNT           1
#define EMU_PRESENT
#define EMU_COUNT           1
#define RMU_PRESENT
#define RMU_COUNT           1
#define CMU_PRESENT
#define CMU_COUNT           1
#define CRYPTO_PRESENT
#define CRYPTO_COUNT        1
#define GPIO_PRESENT
#define GPIO_COUNT          1
#define PRS_PRESENT
#define PRS_COUNT           1
#define LDMA_PRESENT
#define LDMA_COUNT          1
#define GPCRC_PRESENT
#define GPCRC_COUNT         1
#define CRYOTIMER_PRESENT
#define CRYOTIMER_COUNT     1
#define RTCC_PRESENT
#define RTCC_COUNT          1
#define BOOTLOADER_PRESENT
#define BOOTLOADER_COUNT    1

#include "core_cm3.h"         /* Cortex-M3 processor and core peripherals */
#include "system_efm32jg1b.h" /* System Header File */

/**************************************************************************/
#include "efm32jg1b_msc.h"
#include "efm32jg1b_emu.h"
#include "efm32jg1b_rmu.h"
#include "efm32jg1b_cmu.h"
#include "efm32jg1b_crypto.h"
#include "efm32jg1b_gpio_p.h"
#include "efm32jg1b_gpio.h"
#include "efm32jg1b_prs_ch.h"
#include "efm32jg1b_prs.h"
#include "efm32jg1b_ldma_ch.h"
#include "efm32jg1b_ldma.h"
#include "efm32jg1b_gpcrc.h"
#include "efm32jg1b_timer_cc.h"
#include "efm32jg1b_timer.h"
#include "efm32jg1b_usart.h"
#include "efm32jg1b_leuart.h"
#include "efm32jg1b_letimer.h"
#include "efm32jg1b_cryotimer.h"
#include "efm32jg1b_pcnt.h"
#include "efm32jg1b_i2c.h"
#include "efm32jg1b_adc.h"
#include "efm32jg1b_acmp.h"
#include "efm32jg1b_idac.h"
#include "efm32jg1b_rtcc_cc.h"
#include "efm32jg1b_rtcc_ret.h"
#include "efm32jg1b_rtcc.h"
#include "efm32jg1b_wdog_pch.h"
#include "efm32jg1b_wdog.h"
#include "efm32jg1b_dma_descriptor.h"
#include "efm32jg1b_devinfo.h"
#include "efm32jg1b_romtable.h"

/**************************************************************************/
#define MSC_BASE          (0x400E0000UL) 
#define EMU_BASE          (0x400E3000UL) 
#define RMU_BASE          (0x400E5000UL) 
#define CMU_BASE          (0x400E4000UL) 
#define CRYPTO_BASE       (0x400F0000UL) 
#define GPIO_BASE         (0x4000A000UL) 
#define PRS_BASE          (0x400E6000UL) 
#define LDMA_BASE         (0x400E2000UL) 
#define GPCRC_BASE        (0x4001C000UL) 
#define TIMER0_BASE       (0x40018000UL) 
#define TIMER1_BASE       (0x40018400UL) 
#define USART0_BASE       (0x40010000UL) 
#define USART1_BASE       (0x40010400UL) 
#define LEUART0_BASE      (0x4004A000UL) 
#define LETIMER0_BASE     (0x40046000UL) 
#define CRYOTIMER_BASE    (0x4001E000UL) 
#define PCNT0_BASE        (0x4004E000UL) 
#define I2C0_BASE         (0x4000C000UL) 
#define ADC0_BASE         (0x40002000UL) 
#define ACMP0_BASE        (0x40000000UL) 
#define ACMP1_BASE        (0x40000400UL) 
#define IDAC0_BASE        (0x40006000UL) 
#define RTCC_BASE         (0x40042000UL) 
#define WDOG0_BASE        (0x40052000UL) 
#define DEVINFO_BASE      (0x0FE081B0UL) 
#define ROMTABLE_BASE     (0xE00FFFD0UL) 
#define LOCKBITS_BASE     (0x0FE04000UL) 
#define USERDATA_BASE     (0x0FE00000UL) 
/**************************************************************************/
#define MSC          ((MSC_TypeDef *) MSC_BASE)             
#define EMU          ((EMU_TypeDef *) EMU_BASE)             
#define RMU          ((RMU_TypeDef *) RMU_BASE)             
#define CMU          ((CMU_TypeDef *) CMU_BASE)             
#define CRYPTO       ((CRYPTO_TypeDef *) CRYPTO_BASE)       
#define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
#define PRS          ((PRS_TypeDef *) PRS_BASE)             
#define LDMA         ((LDMA_TypeDef *) LDMA_BASE)           
#define GPCRC        ((GPCRC_TypeDef *) GPCRC_BASE)         
#define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
#define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
#define USART0       ((USART_TypeDef *) USART0_BASE)        
#define USART1       ((USART_TypeDef *) USART1_BASE)        
#define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
#define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    
#define CRYOTIMER    ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE) 
#define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
#define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
#define ADC0         ((ADC_TypeDef *) ADC0_BASE)            
#define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
#define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          
#define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          
#define RTCC         ((RTCC_TypeDef *) RTCC_BASE)           
#define WDOG0        ((WDOG_TypeDef *) WDOG0_BASE)          
#define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
#define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
/**************************************************************************/
#define TIMER_OFFSET      0x400 
#define USART_OFFSET      0x400 
#define LEUART_OFFSET     0x400 
#define LETIMER_OFFSET    0x400 
#define PCNT_OFFSET       0x400 
#define I2C_OFFSET        0x400 
#define ADC_OFFSET        0x400 
#define ACMP_OFFSET       0x400 
#define IDAC_OFFSET       0x400 
#define WDOG_OFFSET       0x400 
/**************************************************************************/
#include "efm32jg1b_prs_signals.h"
#include "efm32jg1b_dmareq.h"

/**************************************************************************/
#define MSC_UNLOCK_CODE      0x1B71 
#define EMU_UNLOCK_CODE      0xADE8 
#define RMU_UNLOCK_CODE      0xE084 
#define CMU_UNLOCK_CODE      0x580E 
#define GPIO_UNLOCK_CODE     0xA534 
#define TIMER_UNLOCK_CODE    0xCE80 
#define RTCC_UNLOCK_CODE     0xAEE8 
/**************************************************************************/
#include "efm32jg1b_af_ports.h"
#include "efm32jg1b_af_pins.h"

/**************************************************************************/
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

#ifdef __cplusplus
}
#endif
#endif /* EFM32JG1B200F256GM48_H */