EFM32 Happy Gecko Software Documentation  efm32hg-doc-5.1.2
em_rtcc.h
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1 /***************************************************************************/
33 #ifndef EM_RTCC_H
34 #define EM_RTCC_H
35 
36 #include "em_device.h"
37 #if defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 )
38 
39 #include <stdbool.h>
40 #include "em_assert.h"
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 /***************************************************************************/
51 /***************************************************************************/
57 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \
58  || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
59 /* Enable fix for errata "RTCC_E203 - Potential Stability Issue with RTCC
60  * Registers". */
61 #define ERRATA_FIX_RTCC_E203
62 #endif
63 
64 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
65 /* Enable fix for errata "RTCC_E204 - Disabling the RTCC Backup RAM may consume extra
66  * current". */
67 #define ERRATA_FIX_RTCC_E204
68 #endif
69 
71 /*******************************************************************************
72  ********************************* ENUM ************************************
73  ******************************************************************************/
74 
76 typedef enum
77 {
79  rtccCntModeNormal = _RTCC_CTRL_CNTTICK_PRESC,
80 
83  rtccCntModeCalendar = _RTCC_CTRL_CNTTICK_CCV0MATCH
84 } RTCC_CntMode_TypeDef;
85 
87 typedef enum
88 {
89  rtccCntPresc_1 = _RTCC_CTRL_CNTPRESC_DIV1,
90  rtccCntPresc_2 = _RTCC_CTRL_CNTPRESC_DIV2,
91  rtccCntPresc_4 = _RTCC_CTRL_CNTPRESC_DIV4,
92  rtccCntPresc_8 = _RTCC_CTRL_CNTPRESC_DIV8,
93  rtccCntPresc_16 = _RTCC_CTRL_CNTPRESC_DIV16,
94  rtccCntPresc_32 = _RTCC_CTRL_CNTPRESC_DIV32,
95  rtccCntPresc_64 = _RTCC_CTRL_CNTPRESC_DIV64,
96  rtccCntPresc_128 = _RTCC_CTRL_CNTPRESC_DIV128,
97  rtccCntPresc_256 = _RTCC_CTRL_CNTPRESC_DIV256,
98  rtccCntPresc_512 = _RTCC_CTRL_CNTPRESC_DIV512,
99  rtccCntPresc_1024 = _RTCC_CTRL_CNTPRESC_DIV1024,
100  rtccCntPresc_2048 = _RTCC_CTRL_CNTPRESC_DIV2048,
101  rtccCntPresc_4096 = _RTCC_CTRL_CNTPRESC_DIV4096,
102  rtccCntPresc_8192 = _RTCC_CTRL_CNTPRESC_DIV8192,
103  rtccCntPresc_16384 = _RTCC_CTRL_CNTPRESC_DIV16384,
104  rtccCntPresc_32768 = _RTCC_CTRL_CNTPRESC_DIV32768
105 } RTCC_CntPresc_TypeDef;
106 
107 
109 typedef enum
110 {
112  rtccCntTickPresc = _RTCC_CTRL_CNTTICK_PRESC,
113 
116  rtccCntTickCCV0Match = _RTCC_CTRL_CNTTICK_CCV0MATCH
117 } RTCC_PrescMode_TypeDef;
118 
119 
121 typedef enum
122 {
123  rtccCapComChModeOff = _RTCC_CC_CTRL_MODE_OFF,
124  rtccCapComChModeCapture = _RTCC_CC_CTRL_MODE_INPUTCAPTURE,
125  rtccCapComChModeCompare = _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE,
126 } RTCC_CapComChMode_TypeDef;
127 
129 typedef enum
130 {
131  rtccCompMatchOutActionPulse = _RTCC_CC_CTRL_CMOA_PULSE,
132  rtccCompMatchOutActionToggle = _RTCC_CC_CTRL_CMOA_TOGGLE,
133  rtccCompMatchOutActionClear = _RTCC_CC_CTRL_CMOA_CLEAR,
134  rtccCompMatchOutActionSet = _RTCC_CC_CTRL_CMOA_SET
135 } RTCC_CompMatchOutAction_TypeDef;
136 
137 
139 typedef enum
140 {
141  rtccPRSCh0 = _RTCC_CC_CTRL_PRSSEL_PRSCH0,
142  rtccPRSCh1 = _RTCC_CC_CTRL_PRSSEL_PRSCH1,
143  rtccPRSCh2 = _RTCC_CC_CTRL_PRSSEL_PRSCH2,
144  rtccPRSCh3 = _RTCC_CC_CTRL_PRSSEL_PRSCH3,
145  rtccPRSCh4 = _RTCC_CC_CTRL_PRSSEL_PRSCH4,
146  rtccPRSCh5 = _RTCC_CC_CTRL_PRSSEL_PRSCH5,
147  rtccPRSCh6 = _RTCC_CC_CTRL_PRSSEL_PRSCH6,
148  rtccPRSCh7 = _RTCC_CC_CTRL_PRSSEL_PRSCH7,
149  rtccPRSCh8 = _RTCC_CC_CTRL_PRSSEL_PRSCH8,
150  rtccPRSCh9 = _RTCC_CC_CTRL_PRSSEL_PRSCH9,
151  rtccPRSCh10 = _RTCC_CC_CTRL_PRSSEL_PRSCH10,
152  rtccPRSCh11 = _RTCC_CC_CTRL_PRSSEL_PRSCH11
153 } RTCC_PRSSel_TypeDef;
154 
155 
157 typedef enum
158 {
159  rtccInEdgeRising = _RTCC_CC_CTRL_ICEDGE_RISING,
160  rtccInEdgeFalling = _RTCC_CC_CTRL_ICEDGE_FALLING,
161  rtccInEdgeBoth = _RTCC_CC_CTRL_ICEDGE_BOTH,
162  rtccInEdgeNone = _RTCC_CC_CTRL_ICEDGE_NONE
163 } RTCC_InEdgeSel_TypeDef;
164 
165 
167 typedef enum
168 {
170  rtccCompBaseCnt = _RTCC_CC_CTRL_COMPBASE_CNT,
171 
173  rtccCompBasePreCnt = _RTCC_CC_CTRL_COMPBASE_PRECNT
174 } RTCC_CompBase_TypeDef;
175 
177 typedef enum
178 {
179  rtccDayCompareModeMonth = _RTCC_CC_CTRL_DAYCC_MONTH,
180  rtccDayCompareModeWeek = _RTCC_CC_CTRL_DAYCC_WEEK
181 } RTCC_DayCompareMode_TypeDef;
182 
183 /*******************************************************************************
184  ******************************* STRUCTS ***********************************
185  ******************************************************************************/
186 
188 typedef struct
189 {
191  bool enable;
192 
194  bool debugRun;
195 
197  bool precntWrapOnCCV0;
198 
200  bool cntWrapOnCCV1;
201 
203  RTCC_CntPresc_TypeDef presc;
204 
206  RTCC_PrescMode_TypeDef prescMode;
207 
208 #if defined(_RTCC_CTRL_BUMODETSEN_MASK)
209 
211  bool enaBackupModeSet;
212 #endif
213 
216  bool enaOSCFailDetect;
217 
219  RTCC_CntMode_TypeDef cntMode;
220 
224  bool disLeapYearCorr;
225 } RTCC_Init_TypeDef;
226 
227 
229 typedef struct
230 {
232  RTCC_CapComChMode_TypeDef chMode;
233 
235  RTCC_CompMatchOutAction_TypeDef compMatchOutAction;
236 
238  RTCC_PRSSel_TypeDef prsSel;
239 
241  RTCC_InEdgeSel_TypeDef inputEdgeSel;
242 
244  RTCC_CompBase_TypeDef compBase;
245 
248  uint8_t compMask;
249 
251  RTCC_DayCompareMode_TypeDef dayCompMode;
252 } RTCC_CCChConf_TypeDef;
253 
254 
255 /*******************************************************************************
256  ******************************* DEFINES ***********************************
257  ******************************************************************************/
258 
260 #if defined(_RTCC_CTRL_BUMODETSEN_MASK)
261 #define RTCC_INIT_DEFAULT \
262 { \
263  true, /* Start counting when init done. */ \
264  false, /* Disable RTCC during debug halt. */ \
265  false, /* Disable precounter wrap on ch. 0 CCV value. */ \
266  false, /* Disable counter wrap on ch. 1 CCV value. */ \
267  rtccCntPresc_32, /* 977 us per tick. */ \
268  rtccCntTickPresc, /* Counter increments according to prescaler value. */ \
269  false, /* No RTCC storage on backup mode entry. */ \
270  false, /* No RTCC oscillator failure detection. */ \
271  rtccCntModeNormal, /* Normal RTCC mode. */ \
272  false, /* No leap year correction. */ \
273 }
274 #else
275 #define RTCC_INIT_DEFAULT \
276 { \
277  true, /* Start counting when init done. */ \
278  false, /* Disable RTCC during debug halt. */ \
279  false, /* Disable precounter wrap on ch. 0 CCV value. */ \
280  false, /* Disable counter wrap on ch. 1 CCV value. */ \
281  rtccCntPresc_32, /* 977 us per tick. */ \
282  rtccCntTickPresc, /* Counter increments according to prescaler value. */ \
283  false, /* No RTCC oscillator failure detection. */ \
284  rtccCntModeNormal, /* Normal RTCC mode. */ \
285  false, /* No leap year correction. */ \
286 }
287 #endif
288 
290 #define RTCC_CH_INIT_COMPARE_DEFAULT \
291 { \
292  rtccCapComChModeCompare, /* Select output compare mode. */ \
293  rtccCompMatchOutActionPulse, /* Create pulse on compare match. */ \
294  rtccPRSCh0, /* PRS channel 0 (not used). */ \
295  rtccInEdgeNone, /* No edge detection. */ \
296  rtccCompBaseCnt, /* Counter comparison base. */ \
297  0, /* No compare mask bits set. */ \
298  rtccDayCompareModeMonth /* Don't care */ \
299 }
300 
302 #define RTCC_CH_INIT_CAPTURE_DEFAULT \
303 { \
304  rtccCapComChModeCapture, /* Select input capture mode. */ \
305  rtccCompMatchOutActionPulse, /* Create pulse on capture. */ \
306  rtccPRSCh0, /* PRS channel 0. */ \
307  rtccInEdgeRising, /* Rising edge detection. */ \
308  rtccCompBaseCnt, /* Don't care. */ \
309  0, /* Don't care. */ \
310  rtccDayCompareModeMonth /* Don't care */ \
311 }
312 
314 #define RTCC_CH_VALID( ch ) ( ( ch ) < 3 )
315 
316 /*******************************************************************************
317  ***************************** PROTOTYPES **********************************
318  ******************************************************************************/
319 
320 /***************************************************************************/
330 __STATIC_INLINE uint32_t RTCC_ChannelCCVGet( int ch )
331 {
332  EFM_ASSERT( RTCC_CH_VALID( ch ) );
333  return RTCC->CC[ ch ].CCV;
334 }
335 
336 /***************************************************************************/
346 __STATIC_INLINE void RTCC_ChannelCCVSet( int ch, uint32_t value )
347 {
348  EFM_ASSERT( RTCC_CH_VALID( ch ) );
349  RTCC->CC[ ch ].CCV = value;
350 }
351 
352 /***************************************************************************/
362 __STATIC_INLINE uint32_t RTCC_ChannelDateGet( int ch )
363 {
364  EFM_ASSERT( RTCC_CH_VALID( ch ) );
365  return RTCC->CC[ ch ].DATE;
366 }
367 
368 /***************************************************************************/
378 __STATIC_INLINE void RTCC_ChannelDateSet( int ch, uint32_t date )
379 {
380  EFM_ASSERT( RTCC_CH_VALID( ch ) );
381  RTCC->CC[ ch ].DATE = date;
382 }
383 
384 void RTCC_ChannelInit( int ch, RTCC_CCChConf_TypeDef const *confPtr );
385 
386 /***************************************************************************/
396 __STATIC_INLINE uint32_t RTCC_ChannelTimeGet( int ch )
397 {
398  EFM_ASSERT( RTCC_CH_VALID( ch ) );
399  return RTCC->CC[ ch ].TIME;
400 }
401 
402 /***************************************************************************/
412 __STATIC_INLINE void RTCC_ChannelTimeSet( int ch, uint32_t time )
413 {
414  EFM_ASSERT( RTCC_CH_VALID( ch ) );
415  RTCC->CC[ ch ].TIME = time;
416 }
417 
418 /***************************************************************************/
425 __STATIC_INLINE uint32_t RTCC_CombinedCounterGet( void )
426 {
427  return RTCC->COMBCNT;
428 }
429 
430 /***************************************************************************/
437 __STATIC_INLINE uint32_t RTCC_CounterGet( void )
438 {
439  return RTCC->CNT;
440 }
441 
442 /***************************************************************************/
449 __STATIC_INLINE void RTCC_CounterSet( uint32_t value )
450 {
451  RTCC->CNT = value;
452 }
453 
454 /***************************************************************************/
461 __STATIC_INLINE uint32_t RTCC_DateGet( void )
462 {
463  return RTCC->DATE;
464 }
465 
466 /***************************************************************************/
473 __STATIC_INLINE void RTCC_DateSet( uint32_t date )
474 {
475  RTCC->DATE = date;
476 }
477 
478 /***************************************************************************/
485 __STATIC_INLINE void RTCC_EM4WakeupEnable( bool enable )
486 {
487  if ( enable )
488  {
489  RTCC->EM4WUEN = RTCC_EM4WUEN_EM4WU;
490  }
491  else
492  {
493  RTCC->EM4WUEN = 0;
494  }
495 }
496 
497 void RTCC_Enable( bool enable );
498 
499 void RTCC_Init( const RTCC_Init_TypeDef *init );
500 
501 /***************************************************************************/
509 __STATIC_INLINE void RTCC_IntClear( uint32_t flags )
510 {
511  RTCC->IFC = flags;
512 }
513 
514 /***************************************************************************/
522 __STATIC_INLINE void RTCC_IntDisable( uint32_t flags )
523 {
524  RTCC->IEN &= ~flags;
525 }
526 
527 /***************************************************************************/
540 __STATIC_INLINE void RTCC_IntEnable( uint32_t flags )
541 {
542  RTCC->IEN |= flags;
543 }
544 
545 /***************************************************************************/
556 __STATIC_INLINE uint32_t RTCC_IntGet( void )
557 {
558  return RTCC->IF;
559 }
560 
561 /***************************************************************************/
572 __STATIC_INLINE uint32_t RTCC_IntGetEnabled( void )
573 {
574  uint32_t tmp;
575 
576  tmp = RTCC->IEN;
577 
578  /* Bitwise AND of pending and enabled interrupt flags. */
579  return RTCC->IF & tmp;
580 }
581 
582 /***************************************************************************/
590 __STATIC_INLINE void RTCC_IntSet( uint32_t flags )
591 {
592  RTCC->IFS = flags;
593 }
594 
595 /***************************************************************************/
604 __STATIC_INLINE void RTCC_Lock( void )
605 {
606 #if defined(ERRATA_FIX_RTCC_E203)
607  /* RTCC_E203 - Potential Stability Issue with RTCC Registers
608  * RTCC_LOCK register must be modified while RTCC clock is disabled. */
609  uint32_t lfeReg = CMU->LFECLKEN0;
610  bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED);
611  if (cmuLocked)
612  {
614  }
615  CMU->LFECLKEN0 = 0x0;
616 #endif
617  RTCC->LOCK = RTCC_LOCK_LOCKKEY_LOCK;
618 #if defined(ERRATA_FIX_RTCC_E203)
619  /* Restore clock state after RTCC_E203 fix. */
620  CMU->LFECLKEN0 = lfeReg;
621  if (cmuLocked)
622  {
623  CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
624  }
625 #endif
626 }
627 
628 /***************************************************************************/
635 __STATIC_INLINE uint32_t RTCC_PreCounterGet( void )
636 {
637  return RTCC->PRECNT;
638 }
639 
640 /***************************************************************************/
647 __STATIC_INLINE void RTCC_PreCounterSet( uint32_t preCntVal )
648 {
649  RTCC->PRECNT = preCntVal;
650 }
651 
652 void RTCC_Reset( void );
653 
654 /***************************************************************************/
661 __STATIC_INLINE void RTCC_RetentionRamPowerDown( void )
662 {
663 #if !defined(ERRATA_FIX_RTCC_E204)
664  /* Devices that are affected by RTCC_E204 should always keep the RTCC
665  * backup RAM retained. */
666  RTCC->POWERDOWN = RTCC_POWERDOWN_RAM;
667 #endif
668 }
669 
670 void RTCC_StatusClear( void );
671 
672 /***************************************************************************/
679 __STATIC_INLINE uint32_t RTCC_StatusGet( void )
680 {
681  while ( RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD )
682  {
683  // Wait for syncronization.
684  }
685  return RTCC->STATUS;
686 }
687 
688 /***************************************************************************/
695 __STATIC_INLINE uint32_t RTCC_TimeGet( void )
696 {
697  return RTCC->TIME;
698 }
699 
700 /***************************************************************************/
707 __STATIC_INLINE void RTCC_TimeSet( uint32_t time )
708 {
709  RTCC->TIME = time;
710 }
711 
712 /***************************************************************************/
721 __STATIC_INLINE void RTCC_Unlock( void )
722 {
723 #if defined(ERRATA_FIX_RTCC_E203)
724  /* RTCC_E203 - Potential Stability Issue with RTCC Registers
725  * RTCC_LOCK register must be modified while RTCC clock is disabled. */
726  uint32_t lfeReg = CMU->LFECLKEN0;
727  bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED);
728  if (cmuLocked)
729  {
731  }
732  CMU->LFECLKEN0 = 0x0;
733 #endif
734  RTCC->LOCK = RTCC_LOCK_LOCKKEY_UNLOCK;
735 #if defined(ERRATA_FIX_RTCC_E203)
736  /* Restore clock state after RTCC_E203 fix. */
737  CMU->LFECLKEN0 = lfeReg;
738  if (cmuLocked)
739  {
740  CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
741  }
742 #endif
743 }
744 
748 #ifdef __cplusplus
749 }
750 #endif
751 
752 #endif /* defined( RTCC_COUNT ) && ( RTC_COUNT == 1 ) */
753 #endif /* EM_RTCC_H */
Emlib peripheral API "assert" implementation.
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
#define CMU_LOCK_LOCKKEY_LOCK
Definition: efm32hg_cmu.h:1138
#define CMU_LOCK_LOCKKEY_LOCKED
Definition: efm32hg_cmu.h:1140
#define CMU
#define CMU_LOCK_LOCKKEY_UNLOCK
Definition: efm32hg_cmu.h:1141