EFM32 Giant Gecko Software Documentation  efm32gg-doc-5.1.2
efm32gg_msc.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IOM uint32_t CTRL;
44  __IOM uint32_t READCTRL;
45  __IOM uint32_t WRITECTRL;
46  __IOM uint32_t WRITECMD;
47  __IOM uint32_t ADDRB;
49  uint32_t RESERVED0[1];
50  __IOM uint32_t WDATA;
51  __IM uint32_t STATUS;
53  uint32_t RESERVED1[3];
54  __IM uint32_t IF;
55  __IOM uint32_t IFS;
56  __IOM uint32_t IFC;
57  __IOM uint32_t IEN;
58  __IOM uint32_t LOCK;
59  __IOM uint32_t CMD;
60  __IM uint32_t CACHEHITS;
61  __IM uint32_t CACHEMISSES;
62  uint32_t RESERVED2[1];
63  __IOM uint32_t TIMEBASE;
64  __IOM uint32_t MASSLOCK;
65 } MSC_TypeDef;
67 /**************************************************************************/
72 /* Bit fields for MSC CTRL */
73 #define _MSC_CTRL_RESETVALUE 0x00000001UL
74 #define _MSC_CTRL_MASK 0x00000001UL
75 #define MSC_CTRL_BUSFAULT (0x1UL << 0)
76 #define _MSC_CTRL_BUSFAULT_SHIFT 0
77 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL
78 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL
79 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL
80 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL
81 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0)
82 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0)
83 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0)
85 /* Bit fields for MSC READCTRL */
86 #define _MSC_READCTRL_RESETVALUE 0x00000001UL
87 #define _MSC_READCTRL_MASK 0x000301FFUL
88 #define _MSC_READCTRL_MODE_SHIFT 0
89 #define _MSC_READCTRL_MODE_MASK 0x7UL
90 #define _MSC_READCTRL_MODE_WS0 0x00000000UL
91 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL
92 #define _MSC_READCTRL_MODE_WS1 0x00000001UL
93 #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL
94 #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL
95 #define _MSC_READCTRL_MODE_WS2 0x00000004UL
96 #define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL
97 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0)
98 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0)
99 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0)
100 #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0)
101 #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0)
102 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0)
103 #define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0)
104 #define MSC_READCTRL_IFCDIS (0x1UL << 3)
105 #define _MSC_READCTRL_IFCDIS_SHIFT 3
106 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL
107 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL
108 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3)
109 #define MSC_READCTRL_AIDIS (0x1UL << 4)
110 #define _MSC_READCTRL_AIDIS_SHIFT 4
111 #define _MSC_READCTRL_AIDIS_MASK 0x10UL
112 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL
113 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4)
114 #define MSC_READCTRL_ICCDIS (0x1UL << 5)
115 #define _MSC_READCTRL_ICCDIS_SHIFT 5
116 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL
117 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL
118 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5)
119 #define MSC_READCTRL_EBICDIS (0x1UL << 6)
120 #define _MSC_READCTRL_EBICDIS_SHIFT 6
121 #define _MSC_READCTRL_EBICDIS_MASK 0x40UL
122 #define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL
123 #define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6)
124 #define MSC_READCTRL_RAMCEN (0x1UL << 7)
125 #define _MSC_READCTRL_RAMCEN_SHIFT 7
126 #define _MSC_READCTRL_RAMCEN_MASK 0x80UL
127 #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL
128 #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7)
129 #define MSC_READCTRL_PREFETCH (0x1UL << 8)
130 #define _MSC_READCTRL_PREFETCH_SHIFT 8
131 #define _MSC_READCTRL_PREFETCH_MASK 0x100UL
132 #define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000000UL
133 #define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8)
134 #define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16
135 #define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL
136 #define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL
137 #define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL
138 #define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL
139 #define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL
140 #define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL
141 #define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16)
142 #define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16)
143 #define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16)
144 #define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16)
145 #define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16)
147 /* Bit fields for MSC WRITECTRL */
148 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL
149 #define _MSC_WRITECTRL_MASK 0x0000003FUL
150 #define MSC_WRITECTRL_WREN (0x1UL << 0)
151 #define _MSC_WRITECTRL_WREN_SHIFT 0
152 #define _MSC_WRITECTRL_WREN_MASK 0x1UL
153 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL
154 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0)
155 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1)
156 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1
157 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL
158 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL
159 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1)
160 #define MSC_WRITECTRL_WDOUBLE (0x1UL << 2)
161 #define _MSC_WRITECTRL_WDOUBLE_SHIFT 2
162 #define _MSC_WRITECTRL_WDOUBLE_MASK 0x4UL
163 #define _MSC_WRITECTRL_WDOUBLE_DEFAULT 0x00000000UL
164 #define MSC_WRITECTRL_WDOUBLE_DEFAULT (_MSC_WRITECTRL_WDOUBLE_DEFAULT << 2)
165 #define MSC_WRITECTRL_LPWRITE (0x1UL << 3)
166 #define _MSC_WRITECTRL_LPWRITE_SHIFT 3
167 #define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL
168 #define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL
169 #define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3)
170 #define MSC_WRITECTRL_LPERASE (0x1UL << 4)
171 #define _MSC_WRITECTRL_LPERASE_SHIFT 4
172 #define _MSC_WRITECTRL_LPERASE_MASK 0x10UL
173 #define _MSC_WRITECTRL_LPERASE_DEFAULT 0x00000000UL
174 #define MSC_WRITECTRL_LPERASE_DEFAULT (_MSC_WRITECTRL_LPERASE_DEFAULT << 4)
175 #define MSC_WRITECTRL_RWWEN (0x1UL << 5)
176 #define _MSC_WRITECTRL_RWWEN_SHIFT 5
177 #define _MSC_WRITECTRL_RWWEN_MASK 0x20UL
178 #define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL
179 #define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5)
181 /* Bit fields for MSC WRITECMD */
182 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL
183 #define _MSC_WRITECMD_MASK 0x0000133FUL
184 #define MSC_WRITECMD_LADDRIM (0x1UL << 0)
185 #define _MSC_WRITECMD_LADDRIM_SHIFT 0
186 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL
187 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL
188 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0)
189 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1)
190 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1
191 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL
192 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL
193 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1)
194 #define MSC_WRITECMD_WRITEEND (0x1UL << 2)
195 #define _MSC_WRITECMD_WRITEEND_SHIFT 2
196 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL
197 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL
198 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2)
199 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3)
200 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3
201 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL
202 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL
203 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3)
204 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4)
205 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4
206 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL
207 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL
208 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4)
209 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5)
210 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5
211 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL
212 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL
213 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5)
214 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8)
215 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8
216 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL
217 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL
218 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8)
219 #define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9)
220 #define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9
221 #define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL
222 #define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL
223 #define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9)
224 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12)
225 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12
226 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL
227 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL
228 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12)
230 /* Bit fields for MSC ADDRB */
231 #define _MSC_ADDRB_RESETVALUE 0x00000000UL
232 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL
233 #define _MSC_ADDRB_ADDRB_SHIFT 0
234 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL
235 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL
236 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0)
238 /* Bit fields for MSC WDATA */
239 #define _MSC_WDATA_RESETVALUE 0x00000000UL
240 #define _MSC_WDATA_MASK 0xFFFFFFFFUL
241 #define _MSC_WDATA_WDATA_SHIFT 0
242 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL
243 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL
244 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0)
246 /* Bit fields for MSC STATUS */
247 #define _MSC_STATUS_RESETVALUE 0x00000008UL
248 #define _MSC_STATUS_MASK 0x0000007FUL
249 #define MSC_STATUS_BUSY (0x1UL << 0)
250 #define _MSC_STATUS_BUSY_SHIFT 0
251 #define _MSC_STATUS_BUSY_MASK 0x1UL
252 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL
253 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0)
254 #define MSC_STATUS_LOCKED (0x1UL << 1)
255 #define _MSC_STATUS_LOCKED_SHIFT 1
256 #define _MSC_STATUS_LOCKED_MASK 0x2UL
257 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL
258 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1)
259 #define MSC_STATUS_INVADDR (0x1UL << 2)
260 #define _MSC_STATUS_INVADDR_SHIFT 2
261 #define _MSC_STATUS_INVADDR_MASK 0x4UL
262 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL
263 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2)
264 #define MSC_STATUS_WDATAREADY (0x1UL << 3)
265 #define _MSC_STATUS_WDATAREADY_SHIFT 3
266 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL
267 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL
268 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3)
269 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4)
270 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4
271 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL
272 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL
273 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4)
274 #define MSC_STATUS_ERASEABORTED (0x1UL << 5)
275 #define _MSC_STATUS_ERASEABORTED_SHIFT 5
276 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL
277 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL
278 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5)
279 #define MSC_STATUS_PCRUNNING (0x1UL << 6)
280 #define _MSC_STATUS_PCRUNNING_SHIFT 6
281 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL
282 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL
283 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6)
285 /* Bit fields for MSC IF */
286 #define _MSC_IF_RESETVALUE 0x00000000UL
287 #define _MSC_IF_MASK 0x0000000FUL
288 #define MSC_IF_ERASE (0x1UL << 0)
289 #define _MSC_IF_ERASE_SHIFT 0
290 #define _MSC_IF_ERASE_MASK 0x1UL
291 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL
292 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0)
293 #define MSC_IF_WRITE (0x1UL << 1)
294 #define _MSC_IF_WRITE_SHIFT 1
295 #define _MSC_IF_WRITE_MASK 0x2UL
296 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL
297 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1)
298 #define MSC_IF_CHOF (0x1UL << 2)
299 #define _MSC_IF_CHOF_SHIFT 2
300 #define _MSC_IF_CHOF_MASK 0x4UL
301 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL
302 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2)
303 #define MSC_IF_CMOF (0x1UL << 3)
304 #define _MSC_IF_CMOF_SHIFT 3
305 #define _MSC_IF_CMOF_MASK 0x8UL
306 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL
307 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3)
309 /* Bit fields for MSC IFS */
310 #define _MSC_IFS_RESETVALUE 0x00000000UL
311 #define _MSC_IFS_MASK 0x0000000FUL
312 #define MSC_IFS_ERASE (0x1UL << 0)
313 #define _MSC_IFS_ERASE_SHIFT 0
314 #define _MSC_IFS_ERASE_MASK 0x1UL
315 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL
316 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0)
317 #define MSC_IFS_WRITE (0x1UL << 1)
318 #define _MSC_IFS_WRITE_SHIFT 1
319 #define _MSC_IFS_WRITE_MASK 0x2UL
320 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL
321 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1)
322 #define MSC_IFS_CHOF (0x1UL << 2)
323 #define _MSC_IFS_CHOF_SHIFT 2
324 #define _MSC_IFS_CHOF_MASK 0x4UL
325 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL
326 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2)
327 #define MSC_IFS_CMOF (0x1UL << 3)
328 #define _MSC_IFS_CMOF_SHIFT 3
329 #define _MSC_IFS_CMOF_MASK 0x8UL
330 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL
331 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3)
333 /* Bit fields for MSC IFC */
334 #define _MSC_IFC_RESETVALUE 0x00000000UL
335 #define _MSC_IFC_MASK 0x0000000FUL
336 #define MSC_IFC_ERASE (0x1UL << 0)
337 #define _MSC_IFC_ERASE_SHIFT 0
338 #define _MSC_IFC_ERASE_MASK 0x1UL
339 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL
340 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0)
341 #define MSC_IFC_WRITE (0x1UL << 1)
342 #define _MSC_IFC_WRITE_SHIFT 1
343 #define _MSC_IFC_WRITE_MASK 0x2UL
344 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL
345 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1)
346 #define MSC_IFC_CHOF (0x1UL << 2)
347 #define _MSC_IFC_CHOF_SHIFT 2
348 #define _MSC_IFC_CHOF_MASK 0x4UL
349 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL
350 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2)
351 #define MSC_IFC_CMOF (0x1UL << 3)
352 #define _MSC_IFC_CMOF_SHIFT 3
353 #define _MSC_IFC_CMOF_MASK 0x8UL
354 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL
355 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3)
357 /* Bit fields for MSC IEN */
358 #define _MSC_IEN_RESETVALUE 0x00000000UL
359 #define _MSC_IEN_MASK 0x0000000FUL
360 #define MSC_IEN_ERASE (0x1UL << 0)
361 #define _MSC_IEN_ERASE_SHIFT 0
362 #define _MSC_IEN_ERASE_MASK 0x1UL
363 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL
364 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0)
365 #define MSC_IEN_WRITE (0x1UL << 1)
366 #define _MSC_IEN_WRITE_SHIFT 1
367 #define _MSC_IEN_WRITE_MASK 0x2UL
368 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL
369 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1)
370 #define MSC_IEN_CHOF (0x1UL << 2)
371 #define _MSC_IEN_CHOF_SHIFT 2
372 #define _MSC_IEN_CHOF_MASK 0x4UL
373 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL
374 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2)
375 #define MSC_IEN_CMOF (0x1UL << 3)
376 #define _MSC_IEN_CMOF_SHIFT 3
377 #define _MSC_IEN_CMOF_MASK 0x8UL
378 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL
379 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3)
381 /* Bit fields for MSC LOCK */
382 #define _MSC_LOCK_RESETVALUE 0x00000000UL
383 #define _MSC_LOCK_MASK 0x0000FFFFUL
384 #define _MSC_LOCK_LOCKKEY_SHIFT 0
385 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL
386 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL
387 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL
388 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
389 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL
390 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL
391 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0)
392 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0)
393 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0)
394 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0)
395 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0)
397 /* Bit fields for MSC CMD */
398 #define _MSC_CMD_RESETVALUE 0x00000000UL
399 #define _MSC_CMD_MASK 0x00000007UL
400 #define MSC_CMD_INVCACHE (0x1UL << 0)
401 #define _MSC_CMD_INVCACHE_SHIFT 0
402 #define _MSC_CMD_INVCACHE_MASK 0x1UL
403 #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL
404 #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0)
405 #define MSC_CMD_STARTPC (0x1UL << 1)
406 #define _MSC_CMD_STARTPC_SHIFT 1
407 #define _MSC_CMD_STARTPC_MASK 0x2UL
408 #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL
409 #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1)
410 #define MSC_CMD_STOPPC (0x1UL << 2)
411 #define _MSC_CMD_STOPPC_SHIFT 2
412 #define _MSC_CMD_STOPPC_MASK 0x4UL
413 #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL
414 #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2)
416 /* Bit fields for MSC CACHEHITS */
417 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL
418 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL
419 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0
420 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL
421 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL
422 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0)
424 /* Bit fields for MSC CACHEMISSES */
425 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL
426 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL
427 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0
428 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL
429 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL
430 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0)
432 /* Bit fields for MSC TIMEBASE */
433 #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL
434 #define _MSC_TIMEBASE_MASK 0x0001003FUL
435 #define _MSC_TIMEBASE_BASE_SHIFT 0
436 #define _MSC_TIMEBASE_BASE_MASK 0x3FUL
437 #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL
438 #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0)
439 #define MSC_TIMEBASE_PERIOD (0x1UL << 16)
440 #define _MSC_TIMEBASE_PERIOD_SHIFT 16
441 #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL
442 #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL
443 #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL
444 #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL
445 #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16)
446 #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16)
447 #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16)
449 /* Bit fields for MSC MASSLOCK */
450 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL
451 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL
452 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0
453 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL
454 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL
455 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL
456 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL
457 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL
458 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL
459 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0)
460 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0)
461 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0)
462 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0)
463 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0)
__IOM uint32_t MASSLOCK
Definition: efm32gg_msc.h:64
__IM uint32_t CACHEHITS
Definition: efm32gg_msc.h:60
__IOM uint32_t LOCK
Definition: efm32gg_msc.h:58
__IOM uint32_t IEN
Definition: efm32gg_msc.h:57
__IM uint32_t STATUS
Definition: efm32gg_msc.h:51
__IOM uint32_t WDATA
Definition: efm32gg_msc.h:50
__IOM uint32_t TIMEBASE
Definition: efm32gg_msc.h:63
__IOM uint32_t READCTRL
Definition: efm32gg_msc.h:44
__IOM uint32_t IFC
Definition: efm32gg_msc.h:56
__IOM uint32_t ADDRB
Definition: efm32gg_msc.h:47
__IM uint32_t CACHEMISSES
Definition: efm32gg_msc.h:61
__IOM uint32_t IFS
Definition: efm32gg_msc.h:55
__IOM uint32_t WRITECTRL
Definition: efm32gg_msc.h:45
__IOM uint32_t CMD
Definition: efm32gg_msc.h:59
__IOM uint32_t CTRL
Definition: efm32gg_msc.h:43
__IM uint32_t IF
Definition: efm32gg_msc.h:54
__IOM uint32_t WRITECMD
Definition: efm32gg_msc.h:46