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EFM32 Gecko Software Documentation
efm32g-doc-5.1.2
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EFM32 Gecko Software Documentation
efm32g-doc-5.1.2
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| #define _RMU_CMD_MASK 0x00000001UL |
Mask for RMU_CMD
Definition at line 103 of file efm32g_rmu.h.
| #define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL |
Mode DEFAULT for RMU_CMD
Definition at line 107 of file efm32g_rmu.h.
| #define _RMU_CMD_RCCLR_MASK 0x1UL |
Bit mask for RMU_RCCLR
Definition at line 106 of file efm32g_rmu.h.
| #define _RMU_CMD_RCCLR_SHIFT 0 |
Shift value for RMU_RCCLR
Definition at line 105 of file efm32g_rmu.h.
| #define _RMU_CMD_RESETVALUE 0x00000000UL |
Default value for RMU_CMD
Definition at line 102 of file efm32g_rmu.h.
| #define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL |
Mode DEFAULT for RMU_CTRL
Definition at line 59 of file efm32g_rmu.h.
| #define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL |
Bit mask for RMU_LOCKUPRDIS
Definition at line 58 of file efm32g_rmu.h.
| #define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 |
Shift value for RMU_LOCKUPRDIS
Definition at line 57 of file efm32g_rmu.h.
| #define _RMU_CTRL_MASK 0x00000001UL |
Mask for RMU_CTRL
Definition at line 55 of file efm32g_rmu.h.
| #define _RMU_CTRL_RESETVALUE 0x00000000UL |
Default value for RMU_CTRL
Definition at line 54 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL |
Mode DEFAULT for RMU_RSTCAUSE
Definition at line 78 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL |
Bit mask for RMU_BODREGRST
Definition at line 77 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 |
Shift value for RMU_BODREGRST
Definition at line 76 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL |
Mode DEFAULT for RMU_RSTCAUSE
Definition at line 73 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL |
Bit mask for RMU_BODUNREGRST
Definition at line 72 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 |
Shift value for RMU_BODUNREGRST
Definition at line 71 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL |
Mode DEFAULT for RMU_RSTCAUSE
Definition at line 83 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL |
Bit mask for RMU_EXTRST
Definition at line 82 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_EXTRST_SHIFT 3 |
Shift value for RMU_EXTRST
Definition at line 81 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL |
Mode DEFAULT for RMU_RSTCAUSE
Definition at line 93 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL |
Bit mask for RMU_LOCKUPRST
Definition at line 92 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 |
Shift value for RMU_LOCKUPRST
Definition at line 91 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_MASK 0x0000007FUL |
Mask for RMU_RSTCAUSE
Definition at line 64 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL |
Mode DEFAULT for RMU_RSTCAUSE
Definition at line 68 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_PORST_MASK 0x1UL |
Bit mask for RMU_PORST
Definition at line 67 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_PORST_SHIFT 0 |
Shift value for RMU_PORST
Definition at line 66 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL |
Default value for RMU_RSTCAUSE
Definition at line 63 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL |
Mode DEFAULT for RMU_RSTCAUSE
Definition at line 98 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL |
Bit mask for RMU_SYSREQRST
Definition at line 97 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 |
Shift value for RMU_SYSREQRST
Definition at line 96 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL |
Mode DEFAULT for RMU_RSTCAUSE
Definition at line 88 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL |
Bit mask for RMU_WDOGRST
Definition at line 87 of file efm32g_rmu.h.
| #define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 |
Shift value for RMU_WDOGRST
Definition at line 86 of file efm32g_rmu.h.
| #define RMU_CMD_RCCLR (0x1UL << 0) |
| #define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) |
Shifted mode DEFAULT for RMU_CMD
Definition at line 108 of file efm32g_rmu.h.
| #define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) |
Lockup Reset Disable
Definition at line 56 of file efm32g_rmu.h.
| #define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) |
Shifted mode DEFAULT for RMU_CTRL
Definition at line 60 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) |
Brown Out Detector Regulated Domain Reset
Definition at line 75 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) |
Shifted mode DEFAULT for RMU_RSTCAUSE
Definition at line 79 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) |
Brown Out Detector Unregulated Domain Reset
Definition at line 70 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) |
Shifted mode DEFAULT for RMU_RSTCAUSE
Definition at line 74 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_EXTRST (0x1UL << 3) |
| #define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) |
Shifted mode DEFAULT for RMU_RSTCAUSE
Definition at line 84 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) |
| #define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) |
Shifted mode DEFAULT for RMU_RSTCAUSE
Definition at line 94 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_PORST (0x1UL << 0) |
Power On Reset
Definition at line 65 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) |
Shifted mode DEFAULT for RMU_RSTCAUSE
Definition at line 69 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) |
| #define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) |
Shifted mode DEFAULT for RMU_RSTCAUSE
Definition at line 99 of file efm32g_rmu.h.
| #define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) |
| #define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) |
Shifted mode DEFAULT for RMU_RSTCAUSE
Definition at line 89 of file efm32g_rmu.h.
1.8.10 
