efm32g_devinfo.h

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/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
typedef struct
{
  __IM uint32_t CAL;          
  __IM uint32_t ADC0CAL0;     
  __IM uint32_t ADC0CAL1;     
  __IM uint32_t ADC0CAL2;     
  uint32_t      RESERVED0[2]; 
  __IM uint32_t DAC0CAL0;     
  __IM uint32_t DAC0CAL1;     
  __IM uint32_t DAC0CAL2;     
  uint32_t      RESERVED1[2]; 
  __IM uint32_t HFRCOCAL0;    
  __IM uint32_t HFRCOCAL1;    
  __IM uint32_t MEMINFO;      
  uint32_t      RESERVED2[2]; 
  __IM uint32_t UNIQUEL;      
  __IM uint32_t UNIQUEH;      
  __IM uint32_t MSIZE;        
  __IM uint32_t PART;         
} DEVINFO_TypeDef;            
/**************************************************************************/
/* Bit fields for EFM32G_DEVINFO */
#define _DEVINFO_CAL_CRC_MASK                      0x0000FFFFUL 
#define _DEVINFO_CAL_CRC_SHIFT                     0            
#define _DEVINFO_CAL_TEMP_MASK                     0x00FF0000UL 
#define _DEVINFO_CAL_TEMP_SHIFT                    16           
#define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK           0x00007F00UL 
#define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT          8            
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK         0x0000007FUL 
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT        0            
#define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK            0x7F000000UL 
#define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT           24           
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK          0x007F0000UL 
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT         16           
#define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK            0x00007F00UL 
#define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT           8            
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK          0x0000007FUL 
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT         0            
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK         0x7F000000UL 
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT        24           
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK       0x007F0000UL 
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT      16           
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK     0x0000007FUL 
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT    0            
#define _DEVINFO_ADC0CAL2_TEMP1V25_MASK            0xFFF00000UL 
#define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT           20           
#define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK           0x007F0000UL 
#define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT          16           
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK     0x00003F00UL 
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT    8            
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK     0x0000003FUL 
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT    0            
#define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK            0x007F0000UL 
#define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT           16           
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK      0x00003F00UL 
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT     8            
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK      0x0000003FUL 
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT     0            
#define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK            0x007F0000UL 
#define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT           16           
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK      0x00003F00UL 
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT     8            
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK      0x0000003FUL 
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT     0            
#define _DEVINFO_HFRCOCAL0_BAND1_MASK              0x000000FFUL 
#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT             0            
#define _DEVINFO_HFRCOCAL0_BAND7_MASK              0x0000FF00UL 
#define _DEVINFO_HFRCOCAL0_BAND7_SHIFT             8            
#define _DEVINFO_HFRCOCAL0_BAND11_MASK             0x00FF0000UL 
#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT            16           
#define _DEVINFO_HFRCOCAL0_BAND14_MASK             0xFF000000UL 
#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT            24           
#define _DEVINFO_HFRCOCAL1_BAND21_MASK             0x000000FFUL 
#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT            0            
#define _DEVINFO_HFRCOCAL1_BAND28_MASK             0x0000FF00UL 
#define _DEVINFO_HFRCOCAL1_BAND28_SHIFT            8            
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK      0xFF000000UL 
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT     24           
#define _DEVINFO_UNIQUEL_MASK                      0xFFFFFFFFUL 
#define _DEVINFO_UNIQUEL_SHIFT                     0            
#define _DEVINFO_UNIQUEH_MASK                      0xFFFFFFFFUL 
#define _DEVINFO_UNIQUEH_SHIFT                     0            
#define _DEVINFO_MSIZE_SRAM_MASK                   0xFFFF0000UL 
#define _DEVINFO_MSIZE_SRAM_SHIFT                  16           
#define _DEVINFO_MSIZE_FLASH_MASK                  0x0000FFFFUL 
#define _DEVINFO_MSIZE_FLASH_SHIFT                 0            
#define _DEVINFO_PART_PROD_REV_MASK                0xFF000000UL 
#define _DEVINFO_PART_PROD_REV_SHIFT               24           
#define _DEVINFO_PART_DEVICE_FAMILY_MASK           0x00FF0000UL 
#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT          16           
/* Legacy family #defines */
#define _DEVINFO_PART_DEVICE_FAMILY_G              71           
#define _DEVINFO_PART_DEVICE_FAMILY_GG             72           
#define _DEVINFO_PART_DEVICE_FAMILY_TG             73           
#define _DEVINFO_PART_DEVICE_FAMILY_LG             74           
#define _DEVINFO_PART_DEVICE_FAMILY_WG             75           
#define _DEVINFO_PART_DEVICE_FAMILY_ZG             76           
#define _DEVINFO_PART_DEVICE_FAMILY_HG             77           
/* New style family #defines */
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32G         71           
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG        72           
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG        73           
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG        74           
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG        75           
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG        76           
#define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG        77           
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG        120          
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG        121          
#define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG        122          
#define _DEVINFO_PART_DEVICE_NUMBER_MASK           0x0000FFFFUL 
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT          0