ezr32hg/html/ezr32hg320f64r69_8h_source.html

 /**************************************************************************/

 #ifndef EZR32HG320F64R69_H

 #define EZR32HG320F64R69_H


 #ifdef __cplusplus

 extern "C" {

 #endif


 /**************************************************************************/

 /**************************************************************************/

 typedef enum IRQn

 {

 /******  Cortex-M0+ Processor Exceptions Numbers *****************************************/

   NonMaskableInt_IRQn = -14,

   HardFault_IRQn      = -13,

   SVCall_IRQn         = -5,

   PendSV_IRQn         = -2,

   SysTick_IRQn        = -1,

 /******  EZR32HG Peripheral Interrupt Numbers ********************************************/

   DMA_IRQn            = 0,

   GPIO_EVEN_IRQn      = 1,

   TIMER0_IRQn         = 2,

   ADC0_IRQn           = 4,

   I2C0_IRQn           = 5,

   GPIO_ODD_IRQn       = 6,

   TIMER1_IRQn         = 7,

   USARTRF1_RX_IRQn    = 8,

   USARTRF1_TX_IRQn    = 9,

   LEUART0_IRQn        = 10,

   PCNT0_IRQn          = 11,

   RTC_IRQn            = 12,

   CMU_IRQn            = 13,

   VCMP_IRQn           = 14,

   MSC_IRQn            = 15,

   AES_IRQn            = 16,

   USART0_RX_IRQn      = 17,

   USART0_TX_IRQn      = 18,

   USB_IRQn            = 19,

   TIMER2_IRQn         = 20,

 } IRQn_Type;


 /**************************************************************************/

 #define __MPU_PRESENT             0

 #define __VTOR_PRESENT            1

 #define __NVIC_PRIO_BITS          2

 #define __Vendor_SysTickConfig    0

 /**************************************************************************/

 #define _EFM32_HAPPY_FAMILY                     1

 #define _EFM_DEVICE

 #define _EZR32_HAPPY_FAMILY                     1

 #define _EZR_DEVICE

 #define _SILICON_LABS_32B_SERIES_0

 #define _SILICON_LABS_32B_SERIES                0

 #define _SILICON_LABS_GECKO_INTERNAL_SDID       77

 #define _SILICON_LABS_GECKO_INTERNAL_SDID_77

 #define _SILICON_LABS_32B_PLATFORM_1

 #define _SILICON_LABS_32B_PLATFORM              1

 /* If part number is not defined as compiler option, define it */

 #if !defined(EZR32HG320F64R69)

 #define EZR32HG320F64R69    1

 #endif


 #define PART_NUMBER          "EZR32HG320F64R69"

 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)

 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL)

 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)

 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)

 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL)

 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)

 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL)

 #define AES_MEM_BITS         ((uint32_t) 0x10UL)

 #define USBC_MEM_BASE        ((uint32_t) 0x40100000UL)

 #define USBC_MEM_SIZE        ((uint32_t) 0x40000UL)

 #define USBC_MEM_END         ((uint32_t) 0x4013FFFFUL)

 #define USBC_MEM_BITS        ((uint32_t) 0x18UL)

 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL)

 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)

 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL)

 #define PER_MEM_BITS         ((uint32_t) 0x20UL)

 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL)

 #define RAM_MEM_SIZE         ((uint32_t) 0x40000UL)

 #define RAM_MEM_END          ((uint32_t) 0x2003FFFFUL)

 #define RAM_MEM_BITS         ((uint32_t) 0x18UL)

 #define DEVICE_MEM_BASE      ((uint32_t) 0xF0040000UL)

 #define DEVICE_MEM_SIZE      ((uint32_t) 0x1000UL)

 #define DEVICE_MEM_END       ((uint32_t) 0xF0040FFFUL)

 #define DEVICE_MEM_BITS      ((uint32_t) 0x12UL)

 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL)

 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x20000UL)

 #define RAM_CODE_MEM_END     ((uint32_t) 0x1001FFFFUL)

 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x17UL)

 #define FLASH_BASE           (0x00000000UL)

 #define FLASH_SIZE           (0x00010000UL)

 #define FLASH_PAGE_SIZE      1024

 #define SRAM_BASE            (0x20000000UL)

 #define SRAM_SIZE            (0x00002000UL)

 #define __CM0PLUS_REV        0x001

 #define PRS_CHAN_COUNT       6

 #define DMA_CHAN_COUNT       6

 #define EXT_IRQ_COUNT        20

 #define AFCHAN_MAX           42

 #define AFCHANLOC_MAX        7


 #define AFACHAN_MAX          27


 /* Part number capabilities */


 #define TIMER_PRESENT

 #define TIMER_COUNT             3

 #define USART_PRESENT

 #define USART_COUNT             1

 #define USARTRF_PRESENT

 #define USARTRF_COUNT           1

 #define IDAC_PRESENT

 #define IDAC_COUNT              1

 #define ADC_PRESENT

 #define ADC_COUNT               1

 #define LEUART_PRESENT

 #define LEUART_COUNT            1

 #define PCNT_PRESENT

 #define PCNT_COUNT              1

 #define I2C_PRESENT

 #define I2C_COUNT               1

 #define AES_PRESENT

 #define AES_COUNT               1

 #define DMA_PRESENT

 #define DMA_COUNT               1

 #define LE_PRESENT

 #define LE_COUNT                1

 #define USBC_PRESENT

 #define USBC_COUNT              1

 #define USBLE_PRESENT

 #define USBLE_COUNT             1

 #define USB_PRESENT

 #define USB_COUNT               1

 #define MSC_PRESENT

 #define MSC_COUNT               1

 #define EMU_PRESENT

 #define EMU_COUNT               1

 #define RMU_PRESENT

 #define RMU_COUNT               1

 #define CMU_PRESENT

 #define CMU_COUNT               1

 #define PRS_PRESENT

 #define PRS_COUNT               1

 #define GPIO_PRESENT

 #define GPIO_COUNT              1

 #define VCMP_PRESENT

 #define VCMP_COUNT              1

 #define RTC_PRESENT

 #define RTC_COUNT               1

 #define HFXTAL_PRESENT

 #define HFXTAL_COUNT            1

 #define LFXTAL_PRESENT

 #define LFXTAL_COUNT            1

 #define USHFRCO_PRESENT

 #define USHFRCO_COUNT           1

 #define WDOG_PRESENT

 #define WDOG_COUNT              1

 #define DBG_PRESENT

 #define DBG_COUNT               1

 #define MTB_PRESENT

 #define MTB_COUNT               1

 #define BOOTLOADER_PRESENT

 #define BOOTLOADER_COUNT        1

 #define ANALOG_PRESENT

 #define ANALOG_COUNT            1


 /**************************************************************************/

 #define RF_USARTRF_LOCATION     5

 #define RF_USARTRF_CS_PORT      2

 #define RF_USARTRF_CS_PIN       0

 #define RF_USARTRF_CLK_PORT     2

 #define RF_USARTRF_CLK_PIN      3

 #define RF_USARTRF_MISO_PORT    2

 #define RF_USARTRF_MISO_PIN     2

 #define RF_USARTRF_MOSI_PORT    2

 #define RF_USARTRF_MOSI_PIN     1

 #define RF_INT_PORT             2

 #define RF_INT_PIN              4

 #define RF_SDN_PORT             0

 #define RF_SDN_PIN              2

 #define ARM_MATH_CM0PLUS

 #include "arm_math.h"       /* To get __CLZ definitions etc. */

 #include "core_cm0plus.h"   /* Cortex-M0+ processor and core peripherals */

 #include "system_ezr32hg.h" /* System Header */


 /**************************************************************************/

 #include "ezr32hg_aes.h"

 #include "ezr32hg_dma_ch.h"

 #include "ezr32hg_dma.h"

 #include "ezr32hg_usb_diep.h"

 #include "ezr32hg_usb_doep.h"

 #include "ezr32hg_usb.h"

 #include "ezr32hg_msc.h"

 #include "ezr32hg_emu.h"

 #include "ezr32hg_rmu.h"

 #include "ezr32hg_cmu.h"

 #include "ezr32hg_timer_cc.h"

 #include "ezr32hg_timer.h"

 #include "ezr32hg_usart.h"

 #include "ezr32hg_prs_ch.h"

 #include "ezr32hg_prs.h"

 #include "ezr32hg_idac.h"

 #include "ezr32hg_gpio_p.h"

 #include "ezr32hg_gpio.h"

 #include "ezr32hg_vcmp.h"

 #include "ezr32hg_adc.h"

 #include "ezr32hg_leuart.h"

 #include "ezr32hg_pcnt.h"

 #include "ezr32hg_i2c.h"

 #include "ezr32hg_rtc.h"

 #include "ezr32hg_wdog.h"

 #include "ezr32hg_mtb.h"

 #include "ezr32hg_dma_descriptor.h"

 #include "ezr32hg_devinfo.h"

 #include "ezr32hg_romtable.h"

 #include "ezr32hg_calibrate.h"


 /**************************************************************************/

 #define AES_BASE          (0x400E0000UL)

 #define DMA_BASE          (0x400C2000UL)

 #define USB_BASE          (0x400C4000UL)

 #define MSC_BASE          (0x400C0000UL)

 #define EMU_BASE          (0x400C6000UL)

 #define RMU_BASE          (0x400CA000UL)

 #define CMU_BASE          (0x400C8000UL)

 #define TIMER0_BASE       (0x40010000UL)

 #define TIMER1_BASE       (0x40010400UL)

 #define TIMER2_BASE       (0x40010800UL)

 #define USART0_BASE       (0x4000C000UL)

 #define USARTRF1_BASE     (0x4000C400UL)

 #define PRS_BASE          (0x400CC000UL)

 #define IDAC0_BASE        (0x40004000UL)

 #define GPIO_BASE         (0x40006000UL)

 #define VCMP_BASE         (0x40000000UL)

 #define ADC0_BASE         (0x40002000UL)

 #define LEUART0_BASE      (0x40084000UL)

 #define PCNT0_BASE        (0x40086000UL)

 #define I2C0_BASE         (0x4000A000UL)

 #define RTC_BASE          (0x40080000UL)

 #define WDOG_BASE         (0x40088000UL)

 #define MTB_BASE          (0xF0040000UL)

 #define CALIBRATE_BASE    (0x0FE08000UL)

 #define DEVINFO_BASE      (0x0FE081A8UL)

 #define ROMTABLE_BASE     (0xF00FFFD0UL)

 #define LOCKBITS_BASE     (0x0FE04000UL)

 #define USERDATA_BASE     (0x0FE00000UL)

 /**************************************************************************/

 #define AES          ((AES_TypeDef *) AES_BASE)

 #define DMA          ((DMA_TypeDef *) DMA_BASE)

 #define USB          ((USB_TypeDef *) USB_BASE)

 #define MSC          ((MSC_TypeDef *) MSC_BASE)

 #define EMU          ((EMU_TypeDef *) EMU_BASE)

 #define RMU          ((RMU_TypeDef *) RMU_BASE)

 #define CMU          ((CMU_TypeDef *) CMU_BASE)

 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)

 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)

 #define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)

 #define USART0       ((USART_TypeDef *) USART0_BASE)

 #define USARTRF1     ((USART_TypeDef *) USARTRF1_BASE)

 #define PRS          ((PRS_TypeDef *) PRS_BASE)

 #define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)

 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)

 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)

 #define ADC0         ((ADC_TypeDef *) ADC0_BASE)

 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)

 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)

 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)

 #define RTC          ((RTC_TypeDef *) RTC_BASE)

 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)

 #define MTB          ((MTB_TypeDef *) MTB_BASE)

 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE)

 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)

 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)

 /**************************************************************************/

 #include "ezr32hg_prs_signals.h"

 #include "ezr32hg_dmareq.h"

 #include "ezr32hg_dmactrl.h"

 #include "ezr32hg_usartrf.h"


 /**************************************************************************/

 #define MSC_UNLOCK_CODE      0x1B71

 #define EMU_UNLOCK_CODE      0xADE8

 #define CMU_UNLOCK_CODE      0x580E

 #define TIMER_UNLOCK_CODE    0xCE80

 #define GPIO_UNLOCK_CODE     0xA534

 /**************************************************************************/

 #include "ezr32hg_af_ports.h"

 #include "ezr32hg_af_pins.h"


 /**************************************************************************/

 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \

   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));


 #ifdef __cplusplus

 }

 #endif

 #endif /* EZR32HG320F64R69_H */

system_ezr32hg.h
CMSIS Cortex-M System Layer for EZR32HG devices.

ezr32hg_timer_cc.h
EZR32HG_TIMER_CC register and bit field definitions.

USART0_RX_IRQn
Definition: ezr32hg320f64r69.h:78

ezr32hg_gpio_p.h
EZR32HG_GPIO_P register and bit field definitions.

ezr32hg_i2c.h
EZR32HG_I2C register and bit field definitions.

LEUART0_IRQn
Definition: ezr32hg320f64r69.h:71

ezr32hg_rmu.h
EZR32HG_RMU register and bit field definitions.

ezr32hg_timer.h
EZR32HG_TIMER register and bit field definitions.

ezr32hg_af_pins.h
EZR32HG_AF_PINS register and bit field definitions.

PCNT0_IRQn
Definition: ezr32hg320f64r69.h:72

ezr32hg_adc.h
EZR32HG_ADC register and bit field definitions.

SysTick_IRQn
Definition: ezr32hg320f64r69.h:59

TIMER0_IRQn
Definition: ezr32hg320f64r69.h:64

ezr32hg_dma_ch.h
EZR32HG_DMA_CH register and bit field definitions.

ezr32hg_rtc.h
EZR32HG_RTC register and bit field definitions.

IRQn
IRQn
Definition: ezr32hg320f64r69.h:52

USB_IRQn
Definition: ezr32hg320f64r69.h:80

MSC_IRQn
Definition: ezr32hg320f64r69.h:76

ezr32hg_dmactrl.h
EZR32HG_DMACTRL register and bit field definitions.

DMA_IRQn
Definition: ezr32hg320f64r69.h:62

AES_IRQn
Definition: ezr32hg320f64r69.h:77

ezr32hg_aes.h
EZR32HG_AES register and bit field definitions.

NonMaskableInt_IRQn
Definition: ezr32hg320f64r69.h:55

ezr32hg_dmareq.h
EZR32HG_DMAREQ register and bit field definitions.

ezr32hg_prs.h
EZR32HG_PRS register and bit field definitions.

ezr32hg_devinfo.h
EZR32HG_DEVINFO register and bit field definitions.

ezr32hg_prs_ch.h
EZR32HG_PRS_CH register and bit field definitions.

GPIO_ODD_IRQn
Definition: ezr32hg320f64r69.h:67

SVCall_IRQn
Definition: ezr32hg320f64r69.h:57

ezr32hg_usartrf.h
EZR32HG_USARTRF register and bit field definitions.

TIMER1_IRQn
Definition: ezr32hg320f64r69.h:68

ezr32hg_msc.h
EZR32HG_MSC register and bit field definitions.

TIMER2_IRQn
Definition: ezr32hg320f64r69.h:81

ezr32hg_idac.h
EZR32HG_IDAC register and bit field definitions.

HardFault_IRQn
Definition: ezr32hg320f64r69.h:56

ADC0_IRQn
Definition: ezr32hg320f64r69.h:65

ezr32hg_dma.h
EZR32HG_DMA register and bit field definitions.

CMU_IRQn
Definition: ezr32hg320f64r69.h:74

ezr32hg_vcmp.h
EZR32HG_VCMP register and bit field definitions.

I2C0_IRQn
Definition: ezr32hg320f64r69.h:66

ezr32hg_dma_descriptor.h
EZR32HG_DMA_DESCRIPTOR register and bit field definitions.

ezr32hg_leuart.h
EZR32HG_LEUART register and bit field definitions.

ezr32hg_mtb.h
EZR32HG_MTB register and bit field definitions.

IRQn_Type
enum IRQn IRQn_Type

ezr32hg_usb_doep.h
EZR32HG_USB_DOEP register and bit field definitions.

ezr32hg_usart.h
EZR32HG_USART register and bit field definitions.

ezr32hg_gpio.h
EZR32HG_GPIO register and bit field definitions.

ezr32hg_romtable.h
EZR32HG_ROMTABLE register and bit field definitions.

RTC_IRQn
Definition: ezr32hg320f64r69.h:73

PendSV_IRQn
Definition: ezr32hg320f64r69.h:58

GPIO_EVEN_IRQn
Definition: ezr32hg320f64r69.h:63

USARTRF1_RX_IRQn
Definition: ezr32hg320f64r69.h:69

ezr32hg_usb_diep.h
EZR32HG_USB_DIEP register and bit field definitions.

VCMP_IRQn
Definition: ezr32hg320f64r69.h:75

ezr32hg_cmu.h
EZR32HG_CMU register and bit field definitions.

USART0_TX_IRQn
Definition: ezr32hg320f64r69.h:79

ezr32hg_wdog.h
EZR32HG_WDOG register and bit field definitions.

ezr32hg_emu.h
EZR32HG_EMU register and bit field definitions.

USARTRF1_TX_IRQn
Definition: ezr32hg320f64r69.h:70

ezr32hg_pcnt.h
EZR32HG_PCNT register and bit field definitions.

ezr32hg_calibrate.h
EZR32HG_CALIBRATE register and bit field definitions.

ezr32hg_usb.h
EZR32HG_USB register and bit field definitions.