EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
si7210_regs.h
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1 /***************************************************************************/
16 #ifndef __SI7210_REGS_H_
17 #define __SI7210_REGS_H_
18 
19 /***************************************************************************/
25 /***************************************************************************/
32 #define SI7210_REG_ADDR_HREVID 0xC0
33 #define SI7210_REG_ADDR_DSPSIGM 0xC1
34 #define SI7210_REG_ADDR_DSPSIGL 0xC2
35 #define SI7210_REG_ADDR_DSPSIGSEL 0xC3
36 #define SI7210_REG_ADDR_POWER_CTRL 0xC4
37 #define SI7210_REG_ADDR_ARAUTOINC 0xC5
38 #define SI7210_REG_ADDR_CTRL1 0xC6
39 #define SI7210_REG_ADDR_CTRL2 0xC7
40 #define SI7210_REG_ADDR_SLTIME 0xC8
41 #define SI7210_REG_ADDR_CTRL3 0xC9
42 #define SI7210_REG_ADDR_A0 0xCA
43 #define SI7210_REG_ADDR_A1 0xCB
44 #define SI7210_REG_ADDR_A2 0xCC
45 #define SI7210_REG_ADDR_CTRL4 0xCD
46 #define SI7210_REG_ADDR_A3 0xCE
47 #define SI7210_REG_ADDR_A4 0xCF
48 #define SI7210_REG_ADDR_A5 0xD0
49 #define SI7210_REG_ADDR_OTP_ADDR 0xE1
50 #define SI7210_REG_ADDR_OTP_DATA 0xE2
51 #define SI7210_REG_ADDR_OTP_CTRL 0xE3
52 #define SI7210_REG_ADDR_TM_FG 0xE4
57 /***************************************************************************/
64 #define SI7210_REG_HREVID_REVID_MASK 0x0F
65 #define SI7210_REG_HREVID_REVID_SHIFT 0
66 #define SI7210_REG_HREVID_CHIPID_MASK 0xF0
67 #define SI7210_REG_HREVID_CHIPID_SHIFT 4
69 #define SI7210_REG_POWER_CTRL_SLEEP_MASK 0x01
70 #define SI7210_REG_POWER_CTRL_SLEEP_SHIFT 0
71 #define SI7210_REG_POWER_CTRL_STOP_MASK 0x02
72 #define SI7210_REG_POWER_CTRL_STOP_SHIFT 1
73 #define SI7210_REG_POWER_CTRL_ONEBURST_MASK 0x04
74 #define SI7210_REG_POWER_CTRL_ONEBURST_SHIFT 2
75 #define SI7210_REG_POWER_CTRL_USESTORE_MASK 0x08
76 #define SI7210_REG_POWER_CTRL_USESTORE_SHIFT 3
77 #define SI7210_REG_POWER_CTRL_MEAS_MASK 0x80
78 #define SI7210_REG_POWER_CTRL_MEAS_SHIFT 7
80 #define SI7210_REG_CTRL1_SW_OP_MASK 0x7F
81 #define SI7210_REG_CTRL1_SW_OP_SHIFT 0
82 #define SI7210_REG_CTRL1_SW_LOW4FIELD_MASK 0x80
83 #define SI7210_REG_CTRL1_SW_LOW4FIELD_SHIFT 7
85 #define SI7210_REG_CTRL2_SW_HYST_MASK 0x3F
86 #define SI7210_REG_CTRL2_SW_HYST_SHIFT 0
87 #define SI7210_REG_CTRL2_SW_FIELDPOLSEL_MASK 0xC0
88 #define SI7210_REG_CTRL2_SW_FIELDPOLSEL_SHIFT 6
90 #define SI7210_REG_CTRL3_SLTIMEENA_MASK 0x01
91 #define SI7210_REG_CTRL3_SLTIMEENA_SHIFT 0
92 #define SI7210_REG_CTRL3_SLFAST_MASK 0x02
93 #define SI7210_REG_CTRL3_SLFAST_SHIFT 1
94 #define SI7210_REG_CTRL3_SW_TAMPER_MASK 0xFC
95 #define SI7210_REG_CTRL3_SW_TAMPER_SHIFT 2
97 #define SI7210_REG_OTP_CTRL_BUSY_MASK 0x01
98 #define SI7210_REG_OTP_CTRL_BUSY_SHIFT 0
99 #define SI7210_REG_OTP_CTRL_READ_EN_MASK 0x02
100 #define SI7210_REG_OTP_CTRL_READ_EN_SHIFT 1
105 /***************************************************************************/
112 #define SI7210_OTP_ADDR_CTRL1 0x04
113 #define SI7210_OTP_ADDR_CTRL2 0x05
114 #define SI7210_OTP_ADDR_SLTIME 0x06
115 #define SI7210_OTP_ADDR_CTRL3 0x08
116 #define SI7210_OTP_ADDR_POWER_UP_A0 0x09
117 #define SI7210_OTP_ADDR_POWER_UP_A1 0x0A
118 #define SI7210_OTP_ADDR_POWER_UP_A2 0x0B
119 #define SI7210_OTP_ADDR_CTRL4 0x0C
120 #define SI7210_OTP_ADDR_POWER_UP_A3 0x0D
121 #define SI7210_OTP_ADDR_POWER_UP_A4 0x0E
122 #define SI7210_OTP_ADDR_POWER_UP_A5 0x0F
123 #define SI7210_OTP_ADDR_BASE_PART_NUMBER 0x14
124 #define SI7210_OTP_ADDR_VARIANT 0x15
125 #define SI7210_OTP_ADDR_SERIAL_NUMBER 0x18
126 #define SI7210_OTP_ADDR_BPERVCAL 0x20
128 #define SI7210_OTP_ADDR_COEFFS_20MT 0x21
129 #define SI7210_OTP_ADDR_COEFFS_200MT 0x27
130 #define SI7210_OTP_ADDR_COEFFS_20MT_NEODYMIUM 0x2D
131 #define SI7210_OTP_ADDR_COEFFS_200MT_NEODYMIUM 0x33
132 #define SI7210_OTP_ADDR_COEFFS_20MT_CERAMIC 0x39
133 #define SI7210_OTP_ADDR_COEFFS_200MT_CERAMIC 0x3F
141 #endif /* __SI7210_REGS_H_ */