EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
em_opamp.h
Go to the documentation of this file.
1 /**************************************************************************/
33 #ifndef EM_OPAMP_H
34 #define EM_OPAMP_H
35 
36 #include "em_device.h"
37 #if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \
38  || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0)))
39 
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43 
44 #include <stdint.h>
45 #include <stdbool.h>
46 
47 #if defined(_SILICON_LABS_32B_SERIES_0)
48 #include "em_dac.h"
49 #elif defined (_SILICON_LABS_32B_SERIES_1)
50 #include "em_vdac.h"
51 #endif
52 
53 /***************************************************************************/
58 /***************************************************************************/
66 #if defined(_SILICON_LABS_32B_SERIES_0)
67 #define DAC_OPA_VALID(opa) ((opa) <= OPA2)
68 #elif defined(_SILICON_LABS_32B_SERIES_1)
69 #define VDAC_OPA_VALID(opa) ((opa) <= OPA2)
70 #endif
71 
74 /*******************************************************************************
75  ******************************** ENUMS ************************************
76  ******************************************************************************/
77 
79 typedef enum
80 {
81  OPA0 = 0,
82  OPA1 = 1,
83  OPA2 = 2
84 } OPAMP_TypeDef;
85 
87 typedef enum
88 {
89 #if defined(_SILICON_LABS_32B_SERIES_0)
90  opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE,
91  opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG,
92  opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP,
93  opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD
94 #elif defined(_SILICON_LABS_32B_SERIES_1)
95  opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1,
96  opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3,
97  opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5,
98  opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7,
99  opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9,
100  opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11,
101  opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13,
102  opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15,
103  opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17,
104  opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19,
105  opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21,
106  opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23,
107  opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25,
108  opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27,
109  opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29,
110  opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31,
111  opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0,
112  opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2,
113  opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4,
114  opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6,
115  opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8,
116  opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10,
117  opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12,
118  opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14,
119  opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16,
120  opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18,
121  opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20,
122  opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22,
123  opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24,
124  opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26,
125  opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28,
126  opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30,
127  opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1,
128  opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3,
129  opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5,
130  opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7,
131  opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9,
132  opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11,
133  opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13,
134  opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15,
135  opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17,
136  opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19,
137  opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21,
138  opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23,
139  opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25,
140  opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27,
141  opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29,
142  opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31,
143  opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0,
144  opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2,
145  opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4,
146  opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6,
147  opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8,
148  opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10,
149  opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12,
150  opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14,
151  opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16,
152  opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18,
153  opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20,
154  opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22,
155  opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24,
156  opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26,
157  opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28,
158  opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30,
159  opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE,
160  opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG,
161  opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP,
162  opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD
163 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
164 } OPAMP_NegSel_TypeDef;
165 
167 typedef enum
168 {
169 #if defined(_SILICON_LABS_32B_SERIES_0)
170  opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE,
171  opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC,
172  opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD,
173  opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP,
174  opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP
175 #elif defined(_SILICON_LABS_32B_SERIES_1)
176  opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0,
177  opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2,
178  opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4,
179  opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6,
180  opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8,
181  opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10,
182  opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12,
183  opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14,
184  opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16,
185  opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18,
186  opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20,
187  opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22,
188  opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24,
189  opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26,
190  opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28,
191  opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30,
192  opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1,
193  opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3,
194  opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5,
195  opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7,
196  opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9,
197  opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11,
198  opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13,
199  opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15,
200  opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17,
201  opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19,
202  opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21,
203  opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23,
204  opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25,
205  opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27,
206  opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29,
207  opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31,
208  opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0,
209  opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2,
210  opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4,
211  opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6,
212  opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8,
213  opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10,
214  opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12,
215  opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14,
216  opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16,
217  opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18,
218  opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20,
219  opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22,
220  opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24,
221  opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26,
222  opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28,
223  opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30,
224  opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1,
225  opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3,
226  opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5,
227  opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7,
228  opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9,
229  opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11,
230  opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13,
231  opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15,
232  opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17,
233  opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19,
234  opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21,
235  opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23,
236  opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25,
237  opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27,
238  opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29,
239  opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31,
240  opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE,
241  opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC,
242  opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD,
243  opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT,
244  opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP
245 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
246 } OPAMP_PosSel_TypeDef;
247 
249 typedef enum
250 {
251 #if defined(_SILICON_LABS_32B_SERIES_0)
252  opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE,
253  opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN,
254  opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT,
255  opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL
256 #elif defined(_SILICON_LABS_32B_SERIES_1)
257  opaOutModeDisable = 0,
258  opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN,
259  opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN,
260  opaOutModeAll = VDAC_OPA_OUT_SHORT,
261  opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1),
262  opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3),
263  opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5),
264  opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7),
265  opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9),
266  opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11),
267  opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13),
268  opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15),
269  opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17),
270  opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19),
271  opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21),
272  opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23),
273  opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25),
274  opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27),
275  opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29),
276  opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31),
277  opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0),
278  opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2),
279  opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4),
280  opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6),
281  opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8),
282  opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10),
283  opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12),
284  opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14),
285  opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16),
286  opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18),
287  opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20),
288  opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22),
289  opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24),
290  opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26),
291  opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28),
292  opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30),
293  opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1),
294  opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3),
295  opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5),
296  opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7),
297  opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9),
298  opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11),
299  opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13),
300  opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15),
301  opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17),
302  opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19),
303  opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21),
304  opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23),
305  opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25),
306  opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27),
307  opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29),
308  opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31),
309  opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0),
310  opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2),
311  opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4),
312  opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6),
313  opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8),
314  opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10),
315  opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12),
316  opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14),
317  opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16),
318  opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18),
319  opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20),
320  opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22),
321  opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24),
322  opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26),
323  opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28),
324  opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30),
325 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
326 } OPAMP_OutMode_TypeDef;
327 
329 typedef enum
330 {
331 #if defined(_SILICON_LABS_32B_SERIES_0)
332  opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT,
333  opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0,
334  opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1,
335  opaResSelR1eq1_67R1 = DAC_OPA0MUX_RESSEL_RES2,
336  opaResSelR2eq2R1 = DAC_OPA0MUX_RESSEL_RES3,
337  opaResSelR2eq3R1 = DAC_OPA0MUX_RESSEL_RES4,
338  opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5,
339  opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6,
340  opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7
341 #elif defined(_SILICON_LABS_32B_SERIES_1)
342  opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT,
343  opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0,
344  opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1,
345  opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2,
346  opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3,
347  opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4,
348  opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5,
349  opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6,
350  opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7
351 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
352 } OPAMP_ResSel_TypeDef;
353 
355 typedef enum
356 {
357 #if defined(_SILICON_LABS_32B_SERIES_0)
358  opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE,
359  opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP,
360  opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD,
361  opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD,
362  opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS
363 #elif defined(_SILICON_LABS_32B_SERIES_1)
364  opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE,
365  opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT,
366  opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD,
367  opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD,
368  opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD,
370  opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER,
372  opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS,
373 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
374 } OPAMP_ResInMux_TypeDef;
375 
376 #if defined(_SILICON_LABS_32B_SERIES_1)
377 typedef enum
378 {
379  opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT,
380  opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED,
383  opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED,
386 } OPAMP_PrsMode_TypeDef;
387 
388 typedef enum
389 {
390  opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT,
391  opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0,
392  opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1,
393  opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2,
394  opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3,
395  opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4,
396  opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5,
397  opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6,
398  opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7,
399  opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8,
400  opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9,
401  opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10,
402  opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11,
403 } OPAMP_PrsSel_TypeDef;
404 
405 typedef enum
406 {
407  opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT,
408  opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM,
409  opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID,
410 } OPAMP_PrsOut_TypeDef;
411 
412 typedef enum
413 {
414  opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT,
415  opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL,
416  opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF,
417 } OPAMP_OutScale_Typedef;
418 
419 typedef enum
420 {
421  opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT,
422  opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT),
423  opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT),
424  opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT),
425  opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT),
426 } OPAMP_DrvStr_Typedef;
427 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
428 
429 /*******************************************************************************
430  ******************************* STRUCTS ***********************************
431  ******************************************************************************/
432 
434 typedef struct
435 {
436  OPAMP_NegSel_TypeDef negSel;
437  OPAMP_PosSel_TypeDef posSel;
438  OPAMP_OutMode_TypeDef outMode;
439  OPAMP_ResSel_TypeDef resSel;
440  OPAMP_ResInMux_TypeDef resInMux;
441  uint32_t outPen;
485 #if defined(_SILICON_LABS_32B_SERIES_0)
486  uint32_t bias;
487  bool halfBias;
488  bool lpfPosPadDisable;
489  bool lpfNegPadDisable;
490  bool nextOut;
491  bool npEn;
492  bool ppEn;
493  bool shortInputs;
494  bool hcmDisable;
495  bool defaultOffset;
496  uint32_t offset;
498 #elif defined(_SILICON_LABS_32B_SERIES_1)
499  OPAMP_DrvStr_Typedef drvStr;
500  bool gain3xEn;
501  bool halfDrvStr;
502  bool ugBwScale;
503  bool prsEn;
504  OPAMP_PrsMode_TypeDef prsMode;
505  OPAMP_PrsSel_TypeDef prsSel;
506  OPAMP_PrsOut_TypeDef prsOutSel;
507  bool aportYMasterDisable;
508  bool aportXMasterDisable;
509  uint32_t settleTime;
510  uint32_t startupDly;
511  bool hcmDisable;
512  bool defaultOffsetN;
514  uint32_t offsetN;
516  bool defaultOffsetP;
518  uint32_t offsetP;
520 #endif /* defined(_SILICON_LABS_32B_SERIES_1) */
521 } OPAMP_Init_TypeDef;
522 
523 #if defined(_SILICON_LABS_32B_SERIES_0)
524 
525 #define OPA_INIT_UNITY_GAIN \
526 { \
527  opaNegSelUnityGain, /* Unity gain. */ \
528  opaPosSelPosPad, /* Pos input from pad. */ \
529  opaOutModeMain, /* Main output enabled. */ \
530  opaResSelDefault, /* Resistor ladder is not used. */ \
531  opaResInMuxDisable, /* Resistor ladder disabled. */ \
532  0, /* No alternate outputs enabled. */ \
533  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
534  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
535  false, /* No low pass filter on pos pad. */ \
536  false, /* No low pass filter on neg pad. */ \
537  false, /* No nextout output enabled. */ \
538  false, /* Neg pad disabled. */ \
539  true, /* Pos pad enabled, used as signal input. */ \
540  false, /* No shorting of inputs. */ \
541  false, /* Rail-to-rail input enabled. */ \
542  true, /* Use factory calibrated opamp offset. */ \
543  0 /* Opamp offset value (not used). */ \
544 }
545 
547 #define OPA_INIT_UNITY_GAIN_OPA2 \
548 { \
549  opaNegSelUnityGain, /* Unity gain. */ \
550  opaPosSelPosPad, /* Pos input from pad. */ \
551  opaOutModeMain, /* Main output enabled. */ \
552  opaResSelDefault, /* Resistor ladder is not used. */ \
553  opaResInMuxDisable, /* Resistor ladder disabled. */ \
554  DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
555  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
556  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
557  false, /* No low pass filter on pos pad. */ \
558  false, /* No low pass filter on neg pad. */ \
559  false, /* No nextout output enabled. */ \
560  false, /* Neg pad disabled. */ \
561  true, /* Pos pad enabled, used as signal input. */ \
562  false, /* No shorting of inputs. */ \
563  false, /* Rail-to-rail input enabled. */ \
564  true, /* Use factory calibrated opamp offset. */ \
565  0 /* Opamp offset value (not used). */ \
566 }
567 
569 #define OPA_INIT_NON_INVERTING \
570 { \
571  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
572  opaPosSelPosPad, /* Pos input from pad. */ \
573  opaOutModeMain, /* Main output enabled. */ \
574  opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
575  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
576  0, /* No alternate outputs enabled. */ \
577  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
578  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
579  false, /* No low pass filter on pos pad. */ \
580  false, /* No low pass filter on neg pad. */ \
581  false, /* No nextout output enabled. */ \
582  true, /* Neg pad enabled, used as signal ground. */ \
583  true, /* Pos pad enabled, used as signal input. */ \
584  false, /* No shorting of inputs. */ \
585  false, /* Rail-to-rail input enabled. */ \
586  true, /* Use factory calibrated opamp offset. */ \
587  0 /* Opamp offset value (not used). */ \
588 }
589 
591 #define OPA_INIT_NON_INVERTING_OPA2 \
592 { \
593  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
594  opaPosSelPosPad, /* Pos input from pad. */ \
595  opaOutModeMain, /* Main output enabled. */ \
596  opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
597  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
598  DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
599  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
600  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
601  false, /* No low pass filter on pos pad. */ \
602  false, /* No low pass filter on neg pad. */ \
603  false, /* No nextout output enabled. */ \
604  true, /* Neg pad enabled, used as signal ground. */ \
605  true, /* Pos pad enabled, used as signal input. */ \
606  false, /* No shorting of inputs. */ \
607  false, /* Rail-to-rail input enabled. */ \
608  true, /* Use factory calibrated opamp offset. */ \
609  0 /* Opamp offset value (not used). */ \
610 }
611 
613 #define OPA_INIT_INVERTING \
614 { \
615  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
616  opaPosSelPosPad, /* Pos input from pad. */ \
617  opaOutModeMain, /* Main output enabled. */ \
618  opaResSelR2eqR1, /* R2 = R1 */ \
619  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
620  0, /* No alternate outputs enabled. */ \
621  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
622  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
623  false, /* No low pass filter on pos pad. */ \
624  false, /* No low pass filter on neg pad. */ \
625  false, /* No nextout output enabled. */ \
626  true, /* Neg pad enabled, used as signal input. */ \
627  true, /* Pos pad enabled, used as signal ground. */ \
628  false, /* No shorting of inputs. */ \
629  false, /* Rail-to-rail input enabled. */ \
630  true, /* Use factory calibrated opamp offset. */ \
631  0 /* Opamp offset value (not used). */ \
632 }
633 
635 #define OPA_INIT_INVERTING_OPA2 \
636 { \
637  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
638  opaPosSelPosPad, /* Pos input from pad. */ \
639  opaOutModeMain, /* Main output enabled. */ \
640  opaResSelR2eqR1, /* R2 = R1 */ \
641  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
642  DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
643  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
644  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
645  false, /* No low pass filter on pos pad. */ \
646  false, /* No low pass filter on neg pad. */ \
647  false, /* No nextout output enabled. */ \
648  true, /* Neg pad enabled, used as signal input. */ \
649  true, /* Pos pad enabled, used as signal ground. */ \
650  false, /* No shorting of inputs. */ \
651  false, /* Rail-to-rail input enabled. */ \
652  true, /* Use factory calibrated opamp offset. */ \
653  0 /* Opamp offset value (not used). */ \
654 }
655 
657 #define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \
658 { \
659  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
660  opaPosSelPosPad, /* Pos input from pad. */ \
661  opaOutModeAll, /* Both main and alternate outputs. */ \
662  opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
663  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
664  0, /* No alternate outputs enabled. */ \
665  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
666  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
667  false, /* No low pass filter on pos pad. */ \
668  false, /* No low pass filter on neg pad. */ \
669  true, /* Pass output to next stage (OPA1). */ \
670  true, /* Neg pad enabled, used as signal ground. */ \
671  true, /* Pos pad enabled, used as signal input. */ \
672  false, /* No shorting of inputs. */ \
673  false, /* Rail-to-rail input enabled. */ \
674  true, /* Use factory calibrated opamp offset. */ \
675  0 /* Opamp offset value (not used). */ \
676 }
677 
679 #define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \
680 { \
681  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
682  opaPosSelOpaIn, /* Pos input from OPA0 output. */ \
683  opaOutModeAll, /* Both main and alternate outputs. */ \
684  opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
685  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
686  0, /* No alternate outputs enabled. */ \
687  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
688  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
689  false, /* No low pass filter on pos pad. */ \
690  false, /* No low pass filter on neg pad. */ \
691  true, /* Pass output to next stage (OPA2). */ \
692  true, /* Neg pad enabled, used as signal ground. */ \
693  false, /* Pos pad disabled. */ \
694  false, /* No shorting of inputs. */ \
695  false, /* Rail-to-rail input enabled. */ \
696  true, /* Use factory calibrated opamp offset. */ \
697  0 /* Opamp offset value (not used). */ \
698 }
699 
701 #define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \
702 { \
703  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
704  opaPosSelOpaIn, /* Pos input from OPA1 output. */ \
705  opaOutModeMain, /* Main output enabled. */ \
706  opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
707  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
708  DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
709  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
710  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
711  false, /* No low pass filter on pos pad. */ \
712  false, /* No low pass filter on neg pad. */ \
713  false, /* No nextout output enabled. */ \
714  true, /* Neg pad enabled, used as signal ground. */ \
715  false, /* Pos pad disabled. */ \
716  false, /* No shorting of inputs. */ \
717  false, /* Rail-to-rail input enabled. */ \
718  true, /* Use factory calibrated opamp offset. */ \
719  0 /* Opamp offset value (not used). */ \
720 }
721 
723 #define OPA_INIT_CASCADED_INVERTING_OPA0 \
724 { \
725  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
726  opaPosSelPosPad, /* Pos input from pad. */ \
727  opaOutModeAll, /* Both main and alternate outputs. */ \
728  opaResSelR2eqR1, /* R2 = R1 */ \
729  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
730  0, /* No alternate outputs enabled. */ \
731  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
732  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
733  false, /* No low pass filter on pos pad. */ \
734  false, /* No low pass filter on neg pad. */ \
735  true, /* Pass output to next stage (OPA1). */ \
736  true, /* Neg pad enabled, used as signal input. */ \
737  true, /* Pos pad enabled, used as signal ground. */ \
738  false, /* No shorting of inputs. */ \
739  false, /* Rail-to-rail input enabled. */ \
740  true, /* Use factory calibrated opamp offset. */ \
741  0 /* Opamp offset value (not used). */ \
742 }
743 
745 #define OPA_INIT_CASCADED_INVERTING_OPA1 \
746 { \
747  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
748  opaPosSelPosPad, /* Pos input from pad. */ \
749  opaOutModeAll, /* Both main and alternate outputs. */ \
750  opaResSelR2eqR1, /* R2 = R1 */ \
751  opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
752  0, /* No alternate outputs enabled. */ \
753  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
754  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
755  false, /* No low pass filter on pos pad. */ \
756  false, /* No low pass filter on neg pad. */ \
757  true, /* Pass output to next stage (OPA2). */ \
758  false, /* Neg pad disabled. */ \
759  true, /* Pos pad enabled, used as signal ground. */ \
760  false, /* No shorting of inputs. */ \
761  false, /* Rail-to-rail input enabled. */ \
762  true, /* Use factory calibrated opamp offset. */ \
763  0 /* Opamp offset value (not used). */ \
764 }
765 
767 #define OPA_INIT_CASCADED_INVERTING_OPA2 \
768 { \
769  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
770  opaPosSelPosPad, /* Pos input from pad. */ \
771  opaOutModeMain, /* Main output enabled. */ \
772  opaResSelR2eqR1, /* R2 = R1 */ \
773  opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
774  DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \
775  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
776  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
777  false, /* No low pass filter on pos pad. */ \
778  false, /* No low pass filter on neg pad. */ \
779  false, /* No nextout output enabled. */ \
780  false, /* Neg pad disabled. */ \
781  true, /* Pos pad enabled, used as signal ground. */ \
782  false, /* No shorting of inputs. */ \
783  false, /* Rail-to-rail input enabled. */ \
784  true, /* Use factory calibrated opamp offset. */ \
785  0 /* Opamp offset value (not used). */ \
786 }
787 
789 #define OPA_INIT_DIFF_DRIVER_OPA0 \
790 { \
791  opaNegSelUnityGain, /* Unity gain. */ \
792  opaPosSelPosPad, /* Pos input from pad. */ \
793  opaOutModeAll, /* Both main and alternate outputs. */ \
794  opaResSelDefault, /* Resistor ladder is not used. */ \
795  opaResInMuxDisable, /* Resistor ladder disabled. */ \
796  0, /* No alternate outputs enabled. */ \
797  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
798  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
799  false, /* No low pass filter on pos pad. */ \
800  false, /* No low pass filter on neg pad. */ \
801  true, /* Pass output to next stage (OPA1). */ \
802  false, /* Neg pad disabled. */ \
803  true, /* Pos pad enabled, used as signal input. */ \
804  false, /* No shorting of inputs. */ \
805  false, /* Rail-to-rail input enabled. */ \
806  true, /* Use factory calibrated opamp offset. */ \
807  0 /* Opamp offset value (not used). */ \
808 }
809 
811 #define OPA_INIT_DIFF_DRIVER_OPA1 \
812 { \
813  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
814  opaPosSelPosPad, /* Pos input from pad. */ \
815  opaOutModeMain, /* Main output enabled. */ \
816  opaResSelR2eqR1, /* R2 = R1 */ \
817  opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
818  0, /* No alternate outputs enabled. */ \
819  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
820  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
821  false, /* No low pass filter on pos pad. */ \
822  false, /* No low pass filter on neg pad. */ \
823  false, /* No nextout output enabled. */ \
824  false, /* Neg pad disabled. */ \
825  true, /* Pos pad enabled, used as signal ground. */ \
826  false, /* No shorting of inputs. */ \
827  false, /* Rail-to-rail input enabled. */ \
828  true, /* Use factory calibrated opamp offset. */ \
829  0 /* Opamp offset value (not used). */ \
830 }
831 
833 #define OPA_INIT_DIFF_RECEIVER_OPA0 \
834 { \
835  opaNegSelUnityGain, /* Unity gain. */ \
836  opaPosSelPosPad, /* Pos input from pad. */ \
837  opaOutModeAll, /* Both main and alternate outputs. */ \
838  opaResSelR2eqR1, /* R2 = R1 */ \
839  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
840  0, /* No alternate outputs enabled. */ \
841  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
842  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
843  false, /* No low pass filter on pos pad. */ \
844  false, /* No low pass filter on neg pad. */ \
845  true, /* Pass output to next stage (OPA2). */ \
846  true, /* Neg pad enabled, used as signal ground. */ \
847  true, /* Pos pad enabled, used as signal input. */ \
848  false, /* No shorting of inputs. */ \
849  false, /* Rail-to-rail input enabled. */ \
850  true, /* Use factory calibrated opamp offset. */ \
851  0 /* Opamp offset value (not used). */ \
852 }
853 
855 #define OPA_INIT_DIFF_RECEIVER_OPA1 \
856 { \
857  opaNegSelUnityGain, /* Unity gain. */ \
858  opaPosSelPosPad, /* Pos input from pad. */ \
859  opaOutModeAll, /* Both main and alternate outputs. */ \
860  opaResSelDefault, /* Resistor ladder is not used. */ \
861  opaResInMuxDisable, /* Disable resistor ladder. */ \
862  0, /* No alternate outputs enabled. */ \
863  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
864  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
865  false, /* No low pass filter on pos pad. */ \
866  false, /* No low pass filter on neg pad. */ \
867  true, /* Pass output to next stage (OPA2). */ \
868  false, /* Neg pad disabled. */ \
869  true, /* Pos pad enabled, used as signal input. */ \
870  false, /* No shorting of inputs. */ \
871  false, /* Rail-to-rail input enabled. */ \
872  true, /* Use factory calibrated opamp offset. */ \
873  0 /* Opamp offset value (not used). */ \
874 }
875 
877 #define OPA_INIT_DIFF_RECEIVER_OPA2 \
878 { \
879  opaNegSelResTap, /* Input from resistor ladder tap. */ \
880  opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \
881  opaOutModeMain, /* Main output enabled. */ \
882  opaResSelR2eqR1, /* R2 = R1 */ \
883  opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
884  DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \
885  _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \
886  _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \
887  false, /* No low pass filter on pos pad. */ \
888  false, /* No low pass filter on neg pad. */ \
889  false, /* No nextout output enabled. */ \
890  false, /* Neg pad disabled. */ \
891  false, /* Pos pad disabled. */ \
892  false, /* No shorting of inputs. */ \
893  false, /* Rail-to-rail input enabled. */ \
894  true, /* Use factory calibrated opamp offset. */ \
895  0 /* Opamp offset value (not used). */ \
896 }
897 
898 #elif defined(_SILICON_LABS_32B_SERIES_1)
899 
900 #define OPA_INIT_UNITY_GAIN \
901 { \
902  opaNegSelUnityGain, /* Unity gain. */ \
903  opaPosSelPosPad, /* Pos input from pad. */ \
904  opaOutModeMain, /* Main output enabled. */ \
905  opaResSelDefault, /* Resistor ladder is not used. */ \
906  opaResInMuxDisable, /* Resistor ladder disabled. */ \
907  0, /* No alternate outputs enabled. */ \
908  opaDrvStrDefault, /* Default opamp operation mode. */ \
909  false, /* Disable 3x gain setting. */ \
910  false, /* Use full output drive strength. */ \
911  false, /* Disable unity-gain bandwidth scaling. */ \
912  false, /* Opamp triggered by OPAxEN. */ \
913  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
914  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
915  opaPrsOutDefault, /* Default PRS output setting. */ \
916  false, /* Bus mastering enabled on APORTX. */ \
917  false, /* Bus mastering enabled on APORTY. */ \
918  3, /* 3us settle time with default DrvStr. */ \
919  0, /* No startup delay. */ \
920  false, /* Rail-to-rail input enabled. */ \
921  true, /* Use calibrated inverting offset. */ \
922  0, /* Opamp offset value (not used). */ \
923  true, /* Use calibrated non-inverting offset. */ \
924  0 /* Opamp offset value (not used). */ \
925 }
926 
928 #define OPA_INIT_NON_INVERTING \
929 { \
930  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
931  opaPosSelPosPad, /* Pos input from pad. */ \
932  opaOutModeMain, /* Main output enabled. */ \
933  opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
934  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
935  0, /* No alternate outputs enabled. */ \
936  opaDrvStrDefault, /* Default opamp operation mode. */ \
937  false, /* Disable 3x gain setting. */ \
938  false, /* Use full output drive strength. */ \
939  false, /* Disable unity-gain bandwidth scaling. */ \
940  false, /* Opamp triggered by OPAxEN. */ \
941  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
942  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
943  opaPrsOutDefault, /* Default PRS output setting. */ \
944  false, /* Bus mastering enabled on APORTX. */ \
945  false, /* Bus mastering enabled on APORTY. */ \
946  3, /* 3us settle time with default DrvStr. */ \
947  0, /* No startup delay. */ \
948  false, /* Rail-to-rail input enabled. */ \
949  true, /* Use calibrated inverting offset. */ \
950  0, /* Opamp offset value (not used). */ \
951  true, /* Use calibrated non-inverting offset. */ \
952  0 /* Opamp offset value (not used). */ \
953 }
954 
956 #define OPA_INIT_INVERTING \
957 { \
958  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
959  opaPosSelPosPad, /* Pos input from pad. */ \
960  opaOutModeMain, /* Main output enabled. */ \
961  opaResSelR2eqR1, /* R2 = R1 */ \
962  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
963  0, /* No alternate outputs enabled. */ \
964  opaDrvStrDefault, /* Default opamp operation mode. */ \
965  false, /* Disable 3x gain setting. */ \
966  false, /* Use full output drive strength. */ \
967  false, /* Disable unity-gain bandwidth scaling. */ \
968  false, /* Opamp triggered by OPAxEN. */ \
969  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
970  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
971  opaPrsOutDefault, /* Default PRS output setting. */ \
972  false, /* Bus mastering enabled on APORTX. */ \
973  false, /* Bus mastering enabled on APORTY. */ \
974  3, /* 3us settle time with default DrvStr. */ \
975  0, /* No startup delay. */ \
976  false, /* Rail-to-rail input enabled. */ \
977  true, /* Use calibrated inverting offset. */ \
978  0, /* Opamp offset value (not used). */ \
979  true, /* Use calibrated non-inverting offset. */ \
980  0 /* Opamp offset value (not used). */ \
981 }
982 
984 #define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \
985 { \
986  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
987  opaPosSelPosPad, /* Pos input from pad. */ \
988  opaOutModeMain, /* Main output enabled. */ \
989  opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
990  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
991  0, /* No alternate outputs enabled. */ \
992  opaDrvStrDefault, /* Default opamp operation mode. */ \
993  false, /* Disable 3x gain setting. */ \
994  false, /* Use full output drive strength. */ \
995  false, /* Disable unity-gain bandwidth scaling. */ \
996  false, /* Opamp triggered by OPAxEN. */ \
997  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
998  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
999  opaPrsOutDefault, /* Default PRS output setting. */ \
1000  false, /* Bus mastering enabled on APORTX. */ \
1001  false, /* Bus mastering enabled on APORTY. */ \
1002  3, /* 3us settle time with default DrvStr. */ \
1003  0, /* No startup delay. */ \
1004  false, /* Rail-to-rail input enabled. */ \
1005  true, /* Use calibrated inverting offset. */ \
1006  0, /* Opamp offset value (not used). */ \
1007  true, /* Use calibrated non-inverting offset. */ \
1008  0 /* Opamp offset value (not used). */ \
1009 }
1010 
1012 #define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \
1013 { \
1014  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
1015  opaPosSelOpaIn, /* Pos input from OPA0 output. */ \
1016  opaOutModeMain, /* Main output enabled. */ \
1017  opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
1018  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
1019  0, /* No alternate outputs enabled. */ \
1020  opaDrvStrDefault, /* Default opamp operation mode. */ \
1021  false, /* Disable 3x gain setting. */ \
1022  false, /* Use full output drive strength. */ \
1023  false, /* Disable unity-gain bandwidth scaling. */ \
1024  false, /* Opamp triggered by OPAxEN. */ \
1025  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1026  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1027  opaPrsOutDefault, /* Default PRS output setting. */ \
1028  false, /* Bus mastering enabled on APORTX. */ \
1029  false, /* Bus mastering enabled on APORTY. */ \
1030  3, /* 3us settle time with default DrvStr. */ \
1031  0, /* No startup delay. */ \
1032  false, /* Rail-to-rail input enabled. */ \
1033  true, /* Use calibrated inverting offset. */ \
1034  0, /* Opamp offset value (not used). */ \
1035  true, /* Use calibrated non-inverting offset. */ \
1036  0 /* Opamp offset value (not used). */ \
1037 }
1038 
1040 #define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \
1041 { \
1042  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
1043  opaPosSelOpaIn, /* Pos input from OPA1 output. */ \
1044  opaOutModeMain, /* Main output enabled. */ \
1045  opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \
1046  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
1047  0, /* No alternate outputs enabled. */ \
1048  opaDrvStrDefault, /* Default opamp operation mode. */ \
1049  false, /* Disable 3x gain setting. */ \
1050  false, /* Use full output drive strength. */ \
1051  false, /* Disable unity-gain bandwidth scaling. */ \
1052  false, /* Opamp triggered by OPAxEN. */ \
1053  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1054  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1055  opaPrsOutDefault, /* Default PRS output setting. */ \
1056  false, /* Bus mastering enabled on APORTX. */ \
1057  false, /* Bus mastering enabled on APORTY. */ \
1058  3, /* 3us settle time with default DrvStr. */ \
1059  0, /* No startup delay. */ \
1060  false, /* Rail-to-rail input enabled. */ \
1061  true, /* Use calibrated inverting offset. */ \
1062  0, /* Opamp offset value (not used). */ \
1063  true, /* Use calibrated non-inverting offset. */ \
1064  0 /* Opamp offset value (not used). */ \
1065 }
1066 
1068 #define OPA_INIT_CASCADED_INVERTING_OPA0 \
1069 { \
1070  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
1071  opaPosSelPosPad, /* Pos input from pad. */ \
1072  opaOutModeMain, /* Main output enabled. */ \
1073  opaResSelR2eqR1, /* R2 = R1 */ \
1074  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
1075  0, /* No alternate outputs enabled. */ \
1076  opaDrvStrDefault, /* Default opamp operation mode. */ \
1077  false, /* Disable 3x gain setting. */ \
1078  false, /* Use full output drive strength. */ \
1079  false, /* Disable unity-gain bandwidth scaling. */ \
1080  false, /* Opamp triggered by OPAxEN. */ \
1081  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1082  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1083  opaPrsOutDefault, /* Default PRS output setting. */ \
1084  false, /* Bus mastering enabled on APORTX. */ \
1085  false, /* Bus mastering enabled on APORTY. */ \
1086  3, /* 3us settle time with default DrvStr. */ \
1087  0, /* No startup delay. */ \
1088  false, /* Rail-to-rail input enabled. */ \
1089  true, /* Use calibrated inverting offset. */ \
1090  0, /* Opamp offset value (not used). */ \
1091  true, /* Use calibrated non-inverting offset. */ \
1092  0 /* Opamp offset value (not used). */ \
1093 }
1094 
1096 #define OPA_INIT_CASCADED_INVERTING_OPA1 \
1097 { \
1098  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
1099  opaPosSelPosPad, /* Pos input from pad. */ \
1100  opaOutModeMain, /* Main output enabled. */ \
1101  opaResSelR2eqR1, /* R2 = R1 */ \
1102  opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
1103  0, /* No alternate outputs enabled. */ \
1104  opaDrvStrDefault, /* Default opamp operation mode. */ \
1105  false, /* Disable 3x gain setting. */ \
1106  false, /* Use full output drive strength. */ \
1107  false, /* Disable unity-gain bandwidth scaling. */ \
1108  false, /* Opamp triggered by OPAxEN. */ \
1109  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1110  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1111  opaPrsOutDefault, /* Default PRS output setting. */ \
1112  false, /* Bus mastering enabled on APORTX. */ \
1113  false, /* Bus mastering enabled on APORTY. */ \
1114  3, /* 3us settle time with default DrvStr. */ \
1115  0, /* No startup delay. */ \
1116  false, /* Rail-to-rail input enabled. */ \
1117  true, /* Use calibrated inverting offset. */ \
1118  0, /* Opamp offset value (not used). */ \
1119  true, /* Use calibrated non-inverting offset. */ \
1120  0 /* Opamp offset value (not used). */ \
1121 }
1122 
1124 #define OPA_INIT_CASCADED_INVERTING_OPA2 \
1125 { \
1126  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
1127  opaPosSelPosPad, /* Pos input from pad. */ \
1128  opaOutModeMain, /* Main output enabled. */ \
1129  opaResSelR2eqR1, /* R2 = R1 */ \
1130  opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
1131  0, /* No alternate outputs enabled. */ \
1132  opaDrvStrDefault, /* Default opamp operation mode. */ \
1133  false, /* Disable 3x gain setting. */ \
1134  false, /* Use full output drive strength. */ \
1135  false, /* Disable unity-gain bandwidth scaling. */ \
1136  false, /* Opamp triggered by OPAxEN. */ \
1137  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1138  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1139  opaPrsOutDefault, /* Default PRS output setting. */ \
1140  false, /* Bus mastering enabled on APORTX. */ \
1141  false, /* Bus mastering enabled on APORTY. */ \
1142  3, /* 3us settle time with default DrvStr. */ \
1143  0, /* No startup delay. */ \
1144  false, /* Rail-to-rail input enabled. */ \
1145  true, /* Use calibrated inverting offset. */ \
1146  0, /* Opamp offset value (not used). */ \
1147  true, /* Use calibrated non-inverting offset. */ \
1148  0 /* Opamp offset value (not used). */ \
1149 }
1150 
1152 #define OPA_INIT_DIFF_DRIVER_OPA0 \
1153 { \
1154  opaNegSelUnityGain, /* Unity gain. */ \
1155  opaPosSelPosPad, /* Pos input from pad. */ \
1156  opaOutModeMain, /* Main output enabled. */ \
1157  opaResSelDefault, /* Resistor ladder is not used. */ \
1158  opaResInMuxDisable, /* Resistor ladder disabled. */ \
1159  0, /* No alternate outputs enabled. */ \
1160  opaDrvStrDefault, /* Default opamp operation mode. */ \
1161  false, /* Disable 3x gain setting. */ \
1162  false, /* Use full output drive strength. */ \
1163  false, /* Disable unity-gain bandwidth scaling. */ \
1164  false, /* Opamp triggered by OPAxEN. */ \
1165  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1166  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1167  opaPrsOutDefault, /* Default PRS output setting. */ \
1168  false, /* Bus mastering enabled on APORTX. */ \
1169  false, /* Bus mastering enabled on APORTY. */ \
1170  3, /* 3us settle time with default DrvStr. */ \
1171  0, /* No startup delay. */ \
1172  false, /* Rail-to-rail input enabled. */ \
1173  true, /* Use calibrated inverting offset. */ \
1174  0, /* Opamp offset value (not used). */ \
1175  true, /* Use calibrated non-inverting offset. */ \
1176  0 /* Opamp offset value (not used). */ \
1177 }
1178 
1180 #define OPA_INIT_DIFF_DRIVER_OPA1 \
1181 { \
1182  opaNegSelResTap, /* Neg input from resistor ladder tap. */ \
1183  opaPosSelPosPad, /* Pos input from pad. */ \
1184  opaOutModeMain, /* Main output enabled. */ \
1185  opaResSelR2eqR1, /* R2 = R1 */ \
1186  opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \
1187  0, /* No alternate outputs enabled. */ \
1188  opaDrvStrDefault, /* Default opamp operation mode. */ \
1189  false, /* Disable 3x gain setting. */ \
1190  false, /* Use full output drive strength. */ \
1191  false, /* Disable unity-gain bandwidth scaling. */ \
1192  false, /* Opamp triggered by OPAxEN. */ \
1193  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1194  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1195  opaPrsOutDefault, /* Default PRS output setting. */ \
1196  false, /* Bus mastering enabled on APORTX. */ \
1197  false, /* Bus mastering enabled on APORTY. */ \
1198  3, /* 3us settle time with default DrvStr. */ \
1199  0, /* No startup delay. */ \
1200  false, /* Rail-to-rail input enabled. */ \
1201  true, /* Use calibrated inverting offset. */ \
1202  0, /* Opamp offset value (not used). */ \
1203  true, /* Use calibrated non-inverting offset. */ \
1204  0 /* Opamp offset value (not used). */ \
1205 }
1206 
1208 #define OPA_INIT_DIFF_RECEIVER_OPA0 \
1209 { \
1210  opaNegSelUnityGain, /* Unity gain. */ \
1211  opaPosSelPosPad, /* Pos input from pad. */ \
1212  opaOutModeMain, /* Main output enabled. */ \
1213  opaResSelR2eqR1, /* R2 = R1 */ \
1214  opaResInMuxNegPad, /* Resistor ladder input from neg pad. */ \
1215  0, /* No alternate outputs enabled. */ \
1216  opaDrvStrDefault, /* Default opamp operation mode. */ \
1217  false, /* Disable 3x gain setting. */ \
1218  false, /* Use full output drive strength. */ \
1219  false, /* Disable unity-gain bandwidth scaling. */ \
1220  false, /* Opamp triggered by OPAxEN. */ \
1221  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1222  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1223  opaPrsOutDefault, /* Default PRS output setting. */ \
1224  false, /* Bus mastering enabled on APORTX. */ \
1225  false, /* Bus mastering enabled on APORTY. */ \
1226  3, /* 3us settle time with default DrvStr. */ \
1227  0, /* No startup delay. */ \
1228  false, /* Rail-to-rail input enabled. */ \
1229  true, /* Use calibrated inverting offset. */ \
1230  0, /* Opamp offset value (not used). */ \
1231  true, /* Use calibrated non-inverting offset. */ \
1232  0 /* Opamp offset value (not used). */ \
1233 }
1234 
1236 #define OPA_INIT_DIFF_RECEIVER_OPA1 \
1237 { \
1238  opaNegSelUnityGain, /* Unity gain. */ \
1239  opaPosSelPosPad, /* Pos input from pad. */ \
1240  opaOutModeMain, /* Main output enabled. */ \
1241  opaResSelDefault, /* Resistor ladder is not used. */ \
1242  opaResInMuxDisable, /* Disable resistor ladder. */ \
1243  0, /* No alternate outputs enabled. */ \
1244  opaDrvStrDefault, /* Default opamp operation mode. */ \
1245  false, /* Disable 3x gain setting. */ \
1246  false, /* Use full output drive strength. */ \
1247  false, /* Disable unity-gain bandwidth scaling. */ \
1248  false, /* Opamp triggered by OPAxEN. */ \
1249  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1250  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1251  opaPrsOutDefault, /* Default PRS output setting. */ \
1252  false, /* Bus mastering enabled on APORTX. */ \
1253  false, /* Bus mastering enabled on APORTY. */ \
1254  3, /* 3us settle time with default DrvStr. */ \
1255  0, /* No startup delay. */ \
1256  false, /* Rail-to-rail input enabled. */ \
1257  true, /* Use calibrated inverting offset. */ \
1258  0, /* Opamp offset value (not used). */ \
1259  true, /* Use calibrated non-inverting offset. */ \
1260  0 /* Opamp offset value (not used). */ \
1261 }
1262 
1264 #define OPA_INIT_DIFF_RECEIVER_OPA2 \
1265 { \
1266  opaNegSelResTap, /* Input from resistor ladder tap. */ \
1267  opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \
1268  opaOutModeMain, /* Main output enabled. */ \
1269  opaResSelR2eqR1, /* R2 = R1 */ \
1270  opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \
1271  0, /* No alternate outputs enabled. */ \
1272  opaDrvStrDefault, /* Default opamp operation mode. */ \
1273  false, /* Disable 3x gain setting. */ \
1274  false, /* Use full output drive strength. */ \
1275  false, /* Disable unity-gain bandwidth scaling. */ \
1276  false, /* Opamp triggered by OPAxEN. */ \
1277  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1278  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1279  opaPrsOutDefault, /* Default PRS output setting. */ \
1280  false, /* Bus mastering enabled on APORTX. */ \
1281  false, /* Bus mastering enabled on APORTY. */ \
1282  3, /* 3us settle time with default DrvStr. */ \
1283  0, /* No startup delay. */ \
1284  false, /* Rail-to-rail input enabled. */ \
1285  true, /* Use calibrated inverting offset. */ \
1286  0, /* Opamp offset value (not used). */ \
1287  true, /* Use calibrated non-inverting offset. */ \
1288  0 /* Opamp offset value (not used). */ \
1289 }
1290 
1292 #define OPA_INIT_INSTR_AMP_OPA0 \
1293 { \
1294  opaNegSelResTap, /* Input from resistor ladder tap. */ \
1295  opaPosSelPosPad, /* Pos input from pad. */ \
1296  opaOutModeMain, /* Main output enabled. */ \
1297  opaResSelR2eqR1, /* R2 = R1 */ \
1298  opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \
1299  0, /* No alternate outputs enabled. */ \
1300  opaDrvStrDefault, /* Default opamp operation mode. */ \
1301  false, /* Disable 3x gain setting. */ \
1302  false, /* Use full output drive strength. */ \
1303  false, /* Disable unity-gain bandwidth scaling. */ \
1304  false, /* Opamp triggered by OPAxEN. */ \
1305  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1306  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1307  opaPrsOutDefault, /* Default PRS output setting. */ \
1308  false, /* Bus mastering enabled on APORTX. */ \
1309  false, /* Bus mastering enabled on APORTY. */ \
1310  3, /* 3us settle time with default DrvStr. */ \
1311  0, /* No startup delay. */ \
1312  false, /* Rail-to-rail input enabled. */ \
1313  true, /* Use calibrated inverting offset. */ \
1314  0, /* Opamp offset value (not used). */ \
1315  true, /* Use calibrated non-inverting offset. */ \
1316  0 /* Opamp offset value (not used). */ \
1317 }
1318 
1320 #define OPA_INIT_INSTR_AMP_OPA1 \
1321 { \
1322  opaNegSelNegPad, /* Neg input from pad. */ \
1323  opaPosSelResTap, /* Input from resistor ladder tap. */ \
1324  opaOutModeMain, /* Main output enabled. */ \
1325  opaResSelR2eqR1, /* R2 = R1 */ \
1326  opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \
1327  0, /* No alternate outputs enabled. */ \
1328  opaDrvStrDefault, /* Default opamp operation mode. */ \
1329  false, /* Disable 3x gain setting. */ \
1330  false, /* Use full output drive strength. */ \
1331  false, /* Disable unity-gain bandwidth scaling. */ \
1332  false, /* Opamp triggered by OPAxEN. */ \
1333  opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \
1334  opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \
1335  opaPrsOutDefault, /* Default PRS output setting. */ \
1336  false, /* Bus mastering enabled on APORTX. */ \
1337  false, /* Bus mastering enabled on APORTY. */ \
1338  3, /* 3us settle time with default DrvStr. */ \
1339  0, /* No startup delay. */ \
1340  false, /* Rail-to-rail input enabled. */ \
1341  true, /* Use calibrated inverting offset. */ \
1342  0, /* Opamp offset value (not used). */ \
1343  true, /* Use calibrated non-inverting offset. */ \
1344  0 /* Opamp offset value (not used). */ \
1345 }
1346 
1347 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
1348 
1349 /*******************************************************************************
1350  ***************************** PROTOTYPES **********************************
1351  ******************************************************************************/
1352 
1353 #if defined(_SILICON_LABS_32B_SERIES_0)
1354 void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa);
1355 void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init);
1356 #elif defined(_SILICON_LABS_32B_SERIES_1)
1357 void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa);
1358 void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init);
1359 #endif /* defined(_SILICON_LABS_32B_SERIES_0) */
1360 
1364 #ifdef __cplusplus
1365 }
1366 #endif
1367 
1368 #endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1))
1369  || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */
1370 #endif /* EM_OPAMP_H */
em_device.h
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
em_dac.h
Digital to Analog Converter (DAC) peripheral API.
em_vdac.h
Digital to Analog Converter (VDAC) peripheral API.