EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
em_dac.h
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1 /***************************************************************************/
33 #ifndef EM_DAC_H
34 #define EM_DAC_H
35 
36 #include "em_device.h"
37 
38 #if defined(DAC_COUNT) && (DAC_COUNT > 0)
39 
40 #include "em_assert.h"
41 #include <stdbool.h>
42 
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46 
47 
48 /***************************************************************************/
53 /***************************************************************************/
61 #define DAC_REF_VALID(ref) ((ref) == DAC0)
62 
65 /*******************************************************************************
66  ******************************** ENUMS ************************************
67  ******************************************************************************/
68 
70 typedef enum
71 {
72  dacConvModeContinuous = _DAC_CTRL_CONVMODE_CONTINUOUS,
73  dacConvModeSampleHold = _DAC_CTRL_CONVMODE_SAMPLEHOLD,
74  dacConvModeSampleOff = _DAC_CTRL_CONVMODE_SAMPLEOFF
75 } DAC_ConvMode_TypeDef;
76 
78 typedef enum
79 {
80  dacOutputDisable = _DAC_CTRL_OUTMODE_DISABLE,
81  dacOutputPin = _DAC_CTRL_OUTMODE_PIN,
82  dacOutputADC = _DAC_CTRL_OUTMODE_ADC,
83  dacOutputPinADC = _DAC_CTRL_OUTMODE_PINADC
84 } DAC_Output_TypeDef;
85 
86 
88 typedef enum
89 {
90  dacPRSSELCh0 = _DAC_CH0CTRL_PRSSEL_PRSCH0,
91  dacPRSSELCh1 = _DAC_CH0CTRL_PRSSEL_PRSCH1,
92  dacPRSSELCh2 = _DAC_CH0CTRL_PRSSEL_PRSCH2,
93  dacPRSSELCh3 = _DAC_CH0CTRL_PRSSEL_PRSCH3,
94 #if defined( _DAC_CH0CTRL_PRSSEL_PRSCH4 )
95  dacPRSSELCh4 = _DAC_CH0CTRL_PRSSEL_PRSCH4,
96 #endif
97 #if defined( _DAC_CH0CTRL_PRSSEL_PRSCH5 )
98  dacPRSSELCh5 = _DAC_CH0CTRL_PRSSEL_PRSCH5,
99 #endif
100 #if defined( _DAC_CH0CTRL_PRSSEL_PRSCH6 )
101  dacPRSSELCh6 = _DAC_CH0CTRL_PRSSEL_PRSCH6,
102 #endif
103 #if defined( _DAC_CH0CTRL_PRSSEL_PRSCH7 )
104  dacPRSSELCh7 = _DAC_CH0CTRL_PRSSEL_PRSCH7,
105 #endif
106 #if defined( _DAC_CH0CTRL_PRSSEL_PRSCH8 )
107  dacPRSSELCh8 = _DAC_CH0CTRL_PRSSEL_PRSCH8,
108 #endif
109 #if defined( _DAC_CH0CTRL_PRSSEL_PRSCH9 )
110  dacPRSSELCh9 = _DAC_CH0CTRL_PRSSEL_PRSCH9,
111 #endif
112 #if defined( _DAC_CH0CTRL_PRSSEL_PRSCH10 )
113  dacPRSSELCh10 = _DAC_CH0CTRL_PRSSEL_PRSCH10,
114 #endif
115 #if defined( _DAC_CH0CTRL_PRSSEL_PRSCH11 )
116  dacPRSSELCh11 = _DAC_CH0CTRL_PRSSEL_PRSCH11,
117 #endif
118 } DAC_PRSSEL_TypeDef;
119 
120 
122 typedef enum
123 {
124  dacRef1V25 = _DAC_CTRL_REFSEL_1V25,
125  dacRef2V5 = _DAC_CTRL_REFSEL_2V5,
126  dacRefVDD = _DAC_CTRL_REFSEL_VDD
127 } DAC_Ref_TypeDef;
128 
129 
131 typedef enum
132 {
133  dacRefresh8 = _DAC_CTRL_REFRSEL_8CYCLES,
134  dacRefresh16 = _DAC_CTRL_REFRSEL_16CYCLES,
135  dacRefresh32 = _DAC_CTRL_REFRSEL_32CYCLES,
136  dacRefresh64 = _DAC_CTRL_REFRSEL_64CYCLES
137 } DAC_Refresh_TypeDef;
138 
139 
140 /*******************************************************************************
141  ******************************* STRUCTS ***********************************
142  ******************************************************************************/
143 
145 typedef struct
146 {
148  DAC_Refresh_TypeDef refresh;
149 
151  DAC_Ref_TypeDef reference;
152 
154  DAC_Output_TypeDef outMode;
155 
157  DAC_ConvMode_TypeDef convMode;
158 
163  uint8_t prescale;
164 
166  bool lpEnable;
167 
169  bool ch0ResetPre;
170 
172  bool outEnablePRS;
173 
175  bool sineEnable;
176 
178  bool diff;
179 } DAC_Init_TypeDef;
180 
182 #define DAC_INIT_DEFAULT \
183 { \
184  dacRefresh8, /* Refresh every 8 prescaled cycles. */ \
185  dacRef1V25, /* 1.25V internal reference. */ \
186  dacOutputPin, /* Output to pin only. */ \
187  dacConvModeContinuous, /* Continuous mode. */ \
188  0, /* No prescaling. */ \
189  false, /* Do not enable low pass filter. */ \
190  false, /* Do not reset prescaler on ch0 start. */ \
191  false, /* DAC output enable always on. */ \
192  false, /* Disable sine mode. */ \
193  false /* Single ended mode. */ \
194 }
195 
196 
198 typedef struct
199 {
201  bool enable;
202 
207  bool prsEnable;
208 
213  bool refreshEnable;
214 
219  DAC_PRSSEL_TypeDef prsSel;
220 } DAC_InitChannel_TypeDef;
221 
223 #define DAC_INITCHANNEL_DEFAULT \
224 { \
225  false, /* Leave channel disabled when init done. */ \
226  false, /* Disable PRS triggering. */ \
227  false, /* Channel not refreshed automatically. */ \
228  dacPRSSELCh0 /* Select PRS ch0 (if PRS triggering enabled). */ \
229 }
230 
231 
232 /*******************************************************************************
233  ***************************** PROTOTYPES **********************************
234  ******************************************************************************/
235 
236 void DAC_Enable(DAC_TypeDef *dac, unsigned int ch, bool enable);
237 void DAC_Init(DAC_TypeDef *dac, const DAC_Init_TypeDef *init);
238 void DAC_InitChannel(DAC_TypeDef *dac,
239  const DAC_InitChannel_TypeDef *init,
240  unsigned int ch);
241 void DAC_ChannelOutputSet(DAC_TypeDef *dac,
242  unsigned int channel,
243  uint32_t value);
244 
245 /***************************************************************************/
259 __STATIC_INLINE void DAC_Channel0OutputSet( DAC_TypeDef *dac,
260  uint32_t value )
261 {
262  EFM_ASSERT(value<=_DAC_CH0DATA_MASK);
263  dac->CH0DATA = value;
264 }
265 
266 
267 /***************************************************************************/
281 __STATIC_INLINE void DAC_Channel1OutputSet( DAC_TypeDef *dac,
282  uint32_t value )
283 {
284  EFM_ASSERT(value<=_DAC_CH1DATA_MASK);
285  dac->CH1DATA = value;
286 }
287 
288 
289 /***************************************************************************/
300 __STATIC_INLINE void DAC_IntClear(DAC_TypeDef *dac, uint32_t flags)
301 {
302  dac->IFC = flags;
303 }
304 
305 
306 /***************************************************************************/
317 __STATIC_INLINE void DAC_IntDisable(DAC_TypeDef *dac, uint32_t flags)
318 {
319  dac->IEN &= ~flags;
320 }
321 
322 
323 /***************************************************************************/
339 __STATIC_INLINE void DAC_IntEnable(DAC_TypeDef *dac, uint32_t flags)
340 {
341  dac->IEN |= flags;
342 }
343 
344 
345 /***************************************************************************/
359 __STATIC_INLINE uint32_t DAC_IntGet(DAC_TypeDef *dac)
360 {
361  return dac->IF;
362 }
363 
364 
365 /***************************************************************************/
384 __STATIC_INLINE uint32_t DAC_IntGetEnabled(DAC_TypeDef *dac)
385 {
386  uint32_t ien;
387 
388  /* Store DAC->IEN in temporary variable in order to define explicit order
389  * of volatile accesses. */
390  ien = dac->IEN;
391 
392  /* Bitwise AND of pending and enabled interrupts */
393  return dac->IF & ien;
394 }
395 
396 
397 /***************************************************************************/
408 __STATIC_INLINE void DAC_IntSet(DAC_TypeDef *dac, uint32_t flags)
409 {
410  dac->IFS = flags;
411 }
412 
413 uint8_t DAC_PrescaleCalc(uint32_t dacFreq, uint32_t hfperFreq);
414 void DAC_Reset(DAC_TypeDef *dac);
415 
419 #ifdef __cplusplus
420 }
421 #endif
422 
423 #endif /* defined(DAC_COUNT) && (DAC_COUNT > 0) */
424 #endif /* EM_DAC_H */
Emlib peripheral API "assert" implementation.
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.