EFR32 Mighty Gecko 1 Software Documentation  efr32mg1-doc-5.1.2
bmp_regs.h
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1 /***************************************************************************/
16 #ifndef __BMP_REGS_H_
17 #define __BMP_REGS_H_
18 
19 /***************************************************************************/
24 /***************************************************************************/
30 #define BMP_REG_ADDR_ID 0xD0
31 #define BMP_REG_ADDR_SOFTRESET 0xE0
32 #define BMP_REG_ADDR_CTRL_MEAS 0xF4
34 #define BMP_REG_ADDR_TEMP_XLSB 0xFC
35 #define BMP_REG_ADDR_TEMP_LSB 0xFB
36 #define BMP_REG_ADDR_TEMP_MSB 0xFA
37 #define BMP_REG_ADDR_PRESS_XLSB 0xF9
38 #define BMP_REG_ADDR_PRESS_LSB 0xF8
39 #define BMP_REG_ADDR_PRESS_MSB 0xF7
40 #define BMP_REG_ADDR_CONFIG 0xF5
41 #define BMP_REG_ADDR_CTRL_MEAS 0xF4
42 #define BMP_REG_ADDR_STATUS 0xF3
43 #define BMP_REG_ADDR_SOFTRESET 0xE0
44 #define BMP_REG_ADDR_ID 0xD0
46 #define BMP_REG16_ADDR_RESV 0xA0
47 #define BMP_REG16_ADDR_DIG_P9 0x9E
48 #define BMP_REG16_ADDR_DIG_P8 0x9C
49 #define BMP_REG16_ADDR_DIG_P7 0x9A
50 #define BMP_REG16_ADDR_DIG_P6 0x98
51 #define BMP_REG16_ADDR_DIG_P5 0x96
52 #define BMP_REG16_ADDR_DIG_P4 0x94
53 #define BMP_REG16_ADDR_DIG_P3 0x92
54 #define BMP_REG16_ADDR_DIG_P2 0x90
55 #define BMP_REG16_ADDR_DIG_P1 0x8E
56 #define BMP_REG16_ADDR_DIG_T3 0x8C
57 #define BMP_REG16_ADDR_DIG_T2 0x8A
58 #define BMP_REG16_ADDR_DIG_T1 0x88
64 #endif /* __BMP_REGS_H_ */