EFR32 Blue Gecko 1 Software Documentation  efr32bg1-doc-5.1.2
em_ebi.c
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1 /***************************************************************************/
33 #include "em_ebi.h"
34 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
35 #include "em_assert.h"
36 #include "em_bus.h"
37 
38 /***************************************************************************/
43 /***************************************************************************/
53 /***************************************************************************/
64 void EBI_Init(const EBI_Init_TypeDef *ebiInit)
65 {
66  uint32_t ctrl = EBI->CTRL;
67 
68 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
69  /* Enable Independent Timing for devices that supports it */
70  ctrl |= EBI_CTRL_ITS;
71 
72  /* Set polarity of address ready */
73  EBI_BankPolaritySet(ebiInit->banks, ebiLineARDY, ebiInit->ardyPolarity);
74  /* Set polarity of address latch enable */
75  EBI_BankPolaritySet(ebiInit->banks, ebiLineALE, ebiInit->alePolarity);
76  /* Set polarity of write enable */
77  EBI_BankPolaritySet(ebiInit->banks, ebiLineWE, ebiInit->wePolarity);
78  /* Set polarity of read enable */
79  EBI_BankPolaritySet(ebiInit->banks, ebiLineRE, ebiInit->rePolarity);
80  /* Set polarity of chip select lines */
81  EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
82  /* Set polarity of byte lane line */
83  EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
84 #else
85  /* Set polarity of address ready */
86  EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
87  /* Set polarity of address latch enable */
88  EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
89  /* Set polarity of write enable */
90  EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
91  /* Set polarity of read enable */
92  EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
93  /* Set polarity of chip select lines */
94  EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
95 #endif
96 
97  /* Configure EBI mode and control settings */
98 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
99  if (ebiInit->banks & EBI_BANK0)
100  {
101  ctrl &= ~(_EBI_CTRL_MODE_MASK
102  | _EBI_CTRL_ARDYEN_MASK
103  | _EBI_CTRL_ARDYTODIS_MASK
104  | _EBI_CTRL_BL_MASK
105  | _EBI_CTRL_NOIDLE_MASK
106  | _EBI_CTRL_BANK0EN_MASK);
107  ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT);
108  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
109  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
110  ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
111  ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
112  if ( ebiInit->enable)
113  {
114  ctrl |= EBI_CTRL_BANK0EN;
115  }
116  }
117  if (ebiInit->banks & EBI_BANK1)
118  {
119  ctrl &= ~(_EBI_CTRL_BL1_MASK
120  | _EBI_CTRL_MODE1_MASK
121  | _EBI_CTRL_ARDY1EN_MASK
122  | _EBI_CTRL_ARDYTO1DIS_MASK
123  | _EBI_CTRL_NOIDLE1_MASK
124  | _EBI_CTRL_BANK1EN_MASK);
125  ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
126  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
127  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
128  ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
129  ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
130  if ( ebiInit->enable)
131  {
132  ctrl |= EBI_CTRL_BANK1EN;
133  }
134  }
135  if (ebiInit->banks & EBI_BANK2)
136  {
137  ctrl &= ~(_EBI_CTRL_BL2_MASK
138  | _EBI_CTRL_MODE2_MASK
139  | _EBI_CTRL_ARDY2EN_MASK
140  | _EBI_CTRL_ARDYTO2DIS_MASK
141  | _EBI_CTRL_NOIDLE2_MASK
142  | _EBI_CTRL_BANK2EN_MASK);
143  ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT);
144  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
145  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
146  ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
147  ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
148  if ( ebiInit->enable)
149  {
150  ctrl |= EBI_CTRL_BANK2EN;
151  }
152  }
153  if (ebiInit->banks & EBI_BANK3)
154  {
155  ctrl &= ~(_EBI_CTRL_BL3_MASK
156  | _EBI_CTRL_MODE3_MASK
157  | _EBI_CTRL_ARDY3EN_MASK
158  | _EBI_CTRL_ARDYTO3DIS_MASK
159  | _EBI_CTRL_NOIDLE3_MASK
160  | _EBI_CTRL_BANK3EN_MASK);
161  ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
162  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
163  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
164  ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
165  ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
166  if ( ebiInit->enable)
167  {
168  ctrl |= EBI_CTRL_BANK3EN;
169  }
170  }
171 #else
172  ctrl &= ~(_EBI_CTRL_MODE_MASK
173  | _EBI_CTRL_ARDYEN_MASK
174  | _EBI_CTRL_ARDYTODIS_MASK
175  | _EBI_CTRL_BANK0EN_MASK
176  | _EBI_CTRL_BANK1EN_MASK
177  | _EBI_CTRL_BANK2EN_MASK
178  | _EBI_CTRL_BANK3EN_MASK);
179  if ( ebiInit->enable)
180  {
181  if ( ebiInit->banks & EBI_BANK0 )
182  {
183  ctrl |= EBI_CTRL_BANK0EN;
184  }
185  if ( ebiInit->banks & EBI_BANK1 )
186  {
187  ctrl |= EBI_CTRL_BANK1EN;
188  }
189  if ( ebiInit->banks & EBI_BANK2 )
190  {
191  ctrl |= EBI_CTRL_BANK2EN;
192  }
193  if ( ebiInit->banks & EBI_BANK3 )
194  {
195  ctrl |= EBI_CTRL_BANK3EN;
196  }
197  }
198  ctrl |= ebiInit->mode;
199  ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
200  ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
201 #endif
202 
203  /* Configure timing */
204 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
205  EBI_BankReadTimingSet(ebiInit->banks,
206  ebiInit->readSetupCycles,
207  ebiInit->readStrobeCycles,
208  ebiInit->readHoldCycles);
209  EBI_BankReadTimingConfig(ebiInit->banks,
210  ebiInit->readPageMode,
211  ebiInit->readPrefetch,
212  ebiInit->readHalfRE);
213  EBI_BankWriteTimingSet(ebiInit->banks,
214  ebiInit->writeSetupCycles,
215  ebiInit->writeStrobeCycles,
216  ebiInit->writeHoldCycles);
217  EBI_BankWriteTimingConfig(ebiInit->banks,
218  ebiInit->writeBufferDisable,
219  ebiInit->writeHalfWE);
220  EBI_BankAddressTimingSet(ebiInit->banks,
221  ebiInit->addrSetupCycles,
222  ebiInit->addrHoldCycles);
223  EBI_BankAddressTimingConfig(ebiInit->banks,
224  ebiInit->addrHalfALE);
225 #else
226  EBI_ReadTimingSet(ebiInit->readSetupCycles,
227  ebiInit->readStrobeCycles,
228  ebiInit->readHoldCycles);
229  EBI_WriteTimingSet(ebiInit->writeSetupCycles,
230  ebiInit->writeStrobeCycles,
231  ebiInit->writeHoldCycles);
232  EBI_AddressTimingSet(ebiInit->addrSetupCycles,
233  ebiInit->addrHoldCycles);
234 #endif
235 
236  /* Activate new configuration */
237  EBI->CTRL = ctrl;
238 
239  /* Configure Adress Latch Enable */
240  switch (ebiInit->mode)
241  {
242  case ebiModeD16A16ALE:
243  case ebiModeD8A24ALE:
244  /* Address Latch Enable */
245  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
246  break;
247 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
248  case ebiModeD16:
249 #endif
250  case ebiModeD8A8:
251  /* Make sure Address Latch is disabled */
252  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
253  break;
254  }
255 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
256  /* Limit pin enable */
257  EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
258  EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
259  /* Location */
260  EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
261 
262  /* Enable EBI BL pin if necessary */
263  if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
264  {
265  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
266  }
267 #endif
268  /* Enable EBI pins EBI_WEn and EBI_REn */
269  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
270 
271  /* Enable chip select lines */
272  EBI_ChipSelectEnable(ebiInit->csLines, true);
273 }
274 
275 
276 /***************************************************************************/
280 void EBI_Disable(void)
281 {
282  /* Disable pins */
283  EBI->ROUTE = _EBI_ROUTE_RESETVALUE;
284  /* Disable banks */
285  EBI->CTRL = _EBI_CTRL_RESETVALUE;
286 }
287 
288 
289 /***************************************************************************/
299 void EBI_BankEnable(uint32_t banks, bool enable)
300 {
301  if (banks & EBI_BANK0)
302  {
303  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
304  }
305  if (banks & EBI_BANK1)
306  {
307  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
308  }
309  if (banks & EBI_BANK2)
310  {
311  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
312  }
313  if (banks & EBI_BANK3)
314  {
315  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
316  }
317 }
318 
319 
320 /***************************************************************************/
330 uint32_t EBI_BankAddress(uint32_t bank)
331 {
332 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
333  if(EBI->CTRL & EBI_CTRL_ALTMAP)
334  {
335  switch (bank)
336  {
337  case EBI_BANK0:
338  return(EBI_MEM_BASE);
339 
340  case EBI_BANK1:
341  return(EBI_MEM_BASE + 0x10000000UL);
342 
343  case EBI_BANK2:
344  return(EBI_MEM_BASE + 0x20000000UL);
345 
346  case EBI_BANK3:
347  return(EBI_MEM_BASE + 0x30000000UL);
348 
349  default:
350  EFM_ASSERT(0);
351  break;
352  }
353  }
354 #endif
355  switch (bank)
356  {
357  case EBI_BANK0:
358  return(EBI_MEM_BASE);
359 
360  case EBI_BANK1:
361  return(EBI_MEM_BASE + 0x04000000UL);
362 
363  case EBI_BANK2:
364  return(EBI_MEM_BASE + 0x08000000UL);
365 
366  case EBI_BANK3:
367  return(EBI_MEM_BASE + 0x0C000000UL);
368 
369  default:
370  EFM_ASSERT(0);
371  break;
372  }
373  return 0;
374 }
375 
376 
377 /***************************************************************************/
387 void EBI_ChipSelectEnable(uint32_t cs, bool enable)
388 {
389  if (cs & EBI_CS0)
390  {
391  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
392  }
393  if (cs & EBI_CS1)
394  {
395  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
396  }
397  if (cs & EBI_CS2)
398  {
399  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
400  }
401  if (cs & EBI_CS3)
402  {
403  BUS_RegBitWrite(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
404  }
405 }
406 
407 
408 /***************************************************************************/
418 void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
419 {
420  switch (line)
421  {
422  case ebiLineARDY:
423  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
424  break;
425  case ebiLineALE:
426  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
427  break;
428  case ebiLineWE:
429  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
430  break;
431  case ebiLineRE:
432  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
433  break;
434  case ebiLineCS:
435  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
436  break;
437 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
438  case ebiLineBL:
439  BUS_RegBitWrite(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
440  break;
441  case ebiLineTFTVSync:
442  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
443  break;
444  case ebiLineTFTHSync:
445  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
446  break;
447  case ebiLineTFTDataEn:
448  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
449  break;
450  case ebiLineTFTDClk:
451  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
452  break;
453  case ebiLineTFTCS:
454  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
455  break;
456 #endif
457  default:
458  EFM_ASSERT(0);
459  break;
460  }
461 }
462 
463 
464 /***************************************************************************/
478 void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
479 {
480  uint32_t readTiming;
481 
482  /* Check that timings are within limits */
483  EFM_ASSERT(setupCycles < 4);
484  EFM_ASSERT(strobeCycles < 16);
485  EFM_ASSERT(holdCycles < 4);
486 
487  /* Configure timing values */
488  readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
489  | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
490  | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
491 
492 
493  EBI->RDTIMING = (EBI->RDTIMING
494  & ~(_EBI_RDTIMING_RDSETUP_MASK
495  | _EBI_RDTIMING_RDSTRB_MASK
496  | _EBI_RDTIMING_RDHOLD_MASK))
497  | readTiming;
498 }
499 
500 
501 /***************************************************************************/
514 void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
515 {
516  uint32_t writeTiming;
517 
518  /* Check that timings are within limits */
519  EFM_ASSERT(setupCycles < 4);
520  EFM_ASSERT(strobeCycles < 16);
521  EFM_ASSERT(holdCycles < 4);
522 
523  /* Configure timing values */
524  writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
525  | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
526  | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
527 
528  EBI->WRTIMING = (EBI->WRTIMING
529  & ~(_EBI_WRTIMING_WRSETUP_MASK
530  | _EBI_WRTIMING_WRSTRB_MASK
531  | _EBI_WRTIMING_WRHOLD_MASK))
532  | writeTiming;
533 }
534 
535 
536 /***************************************************************************/
547 void EBI_AddressTimingSet(int setupCycles, int holdCycles)
548 {
549  uint32_t addressLatchTiming;
550 
551  /* Check that timing values are within limits */
552  EFM_ASSERT(setupCycles < 4);
553  EFM_ASSERT(holdCycles < 4);
554 
555  /* Configure address latch timing values */
556  addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
557  | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
558 
559  EBI->ADDRTIMING = (EBI->ADDRTIMING
560  & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
561  | _EBI_ADDRTIMING_ADDRHOLD_MASK))
562  | addressLatchTiming;
563 }
564 
565 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
566 /***************************************************************************/
573 void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
574 {
575  uint32_t ctrl;
576 
577  /* Configure base address for frame buffer offset to EBI bank */
578  EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset);
579 
580  /* Configure display size and porch areas */
581  EBI_TFTSizeSet(ebiTFTInit->hsize,
582  ebiTFTInit->vsize);
583  EBI_TFTHPorchSet(ebiTFTInit->hPorchFront,
584  ebiTFTInit->hPorchBack,
585  ebiTFTInit->hPulseWidth);
586  EBI_TFTVPorchSet(ebiTFTInit->vPorchFront,
587  ebiTFTInit->vPorchBack,
588  ebiTFTInit->vPulseWidth);
589 
590  /* Configure timing settings */
591  EBI_TFTTimingSet(ebiTFTInit->dclkPeriod,
592  ebiTFTInit->startPosition,
593  ebiTFTInit->setupCycles,
594  ebiTFTInit->holdCycles);
595 
596  /* Configure line polarity settings */
597  EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity);
598  EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity);
599  EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity);
600  EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity);
601  EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity);
602 
603  /* Main control, EBI bank select, mask and blending configuration */
604  ctrl = (uint32_t)ebiTFTInit->bank
605  | (uint32_t)ebiTFTInit->width
606  | (uint32_t)ebiTFTInit->colSrc
607  | (uint32_t)ebiTFTInit->interleave
608  | (uint32_t)ebiTFTInit->fbTrigger
609  | (uint32_t)(ebiTFTInit->shiftDClk == true
610  ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0)
611  | (uint32_t)ebiTFTInit->maskBlend
612  | (uint32_t)ebiTFTInit->driveMode;
613 
614  EBI->TFTCTRL = ctrl;
615 
616  /* Enable TFT pins */
617  if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
618  {
619  EBI->ROUTE |= EBI_ROUTE_TFTPEN;
620  }
621 }
622 
623 
624 /***************************************************************************/
633 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
634 {
635  EFM_ASSERT((horizontal-1) < 1024);
636  EFM_ASSERT((vertical-1) < 1024);
637 
638  EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT)
639  | ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
640 }
641 
642 /***************************************************************************/
653 void EBI_TFTHPorchSet(int front, int back, int pulseWidth)
654 {
655  EFM_ASSERT(front < 256);
656  EFM_ASSERT(back < 256);
657  EFM_ASSERT((pulseWidth-1) < 128);
658 
659  EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT)
660  | (back << _EBI_TFTHPORCH_HBPORCH_SHIFT)
661  | ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
662 }
663 
664 
665 /***************************************************************************/
676 void EBI_TFTVPorchSet(int front, int back, int pulseWidth)
677 {
678  EFM_ASSERT(front < 256);
679  EFM_ASSERT(back < 256);
680  EFM_ASSERT((pulseWidth-1) < 128);
681 
682  EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT)
683  | (back << _EBI_TFTVPORCH_VBPORCH_SHIFT)
684  | ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
685 }
686 
687 
688 /***************************************************************************/
704 void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
705 {
706  EFM_ASSERT(dclkPeriod < 2048);
707  EFM_ASSERT(start < 2048);
708  EFM_ASSERT(setup < 4);
709  EFM_ASSERT(hold < 4);
710 
711  EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT)
712  | (start << _EBI_TFTTIMING_TFTSTART_SHIFT)
713  | (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT)
714  | (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
715 }
716 #endif
717 
718 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
719 /***************************************************************************/
735 void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
736 {
737  /* Verify only valid banks are used */
738  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
739 
740  /* Configure read operation parameters */
741  if( banks & EBI_BANK0 )
742  {
743  BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
744  BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
745  BUS_RegBitWrite(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
746  }
747  if( banks & EBI_BANK1 )
748  {
749  BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
750  BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
751  BUS_RegBitWrite(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
752  }
753  if( banks & EBI_BANK2 )
754  {
755  BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
756  BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
757  BUS_RegBitWrite(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
758  }
759  if( banks & EBI_BANK3 )
760  {
761  BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
762  BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
763  BUS_RegBitWrite(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
764  }
765 }
766 
767 /***************************************************************************/
784 void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
785 {
786  uint32_t readTiming;
787 
788  /* Verify only valid banks are used */
789  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
790 
791  /* Check that timings are within limits */
792  EFM_ASSERT(setupCycles < 4);
793  EFM_ASSERT(strobeCycles < 64);
794  EFM_ASSERT(holdCycles < 4);
795 
796  /* Configure timing values */
797  readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT)
798  | (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT)
799  | (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
800 
801  if (banks & EBI_BANK0)
802  {
803  EBI->RDTIMING = (EBI->RDTIMING
804  & ~(_EBI_RDTIMING_RDSETUP_MASK
805  | _EBI_RDTIMING_RDSTRB_MASK
806  | _EBI_RDTIMING_RDHOLD_MASK))
807  | readTiming;
808  }
809  if (banks & EBI_BANK1)
810  {
811  EBI->RDTIMING1 = (EBI->RDTIMING1
812  & ~(_EBI_RDTIMING1_RDSETUP_MASK
813  | _EBI_RDTIMING1_RDSTRB_MASK
814  | _EBI_RDTIMING1_RDHOLD_MASK))
815  | readTiming;
816  }
817  if (banks & EBI_BANK2)
818  {
819  EBI->RDTIMING2 = (EBI->RDTIMING2
820  & ~(_EBI_RDTIMING2_RDSETUP_MASK
821  | _EBI_RDTIMING2_RDSTRB_MASK
822  | _EBI_RDTIMING2_RDHOLD_MASK))
823  | readTiming;
824  }
825  if (banks & EBI_BANK3)
826  {
827  EBI->RDTIMING3 = (EBI->RDTIMING3
828  & ~(_EBI_RDTIMING3_RDSETUP_MASK
829  | _EBI_RDTIMING3_RDSTRB_MASK
830  | _EBI_RDTIMING3_RDHOLD_MASK))
831  | readTiming;
832  }
833 }
834 
835 
836 /***************************************************************************/
849 void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE)
850 {
851  /* Verify only valid banks are used */
852  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
853 
854  /* Configure write operation parameters */
855  if( banks & EBI_BANK0 )
856  {
857  BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
858  BUS_RegBitWrite(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
859  }
860  if( banks & EBI_BANK1 )
861  {
862  BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
863  BUS_RegBitWrite(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
864  }
865  if( banks & EBI_BANK2 )
866  {
867  BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
868  BUS_RegBitWrite(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
869  }
870  if( banks & EBI_BANK3 )
871  {
872  BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
873  BUS_RegBitWrite(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
874  }
875 }
876 
877 
878 /***************************************************************************/
894 void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
895 {
896  uint32_t writeTiming;
897 
898  /* Verify only valid banks are used */
899  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
900 
901  /* Check that timings are within limits */
902  EFM_ASSERT(setupCycles < 4);
903  EFM_ASSERT(strobeCycles < 64);
904  EFM_ASSERT(holdCycles < 4);
905 
906  /* Configure timing values */
907  writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT)
908  | (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT)
909  | (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
910 
911  if (banks & EBI_BANK0)
912  {
913  EBI->WRTIMING = (EBI->WRTIMING
914  & ~(_EBI_WRTIMING_WRSETUP_MASK
915  | _EBI_WRTIMING_WRSTRB_MASK
916  | _EBI_WRTIMING_WRHOLD_MASK))
917  | writeTiming;
918  }
919  if (banks & EBI_BANK1)
920  {
921  EBI->WRTIMING1 = (EBI->WRTIMING1
922  & ~(_EBI_WRTIMING1_WRSETUP_MASK
923  | _EBI_WRTIMING1_WRSTRB_MASK
924  | _EBI_WRTIMING1_WRHOLD_MASK))
925  | writeTiming;
926  }
927  if (banks & EBI_BANK2)
928  {
929  EBI->WRTIMING2 = (EBI->WRTIMING2
930  & ~(_EBI_WRTIMING2_WRSETUP_MASK
931  | _EBI_WRTIMING2_WRSTRB_MASK
932  | _EBI_WRTIMING2_WRHOLD_MASK))
933  | writeTiming;
934  }
935  if (banks & EBI_BANK3)
936  {
937  EBI->WRTIMING3 = (EBI->WRTIMING3
938  & ~(_EBI_WRTIMING3_WRSETUP_MASK
939  | _EBI_WRTIMING3_WRSTRB_MASK
940  | _EBI_WRTIMING3_WRHOLD_MASK))
941  | writeTiming;
942  }
943 }
944 
945 
946 /***************************************************************************/
956 void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE)
957 {
958  /* Verify only valid banks are used */
959  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
960 
961  if( banks & EBI_BANK0 )
962  {
963  BUS_RegBitWrite(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
964  }
965  if( banks & EBI_BANK1 )
966  {
967  BUS_RegBitWrite(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
968  }
969  if( banks & EBI_BANK2 )
970  {
971  BUS_RegBitWrite(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
972  }
973  if( banks & EBI_BANK3 )
974  {
975  BUS_RegBitWrite(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
976  }
977 }
978 
979 
980 /***************************************************************************/
994 void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles)
995 {
996  uint32_t addressLatchTiming;
997 
998  /* Verify only valid banks are used */
999  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
1000 
1001  /* Check that timing values are within limits */
1002  EFM_ASSERT(setupCycles < 4);
1003  EFM_ASSERT(holdCycles < 4);
1004 
1005  /* Configure address latch timing values */
1006  addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT)
1007  | (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
1008 
1009  if (banks & EBI_BANK0)
1010  {
1011  EBI->ADDRTIMING = (EBI->ADDRTIMING
1012  & ~(_EBI_ADDRTIMING_ADDRSETUP_MASK
1013  | _EBI_ADDRTIMING_ADDRHOLD_MASK))
1014  | addressLatchTiming;
1015  }
1016  if (banks & EBI_BANK1)
1017  {
1018  EBI->ADDRTIMING1 = (EBI->ADDRTIMING1
1019  & ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK
1020  | _EBI_ADDRTIMING1_ADDRHOLD_MASK))
1021  | addressLatchTiming;
1022  }
1023  if (banks & EBI_BANK2)
1024  {
1025  EBI->ADDRTIMING2 = (EBI->ADDRTIMING2
1026  & ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK
1027  | _EBI_ADDRTIMING2_ADDRHOLD_MASK))
1028  | addressLatchTiming;
1029  }
1030  if (banks & EBI_BANK3)
1031  {
1032  EBI->ADDRTIMING3 = (EBI->ADDRTIMING3
1033  & ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK
1034  | _EBI_ADDRTIMING3_ADDRHOLD_MASK))
1035  | addressLatchTiming;
1036  }
1037 }
1038 
1039 
1040 /***************************************************************************/
1054 void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
1055 {
1056  uint32_t bankSet = 0;
1057  volatile uint32_t *polRegister = 0;
1058 
1059  /* Verify only valid banks are used */
1060  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
1061 
1062  while (banks)
1063  {
1064 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1065  if (banks & EBI_BANK0)
1066  {
1067  polRegister = &EBI->POLARITY;
1068  bankSet = EBI_BANK0;
1069  }
1070  if (banks & EBI_BANK1)
1071  {
1072  polRegister = &EBI->POLARITY1;
1073  bankSet = EBI_BANK1;
1074  }
1075  if (banks & EBI_BANK2)
1076  {
1077  polRegister = &EBI->POLARITY2;
1078  bankSet = EBI_BANK2;
1079  }
1080  if (banks & EBI_BANK3)
1081  {
1082  polRegister = &EBI->POLARITY3;
1083  bankSet = EBI_BANK3;
1084  }
1085 #else
1086  polRegister = &EBI->POLARITY;
1087  banks = 0;
1088 #endif
1089 
1090  /* What line to configure */
1091  switch (line)
1092  {
1093  case ebiLineARDY:
1094  BUS_RegBitWrite(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
1095  break;
1096  case ebiLineALE:
1097  BUS_RegBitWrite(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
1098  break;
1099  case ebiLineWE:
1100  BUS_RegBitWrite(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity);
1101  break;
1102  case ebiLineRE:
1103  BUS_RegBitWrite(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity);
1104  break;
1105  case ebiLineCS:
1106  BUS_RegBitWrite(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
1107  break;
1108 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
1109  case ebiLineBL:
1110  BUS_RegBitWrite(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
1111  break;
1112  case ebiLineTFTVSync:
1113  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
1114  break;
1115  case ebiLineTFTHSync:
1116  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
1117  break;
1118  case ebiLineTFTDataEn:
1119  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
1120  break;
1121  case ebiLineTFTDClk:
1122  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
1123  break;
1124  case ebiLineTFTCS:
1125  BUS_RegBitWrite(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
1126  break;
1127 #endif
1128  default:
1129  EFM_ASSERT(0);
1130  break;
1131  }
1132  banks = banks & ~bankSet;
1133  }
1134 }
1135 
1136 
1137 /***************************************************************************/
1148 void EBI_BankByteLaneEnable(uint32_t banks, bool enable)
1149 {
1150  /* Verify only valid banks are used */
1151  EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
1152 
1153  /* Configure byte lane support for each selected bank */
1154  if (banks & EBI_BANK0)
1155  {
1156  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
1157  }
1158  if (banks & EBI_BANK1)
1159  {
1160  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
1161  }
1162  if (banks & EBI_BANK2)
1163  {
1164  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
1165  }
1166  if (banks & EBI_BANK3)
1167  {
1168  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
1169  }
1170 }
1171 
1172 
1173 /***************************************************************************/
1181 void EBI_AltMapEnable(bool enable)
1182 {
1183  BUS_RegBitWrite(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable);
1184 }
1185 
1186 #endif
1187 
1191 #endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */
em_assert.h
Emlib peripheral API "assert" implementation.
em_bus.h
RAM and peripheral bit-field set and clear API.
em_ebi.h
External Bus Iterface (EBI) peripheral API.
BUS_RegBitWrite
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:148