37 #if defined( CSEN_COUNT ) && ( CSEN_COUNT > 0 )
89 csenCmpModeDisabled = 0,
92 csenCmpModeGreater = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_GT,
95 csenCmpModeLessOrEqual = CSEN_CTRL_CMPEN | CSEN_CTRL_CMPPOL_LTE,
98 csenCmpModeEMAWindow = CSEN_CTRL_EMACMPEN,
99 } CSEN_CmpMode_TypeDef;
106 csenConvSelSAR = CSEN_CTRL_CONVSEL_SAR,
109 csenConvSelSARChop = CSEN_CTRL_CONVSEL_SAR | CSEN_CTRL_CHOPEN_ENABLE,
112 csenConvSelDM = CSEN_CTRL_CONVSEL_DM,
115 csenConvSelDMChop = CSEN_CTRL_CONVSEL_DM | CSEN_CTRL_CHOPEN_ENABLE,
116 } CSEN_ConvSel_TypeDef;
123 csenSampleModeBonded = CSEN_CTRL_CM_SGL | CSEN_CTRL_MCEN_ENABLE,
126 csenSampleModeSingle = CSEN_CTRL_CM_SGL,
129 csenSampleModeScan = CSEN_CTRL_CM_SCAN,
132 csenSampleModeContBonded = CSEN_CTRL_CM_CONTSGL | CSEN_CTRL_MCEN_ENABLE,
135 csenSampleModeContSingle = CSEN_CTRL_CM_CONTSGL,
138 csenSampleModeContScan = CSEN_CTRL_CM_CONTSCAN,
139 } CSEN_SampleMode_TypeDef;
145 csenTrigSelPRS = _CSEN_CTRL_STM_PRS,
146 csenTrigSelTimer = _CSEN_CTRL_STM_TIMER,
147 csenTrigSelStart = _CSEN_CTRL_STM_START,
148 } CSEN_TrigSel_TypeDef;
154 csenAccMode1 = _CSEN_CTRL_ACU_ACC1,
155 csenAccMode2 = _CSEN_CTRL_ACU_ACC2,
156 csenAccMode4 = _CSEN_CTRL_ACU_ACC4,
157 csenAccMode8 = _CSEN_CTRL_ACU_ACC8,
158 csenAccMode16 = _CSEN_CTRL_ACU_ACC16,
159 csenAccMode32 = _CSEN_CTRL_ACU_ACC32,
160 csenAccMode64 = _CSEN_CTRL_ACU_ACC64,
161 } CSEN_AccMode_TypeDef;
167 csenSARRes10 = _CSEN_CTRL_SARCR_CLK10,
168 csenSARRes12 = _CSEN_CTRL_SARCR_CLK12,
169 csenSARRes14 = _CSEN_CTRL_SARCR_CLK14,
170 csenSARRes16 = _CSEN_CTRL_SARCR_CLK16,
171 } CSEN_SARRes_TypeDef;
177 csenDMRes10 = _CSEN_DMCFG_CRMODE_DM10,
178 csenDMRes12 = _CSEN_DMCFG_CRMODE_DM12,
179 csenDMRes14 = _CSEN_DMCFG_CRMODE_DM14,
180 csenDMRes16 = _CSEN_DMCFG_CRMODE_DM16,
181 } CSEN_DMRes_TypeDef;
188 csenPCPrescaleDiv1 = _CSEN_TIMCTRL_PCPRESC_DIV1,
189 csenPCPrescaleDiv2 = _CSEN_TIMCTRL_PCPRESC_DIV2,
190 csenPCPrescaleDiv4 = _CSEN_TIMCTRL_PCPRESC_DIV4,
191 csenPCPrescaleDiv8 = _CSEN_TIMCTRL_PCPRESC_DIV8,
192 csenPCPrescaleDiv16 = _CSEN_TIMCTRL_PCPRESC_DIV16,
193 csenPCPrescaleDiv32 = _CSEN_TIMCTRL_PCPRESC_DIV32,
194 csenPCPrescaleDiv64 = _CSEN_TIMCTRL_PCPRESC_DIV64,
195 csenPCPrescaleDiv128 = _CSEN_TIMCTRL_PCPRESC_DIV128,
196 } CSEN_PCPrescale_TypeDef;
202 csenEMASampleW1 = _CSEN_EMACTRL_EMASAMPLE_W1,
203 csenEMASampleW2 = _CSEN_EMACTRL_EMASAMPLE_W2,
204 csenEMASampleW4 = _CSEN_EMACTRL_EMASAMPLE_W4,
205 csenEMASampleW8 = _CSEN_EMACTRL_EMASAMPLE_W8,
206 csenEMASampleW16 = _CSEN_EMACTRL_EMASAMPLE_W16,
207 csenEMASampleW32 = _CSEN_EMACTRL_EMASAMPLE_W32,
208 csenEMASampleW64 = _CSEN_EMACTRL_EMASAMPLE_W64,
209 } CSEN_EMASample_TypeDef;
215 csenResetPhaseSel0 = 0,
216 csenResetPhaseSel1 = 1,
217 csenResetPhaseSel2 = 2,
218 csenResetPhaseSel3 = 3,
219 csenResetPhaseSel4 = 4,
220 csenResetPhaseSel5 = 5,
221 csenResetPhaseSel6 = 6,
222 csenResetPhaseSel7 = 7,
223 } CSEN_ResetPhaseSel_TypeDef;
229 csenDriveSelFull = 0,
237 } CSEN_DriveSel_TypeDef;
251 } CSEN_GainSel_TypeDef;
257 csenPRSSELCh0 = _CSEN_PRSSEL_PRSSEL_PRSCH0,
258 csenPRSSELCh1 = _CSEN_PRSSEL_PRSSEL_PRSCH1,
259 csenPRSSELCh2 = _CSEN_PRSSEL_PRSSEL_PRSCH2,
260 csenPRSSELCh3 = _CSEN_PRSSEL_PRSSEL_PRSCH3,
261 csenPRSSELCh4 = _CSEN_PRSSEL_PRSSEL_PRSCH4,
262 csenPRSSELCh5 = _CSEN_PRSSEL_PRSSEL_PRSCH5,
263 csenPRSSELCh6 = _CSEN_PRSSEL_PRSSEL_PRSCH6,
264 csenPRSSELCh7 = _CSEN_PRSSEL_PRSSEL_PRSCH7,
265 csenPRSSELCh8 = _CSEN_PRSSEL_PRSSEL_PRSCH8,
266 csenPRSSELCh9 = _CSEN_PRSSEL_PRSSEL_PRSCH9,
267 csenPRSSELCh10 = _CSEN_PRSSEL_PRSSEL_PRSCH10,
268 csenPRSSELCh11 = _CSEN_PRSSEL_PRSSEL_PRSCH11,
269 } CSEN_PRSSel_TypeDef;
275 csenInputSelDefault = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_DEFAULT,
276 csenInputSelAPORT1CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH0TO7,
277 csenInputSelAPORT1CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH8TO15,
278 csenInputSelAPORT1CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH16TO23,
279 csenInputSelAPORT1CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT1CH24TO31,
280 csenInputSelAPORT3CH0TO7 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH0TO7,
281 csenInputSelAPORT3CH8TO15 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH8TO15,
282 csenInputSelAPORT3CH16TO23 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH16TO23,
283 csenInputSelAPORT3CH24TO31 = _CSEN_SCANINPUTSEL0_INPUT0TO7SEL_APORT3CH24TO31,
284 } CSEN_InputSel_TypeDef;
290 csenSingleSelDefault = _CSEN_SINGLECTRL_SINGLESEL_DEFAULT,
291 csenSingleSelAPORT1XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH0,
292 csenSingleSelAPORT1YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH1,
293 csenSingleSelAPORT1XCH2 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH2,
294 csenSingleSelAPORT1YCH3 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH3,
295 csenSingleSelAPORT1XCH4 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH4,
296 csenSingleSelAPORT1YCH5 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH5,
297 csenSingleSelAPORT1XCH6 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH6,
298 csenSingleSelAPORT1YCH7 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH7,
299 csenSingleSelAPORT1XCH8 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH8,
300 csenSingleSelAPORT1YCH9 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH9,
301 csenSingleSelAPORT1XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH10,
302 csenSingleSelAPORT1YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH11,
303 csenSingleSelAPORT1XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH12,
304 csenSingleSelAPORT1YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH13,
305 csenSingleSelAPORT1XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH14,
306 csenSingleSelAPORT1YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH15,
307 csenSingleSelAPORT1XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH16,
308 csenSingleSelAPORT1YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH17,
309 csenSingleSelAPORT1XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH18,
310 csenSingleSelAPORT1YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH19,
311 csenSingleSelAPORT1XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH20,
312 csenSingleSelAPORT1YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH21,
313 csenSingleSelAPORT1XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH22,
314 csenSingleSelAPORT1YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH23,
315 csenSingleSelAPORT1XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH24,
316 csenSingleSelAPORT1YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH25,
317 csenSingleSelAPORT1XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH26,
318 csenSingleSelAPORT1YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH27,
319 csenSingleSelAPORT1XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH28,
320 csenSingleSelAPORT1YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH29,
321 csenSingleSelAPORT1XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT1XCH30,
322 csenSingleSelAPORT1YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT1YCH31,
323 csenSingleSelAPORT3XCH0 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH0,
324 csenSingleSelAPORT3YCH1 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH1,
325 csenSingleSelAPORT3XCH2 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH2,
326 csenSingleSelAPORT3YCH3 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH3,
327 csenSingleSelAPORT3XCH4 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH4,
328 csenSingleSelAPORT3YCH5 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH5,
329 csenSingleSelAPORT3XCH6 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH6,
330 csenSingleSelAPORT3YCH7 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH7,
331 csenSingleSelAPORT3XCH8 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH8,
332 csenSingleSelAPORT3YCH9 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH9,
333 csenSingleSelAPORT3XCH10 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH10,
334 csenSingleSelAPORT3YCH11 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH11,
335 csenSingleSelAPORT3XCH12 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH12,
336 csenSingleSelAPORT3YCH13 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH13,
337 csenSingleSelAPORT3XCH14 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH14,
338 csenSingleSelAPORT3YCH15 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH15,
339 csenSingleSelAPORT3XCH16 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH16,
340 csenSingleSelAPORT3YCH17 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH17,
341 csenSingleSelAPORT3XCH18 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH18,
342 csenSingleSelAPORT3YCH19 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH19,
343 csenSingleSelAPORT3XCH20 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH20,
344 csenSingleSelAPORT3YCH21 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH21,
345 csenSingleSelAPORT3XCH22 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH22,
346 csenSingleSelAPORT3YCH23 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH23,
347 csenSingleSelAPORT3XCH24 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH24,
348 csenSingleSelAPORT3YCH25 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH25,
349 csenSingleSelAPORT3XCH26 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH26,
350 csenSingleSelAPORT3YCH27 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH27,
351 csenSingleSelAPORT3XCH28 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH28,
352 csenSingleSelAPORT3YCH29 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH29,
353 csenSingleSelAPORT3XCH30 = _CSEN_SINGLECTRL_SINGLESEL_APORT3XCH30,
354 csenSingleSelAPORT3YCH31 = _CSEN_SINGLECTRL_SINGLESEL_APORT3YCH31,
355 } CSEN_SingleSel_TypeDef;
381 CSEN_PCPrescale_TypeDef pcPrescale;
384 CSEN_PRSSel_TypeDef prsSel;
387 CSEN_InputSel_TypeDef input0To7;
388 CSEN_InputSel_TypeDef input8To15;
389 CSEN_InputSel_TypeDef input16To23;
390 CSEN_InputSel_TypeDef input24To31;
391 CSEN_InputSel_TypeDef input32To39;
392 CSEN_InputSel_TypeDef input40To47;
393 CSEN_InputSel_TypeDef input48To55;
394 CSEN_InputSel_TypeDef input56To63;
397 #define CSEN_INIT_DEFAULT \
404 csenPCPrescaleDiv1, \
406 csenInputSelAPORT1CH0TO7, \
407 csenInputSelAPORT1CH8TO15, \
408 csenInputSelAPORT1CH16TO23, \
409 csenInputSelAPORT1CH24TO31, \
410 csenInputSelAPORT3CH0TO7, \
411 csenInputSelAPORT3CH8TO15, \
412 csenInputSelAPORT3CH16TO23, \
413 csenInputSelAPORT3CH24TO31, \
421 CSEN_SampleMode_TypeDef sampleMode;
424 CSEN_TrigSel_TypeDef trigSel;
433 CSEN_AccMode_TypeDef accMode;
436 CSEN_EMASample_TypeDef emaSample;
439 CSEN_CmpMode_TypeDef cmpMode;
445 CSEN_SingleSel_TypeDef singleSel;
463 CSEN_ConvSel_TypeDef convSel;
466 CSEN_SARRes_TypeDef sarRes;
469 CSEN_DMRes_TypeDef dmRes;
473 uint8_t dmIterPerCycle;
489 CSEN_ResetPhaseSel_TypeDef resetPhase;
493 CSEN_DriveSel_TypeDef driveSel;
496 CSEN_GainSel_TypeDef gainSel;
497 } CSEN_InitMode_TypeDef;
499 #define CSEN_INITMODE_DEFAULT \
501 csenSampleModeSingle, \
507 csenCmpModeDisabled, \
509 csenSingleSelDefault, \
520 csenResetPhaseSel0, \
545 __STATIC_INLINE uint32_t CSEN_DataGet(CSEN_TypeDef *csen)
563 __STATIC_INLINE uint32_t CSEN_EMAGet(CSEN_TypeDef *csen)
565 return (csen->EMA & _CSEN_EMA_EMA_MASK);
581 __STATIC_INLINE
void CSEN_EMASet(CSEN_TypeDef *csen, uint32_t ema)
583 csen->EMA = ema & _CSEN_EMA_EMA_MASK;
593 __STATIC_INLINE
void CSEN_Disable(CSEN_TypeDef *csen)
605 __STATIC_INLINE
void CSEN_Enable(CSEN_TypeDef *csen)
610 void CSEN_DMBaselineSet(CSEN_TypeDef *csen, uint32_t up, uint32_t down);
611 void CSEN_Init(CSEN_TypeDef *csen,
const CSEN_Init_TypeDef *init);
612 void CSEN_InitMode(CSEN_TypeDef *csen,
const CSEN_InitMode_TypeDef *init);
613 void CSEN_Reset(CSEN_TypeDef *csen);
627 __STATIC_INLINE
void CSEN_IntClear(CSEN_TypeDef *csen, uint32_t flags)
644 __STATIC_INLINE
void CSEN_IntDisable(CSEN_TypeDef *csen, uint32_t flags)
666 __STATIC_INLINE
void CSEN_IntEnable(CSEN_TypeDef *csen, uint32_t flags)
686 __STATIC_INLINE uint32_t CSEN_IntGet(CSEN_TypeDef *csen)
711 __STATIC_INLINE uint32_t CSEN_IntGetEnabled(CSEN_TypeDef *csen)
720 return csen->IF & ien;
735 __STATIC_INLINE
void CSEN_IntSet(CSEN_TypeDef *csen, uint32_t flags)
751 __STATIC_INLINE
bool CSEN_IsBusy(CSEN_TypeDef *csen)
753 return (
bool)(csen->STATUS & _CSEN_STATUS_CSENBUSY_MASK);
764 __STATIC_INLINE
void CSEN_Start(CSEN_TypeDef *csen)
766 csen->CMD = CSEN_CMD_START;
RAM and peripheral bit-field set and clear API.
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.