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si7210_regs.h
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/***************************************************************************/
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#ifndef __SI7210_REGS_H_
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#define __SI7210_REGS_H_
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/***************************************************************************/
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/***************************************************************************/
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#define SI7210_REG_ADDR_HREVID 0xC0
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#define SI7210_REG_ADDR_DSPSIGM 0xC1
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#define SI7210_REG_ADDR_DSPSIGL 0xC2
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#define SI7210_REG_ADDR_DSPSIGSEL 0xC3
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#define SI7210_REG_ADDR_POWER_CTRL 0xC4
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#define SI7210_REG_ADDR_ARAUTOINC 0xC5
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#define SI7210_REG_ADDR_CTRL1 0xC6
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#define SI7210_REG_ADDR_CTRL2 0xC7
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#define SI7210_REG_ADDR_SLTIME 0xC8
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#define SI7210_REG_ADDR_CTRL3 0xC9
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#define SI7210_REG_ADDR_A0 0xCA
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#define SI7210_REG_ADDR_A1 0xCB
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#define SI7210_REG_ADDR_A2 0xCC
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#define SI7210_REG_ADDR_CTRL4 0xCD
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#define SI7210_REG_ADDR_A3 0xCE
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#define SI7210_REG_ADDR_A4 0xCF
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#define SI7210_REG_ADDR_A5 0xD0
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#define SI7210_REG_ADDR_OTP_ADDR 0xE1
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#define SI7210_REG_ADDR_OTP_DATA 0xE2
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#define SI7210_REG_ADDR_OTP_CTRL 0xE3
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#define SI7210_REG_ADDR_TM_FG 0xE4
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/***************************************************************************/
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#define SI7210_REG_HREVID_REVID_MASK 0x0F
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#define SI7210_REG_HREVID_REVID_SHIFT 0
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#define SI7210_REG_HREVID_CHIPID_MASK 0xF0
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#define SI7210_REG_HREVID_CHIPID_SHIFT 4
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#define SI7210_REG_POWER_CTRL_SLEEP_MASK 0x01
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#define SI7210_REG_POWER_CTRL_SLEEP_SHIFT 0
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#define SI7210_REG_POWER_CTRL_STOP_MASK 0x02
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#define SI7210_REG_POWER_CTRL_STOP_SHIFT 1
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#define SI7210_REG_POWER_CTRL_ONEBURST_MASK 0x04
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#define SI7210_REG_POWER_CTRL_ONEBURST_SHIFT 2
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#define SI7210_REG_POWER_CTRL_USESTORE_MASK 0x08
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#define SI7210_REG_POWER_CTRL_USESTORE_SHIFT 3
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#define SI7210_REG_POWER_CTRL_MEAS_MASK 0x80
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#define SI7210_REG_POWER_CTRL_MEAS_SHIFT 7
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#define SI7210_REG_CTRL1_SW_OP_MASK 0x7F
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#define SI7210_REG_CTRL1_SW_OP_SHIFT 0
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#define SI7210_REG_CTRL1_SW_LOW4FIELD_MASK 0x80
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#define SI7210_REG_CTRL1_SW_LOW4FIELD_SHIFT 7
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#define SI7210_REG_CTRL2_SW_HYST_MASK 0x3F
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#define SI7210_REG_CTRL2_SW_HYST_SHIFT 0
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#define SI7210_REG_CTRL2_SW_FIELDPOLSEL_MASK 0xC0
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#define SI7210_REG_CTRL2_SW_FIELDPOLSEL_SHIFT 6
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#define SI7210_REG_CTRL3_SLTIMEENA_MASK 0x01
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#define SI7210_REG_CTRL3_SLTIMEENA_SHIFT 0
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#define SI7210_REG_CTRL3_SLFAST_MASK 0x02
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#define SI7210_REG_CTRL3_SLFAST_SHIFT 1
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#define SI7210_REG_CTRL3_SW_TAMPER_MASK 0xFC
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#define SI7210_REG_CTRL3_SW_TAMPER_SHIFT 2
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#define SI7210_REG_OTP_CTRL_BUSY_MASK 0x01
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#define SI7210_REG_OTP_CTRL_BUSY_SHIFT 0
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#define SI7210_REG_OTP_CTRL_READ_EN_MASK 0x02
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#define SI7210_REG_OTP_CTRL_READ_EN_SHIFT 1
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/***************************************************************************/
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#define SI7210_OTP_ADDR_CTRL1 0x04
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#define SI7210_OTP_ADDR_CTRL2 0x05
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#define SI7210_OTP_ADDR_SLTIME 0x06
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#define SI7210_OTP_ADDR_CTRL3 0x08
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#define SI7210_OTP_ADDR_POWER_UP_A0 0x09
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#define SI7210_OTP_ADDR_POWER_UP_A1 0x0A
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#define SI7210_OTP_ADDR_POWER_UP_A2 0x0B
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#define SI7210_OTP_ADDR_CTRL4 0x0C
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#define SI7210_OTP_ADDR_POWER_UP_A3 0x0D
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#define SI7210_OTP_ADDR_POWER_UP_A4 0x0E
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#define SI7210_OTP_ADDR_POWER_UP_A5 0x0F
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#define SI7210_OTP_ADDR_BASE_PART_NUMBER 0x14
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#define SI7210_OTP_ADDR_VARIANT 0x15
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#define SI7210_OTP_ADDR_SERIAL_NUMBER 0x18
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#define SI7210_OTP_ADDR_BPERVCAL 0x20
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#define SI7210_OTP_ADDR_COEFFS_20MT 0x21
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#define SI7210_OTP_ADDR_COEFFS_200MT 0x27
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#define SI7210_OTP_ADDR_COEFFS_20MT_NEODYMIUM 0x2D
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#define SI7210_OTP_ADDR_COEFFS_200MT_NEODYMIUM 0x33
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#define SI7210_OTP_ADDR_COEFFS_20MT_CERAMIC 0x39
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#define SI7210_OTP_ADDR_COEFFS_200MT_CERAMIC 0x3F
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#endif
/* __SI7210_REGS_H_ */
hardware
kit
common
bsp
thunderboard
si7210_regs.h
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